Hurry up ALD & ALE People - These articles on Atomic Layer Processing have been made free to download for a limited time!

Hurry up ALD & ALE People - These articles on Atomic Layer Processing have been made free to download for a limited time!

Journal of Vacuum Science & Technology A -  First 2016 Issue Online Special Issue on ALD/ALE 2.322  Impact Factor

Gartner says that 7nm will be delayed and 5nm will be pushed out ot 2023

10 nm FinFET may start to ship as early as end of 2016. However, according to a recent article by Mark Lapedus (at Semiconductor Engineering) Bob Johnson, an analyst at Gartner, projects that 7nm could get pushed out to 2020. "This, in turn, could impact the potential timing of 5nm, if the industry decides to move forward with the technology. “I assume 5nm will happen, but not by 2020,” Johnson said, adding that a viable 5nm process may not appear until the next decade, possibly 2023."

The slow down in scaling is not something new and has been seen for some time now. Above is a forecast presented at 2014 Semicon West with conclusions of the SEMI’s World Fab Forecast - Technology Node Transitions Slowing Below 32 nm. Her you can clearly see that the node transitions has paced slower since 28/32 nm.  The question now is then if the pace will come to a halt.

The current 3 main options for 5nm logic FETs are :

• Gate-All-Around FETs based on III/V Nanowires
• To extend FinFET
• Monolithic 3D and other 2.5D/3D IC technologies

AVS ALE 2016 - Call for Papers, Dublin, July 24-25th

ALE 2016 - Call for Papers!

In conjunction with ALD 2016 in Dublin, Ireland, the AVS Plasma Science and Technology and Thin Film Divisions will be hosting the 3rd workshop on Atomic Layer Etching. 

Deadline: March 18, 2016 : http://ald2016.com/atomic-layer-etching-workshop-overview/

Plenary Speaker
•Ankur Agarwal (Applied Materials)

Invited Speakers
• Steven George, University of Colorado, Boulder
• Dennis van Dorp, IMEC
• Akira Koshiishi, Tokyo Electron
• Kazunori Shinoda, Hitachi Hi-Tech

ALE 2016 Workshop Overview

Extending Moore's law beyond the 10 nm node will increasingly rely on high precision processes employing new materials with high-quality surfaces. Atomic layer etching & atomic layer clean technology is a promising pathway to achieve these fundamental requirements.

In conjunction with ALD 2016 in Dublin, Ireland, the AVS Plasma Science and Technology and Thin Film Divisions will be hosting the 3rd workshop on Atomic Layer Etching. The 2nd ALE workshop was held in 2015, and attracted global participation, with nearly 280 attendees representing both academia and industry. The goals of the meeting are to provide research focus, report progress to-date, and foster collaboration to accelerate this unique capability. Latest findings are expected from experts at major universities, semiconductor manufacturers, and leading equipment suppliers. A broad range of topics are expected, including but not limited to:

• Surface chemical reactions
• Ion energy distributions and control
• Damage-free processes
• Modeling of processes and discharges
• Chemistry synthesis for 'reverse ALD'
• Interesting and new applications for ALE

Workshop Chairs

Bert Ellingboe, Dublin City University (albert.ellingboe@dcu.ie)

Sumit Agarwal, Colorado School of Mines (sagarwal@mines.edu) 

2016 Critical Materials Council (CMC) Seminar – Call for Papers

The Critical Materials Council (CMC) and TECHCET have issued a call for papers to be presented at the “Critical Materials for Device Driven Scaling” Seminar to be held May 5-6, 2016 in Hillsboro, Oregon, USA. Semiconductor manufacturing industry experts from IDMs, OEMS, and materials suppliers will gather to discuss actionable information on critical materials used in HVM fabs, while also looking at issues associated with new materials needed for future devices. Tim G. Hendry, Vice President, Technology & Manufacturing and Group Director of Fab Materials, Intel Corp., will provide the keynote address.

Following the annual members-only CMC meeting to be held May 3-4, the 2016 CMC Seminar is open to the public. Business drives our world, but technology enables the profitable business of manufacturing new devices in IC fabs, and new devices need new materials. In addition to panel discussions, presentation sessions will focus on the following topics:

I. Semiconductor Market Briefing: application-specific demands for devices and materials

II. Tracking the Supply Chain down to Earth, Wind, and Fire: manufacturing and supply chain

III. Emerging Materials Evolutions: alternate logic channels and new memory switches, and

IV. Materials Revolutions: beyond silicon CMOS.

Attendees will include industry experts handling supply-chains, business-development, R&D, and product management, as well as academics and analysts. The early-bird registration fee (before March 15th) for the CMC Seminar is $349; the standard registration fee is $425 (after March 15th). CMC member companies will be attending this meeting, as it is an important part of their membership. Additional information can be found online at http://cmcfabs.org/seminars.

To submit a paper for consideration, please send a 1-page abstract focusing on critical materials supply dynamics by February 29, 2016 to cmcinfo@techcet.com.

The Critical Materials Council for Semiconductor Device Fabricators was originally started by SEMATECH in the early 1990’s, and is now managed by TECHCET. It actively works to identify issues surrounding the supply, availability, accessibility, or lack thereof, of semiconductor process materials, current and emerging, also known as “Critical Materials”. This is done by collectively working to solve common materials related issues in a non-competitive environment. The CMC supports the continuous improvement of the Materials Supply Chain Community for Semiconductor Fabricators. For more information see www.CMCFabs.org .

AVS - Atomic Layer Etching Workshop 2016, 24th-25th July 2016, Dublin, Ireland

Extending Moore’s law beyond the 10nm node will increasingly rely on high precision processes employing new materials with high-quality surfaces. Atomic layer etching & atomic layer clean technology is a promising pathway to achieve these fundamental requirements.

In conjunction with ALD 2016 the AVS Plasma Science and Technology Division will be hosting a workshop on Atomic Layer Etching.  The goals of the meeting are to provide research focus, report progress to-date and foster collaboration to accelerate this unique capability. Latest findings are expected from experts at major universities, semiconductor manufacturers and leading equipment suppliers.

Details regarding the workshop programme will be announced soon.

You can register for ALD2016 (one day or three days, 25-27 July) and the Atomic Layer Etch workshop (one day, 25 July), as well as for the joint ALD/ALE tutorial (half-day, 24 July). As part of the registration process and for tracking purposes, we ask that you indicate your primary interest in Atomic Layer Deposition or Atomic Layer Etching.

Register here.

Ferrotec and JSW AFTY Sign Joint Representation Alliance

Just when I thought that I had them all in my list another ALD company appears to me. Here is a highly interesting Japanese company JSW AFTY, that manufacture CCP ALD tools and also a magical ALD-ECR combination tool - ECR as in Electron Cyclotron Plasma. Check out their press release below on their new joint distribution with US company Ferrotec.

Ferrotec Corporation (JASDAQ: 6890) today announces a joint representation alliance between Ferrotec and JSW AFTY. With this alliance, JSW AFTY will represent Ferrotec's Temescal electron beam evaporators in the Japanese market, and Ferrotec will represent JSW AFTY's systems in the United States. The agreement spans sales, service and support and is expected to provide customers in both markets with an expanded local infrastructure.

With more than 1500 Temescal evaporation systems and over 16,000 E-beam guns and power supplies installed worldwide, Ferrotec's Temescal systems are the leading electron beam evaporators for global compound semiconductor Independent Device Manufacturers (IDMs) and foundries.

JSW AFTY's products include a unique line of Electron Cyclotron Resonance (ECR) Plasma and Atomic Layer Deposition (ALD) systems as well as their Hybrid ALD – ECR Deposition systems.

"We are pleased to be able to partner with the JSW AFTY team to help bring their unique high quality, low temperature and low damage deposition technologies to the US market. JSW AFTY's technology is increasingly important in the production of high power semiconductor laser, MR (MagnetoResistance) head and SAW devices," said Gregg Wallace, Managing Director of Temescal products at Ferrotec "We look forward to this partnership and the opportunity to introduce JSW AFTY's products to both our existing and new customers in USA."

"Ferrotec's Temescal electron beam evaporators have been tremendously adopted in compound semiconductor business field worldwide. By adding their product to our product lineup, we are now able to offer wider range of solutions to our Japanese customers," said Nobuhisa Kobayashi, President of JSW AFTY. "I'm certain that this alliance enables both companies to offer more flexible and perfect services to our customers by using each know-how as well as aftersales service network which have been accumulated for many years."

A Non-FinFET Path to 10nm Globalfoundries’ FD-SOI Alternative

STMicroelectronics and CEA/Leti have been leading an effort in scaling FD-SOI for long now and have recently gotten some muscles in support by fabing it at Samsung (28nm) and Globalfoundries Fab1 in Dresden (22nm). I ran some sub 22 nm development LOTs for one of our customers some years ago and form an ALD high-k point of view this was a a piece of cake. I gave them the same recipe, adjusted the thickness slightly, as the other guys and they didn't complain. That is why I since then always follow news on FD-SOI - it´s such an underdog technology compared to bulk FinFET in terms of ecosystem support and investments but I like underdogs - or  maybe rather medium sized dogs with a big dog attitude. Anyhow here is a recent feature article by GloFo on the topic that is worth reading:

It was the coolest transistor development in many a year. Rather than continually squishing transistor parts closer and closer together, we flipped it to vertical and celebrated the arrival of the FinFET.

Image courtesy GlobalFoundries

Which was great: it gave us a way to keep increasing performance in many of the applications where the value lies in the speed of the circuit. But after the initial party was over and we started picking up the pointy party hats and nursing the hangovers with massive doses of ibuprofen, we started looking at the bill. FinFET is nice, but it’s also expensive. And, while we’re throwing stones, it’s also not so great for analog and RF designers based on the quantized nature of the gate. You can’t increase channel dimensions by 1.5 times; it’s either 1 or 2.

Rutger Wijburg announcing the investment for 22 nm FD-SOI investment at Fab1 in Dresden, Germany. (Picture by Computer-Oiger)

FinFET has been billed as the future of silicon, and Intel jumped on it, meaning everyone else had to as well. But that pounding morning-after headache is pretty strong, and there are folks wishing they had an alternative to FinFET.

Full story here: http://www.eejournal.com/archives/articles/20160118-fdsoi/

Large area Self-Limiting Synthesis of Transition Metal Dichalcogenides by KEIT & Samsung Display

Here is a very interesting report from Korea Evaluation Institute of Industrial Technology (KEIT) supported by Samsung Display Co., Ltd. on self-limiting synthesis of an atomically thin, two dimensional transition metal dichalcogenides in the form of MoS2 for potential use in future display technology. The team was able to manufacture Large-area (~9 cm) mono-, bi-, and tri-layer MoS₂ on a SiO₂ substrate comparable in size to a cellular phone display screen.

Large-area (~9 cm) mono-, bi-, and tri-layer MoS₂ on a SiO₂ substrate comparable in size to a cellular phone display screen. (Picture From: Self-Limiting Layer Synthesis of Transition Metal Dichalcogenides, licensed under a Creative Commons Attribution 4.0 International License.)

As you all know ALD is a self-limiting growth method,however in this case where growth occurs by the formation of multi-layer islands it is difficult to achieve the layer controllability needed when compared to CVD.  That is why the research team states three important findings for ALD growth of 2D layer structured materials:

• Maximizing the self-limiting behavior of the ALD process to achieve layer controllability needed for a 2D structure by careful optimization of the process conditions (e.g., temperature, pressure, exposure of precursor/reactant)
• Careful selection of the precursor and reactant - in this study MoCl₅ and H₂S are used as the precursors.
• Understand the surface characteristics of the material being deposited.

Read all about it in the excellent open source report in published early this year in Scientific Reports:

Self-Limiting Layer Synthesis of Transition Metal Dichalcogenides 

Youngjun Kim, Jeong-Gyu Song, Yong Ju Park, Gyeong Hee Ryu, Su Jeong Lee, Jin Sung Kim, Pyo Jin Jeon, Chang Wan Lee, Whang Je Woo, Taejin Choi, Hanearl Jung, Han-Bo-Ram Lee, Jae-Min Myoung, Seongil Im, Zonghoon Lee, Jong-Hyun Ahn, Jusang Park& Hyungjun Kim

Scientific Reports 6, Article number: 18754 (2016), doi:10.1038/srep18754

This work reports the self-limiting synthesis of an atomically thin, two dimensional transition metal dichalcogenides (2D TMDCs) in the form of MoS2. The layer controllability and large area uniformity essential for electronic and optical device applications is achieved through atomic layer deposition in what is named self-limiting layer synthesis (SLS); a process in which the number of layers is determined by temperature rather than process cycles due to the chemically inactive nature of 2D MoS2. Through spectroscopic and microscopic investigation it is demonstrated that SLS is capable of producing MoS2 with a wafer-scale (~10 cm) layer-number uniformity of more than 90%, which when used as the active layer in a top-gated field-effect transistor, produces an on/off ratio as high as 108. This process is also shown to be applicable to WSe2, with a PN diode fabricated from a MoS2/WSe2 heterostructure exhibiting gate-tunable rectifying characteristics.

ALD History Blog: Wikipedia 15 years - status of WikiALD update

ALD History Blog: Wikipedia 15 years - status of WikiALD update: Wikipedia was launched exactly fifteen years ago, on January 15, 2001 (https://15.wikipedia.org/). Wikipedia and VPHA share much of the same philosophy: both are worldwide efforts based on voluntary work, and both are aimed for collectively creating correct information for everyone's benefit. Today should be a good day to share what we have done already in VPHA related to the Wikipedia ALD history update, Item #11 in the VPHA Publication Plan. These are easy to track back through "view history" tab in Wikipedia.

Please contact us if you want to contribute to this effort or just to point out errors in the current version! 

2016 will be a good year for the ALD Equipment Manaufacturers

According to Seeking Alpha : "In its Q4 report, TSMC (a top-3 chip equipment buyer, along with Intel and Samsung) set a 2016 capex budget of $9B-$10B, a healthy increase over reported 2015 capex of $8.12B. The spending will help finance TSMC's 16nm manufacturing process ramp and the start of production (towards the end of 2016) for its 10nm process."'

If TSMC is investing it means that also the other Foundries will be investing the interesting question is - What does this mean for ALD - to start with the number of ALD process steps are increasing for each node since introduction fo ALD High-k at 45 nm (Intel 2007). At 14/16 nm it is reported that there are more than 10 ALD process steps and at 10 there will maybe be getting closer to 20. Growth are seen in typical CVD applications like:

• Replacement Metal Gate stack (TiN, TaN, TiAl)
• Spacers and liners for e.g. multiple patterning
• Solid state diffusion doping for FinFETs by P and B doped ALD Oxide
• Metallization barriers, liner and seed
• Embedded memory or decoupling capacitors

So when TSMC is increasing its investments in processing equipment it means big business for ALD equipment manufacturers and especially those that are strong in Logic ALD processes like ASM and LAM Research which is dominated by single wafer and mutli-wafer tools rather that batch furnaces (Kokusai, ASM, TEL) more commonly used for commodity products like DRAM and NAND. It will be very interesting to follow how successful Applied Materials will be the coming years with the introduction of their new Olympia ALD Platform using a Spatial ALD technology too drive up through put.

Market estimation  for ALD excluding Large Batch ALD (supplied by e.g. Tokyo Electron, Kokusai, ASM), which is typically reported as LPCVD. (www.asm.com)

A great start for the BALD Blog in 2016 and welcome to all Russian ALD Visitors!

2016 has started of fantastic on the blog with a lot of new visitors - let´s hope it was not based on New Years resolutions since those tend to fade away. Since May 2015 there has been a monthly average of about 10,000 visitors / month but now suddenly there is an influx of visitors that would extrapolate to >15,000 visitors/month if it goes on for another two weeks!

Looking at the statistics it seems that quite many of the new visitors are originating out of Russia and it could be that Russia for the first time reach the same share of visitors as USA who has always been the most common origin for the the blog traffic.

Double-Layered Nanowire to Develop High-Speed Transistor Channel by NIMS and Georgia Institute of Technology

The future of highly scaled semiconductor devices is reaching oout in the third dimension like form DRAM, 3DNAND, 3D Stacking of chips. Recently also Logic made the move by the introduction of FinFETs at 22 nm. It wil be realy interesting to follow this progressing and there are just less limitations than for planar devices. Here is a recent report by AZO Nano on a novel dual layer nanowire transistor that looks like it can be produced by almost standard semiconductor processing methods.

A team of researchers, from the International Center for Materials Nanoarchitectonics of National Institute for Materials Science (NIMS) and the Georgia Institute of Technology, have developed a dual-layered nanowire that comprises a silicon (Si) shell and a germanium (Ge) core.

 Schematic of a vertical transistor and an expanded view of its core-shell nanowire part. (AZONano.com)

Full story: here

CMC Semicanr “Critical Materials for Device Driven Scaling" May 5-6, Hillsboro, OR, USA

“Critical Materials for Device Driven Scaling”

CMC Seminar Overview
The Critical Materials Council Seminar is a two day event from May 5-6 at The Embassy Suites Hotel in Hillsboro, Oregon providing actionable information on materials and supply-chains for current and future semiconductor manufacturing. Business may drive the world, but it is technology which enables the semiconductor business. In short, it is important to understand the dynamics of how materials and technologies enable the scaling of devices in IC fabs. Seminar speakers will provide information on critical materials used in HVM fabs, while also looking at issues and requirements associated with new materials needed for future devices.

Dates: May 5-6, 2016*
Location: Hillsboro, Oregon – The Embassy Suites Hotel
*This is the open forum portion of the CMC regularly scheduled meeting.

Web page: http://cmcfabs.org/seminars/

Keynote Speaker: Tim G. Hendry – VP Technology and Manufacturing & Group Director of Fab Materials, INTEL CORPORATION, “Material Requirements for the Future of Semiconductor Devices”

Four sessions:
I. Semi Market Briefing – Status and growth of Electronic Applications, Semi Devices, Equipment, and Materials
II. Tracking the Supply Chain Down to Earth, Wind and Fire
III. The Emerging Materials Evolution: What’s next in Materials, i.e. ALD / ALE
IV. The Materials Revolution: “The Carbon Generation” 8+ years

• Featuring Speakers from: Materials and Equipment Suppliers, Device Technologists, Market Analysts

Stanford presents Area Selective ALD to Develop Higher Performing, More Energy Efficient Electronics

Press release: Stanford University researchers sponsored by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductor technologies, have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors. 

The Stanford researchers employ the intrinsically selective adsorption of octadecylphosphonic acid self-assembled monolayers on Cu over SiO2 surfaces to selectively create a resist layer only on Cu. ALD is then performed on the patterns to deposit a dielectric film. A mild etchant is subsequently used to selectively remove any residual dielectric film deposited on the Cu surface while leaving the dielectric film on SiO2 unaffected. The selectivity achieved after this treatment, measured by compositional analysis, is found to be 10 times greater than for conventional area selective ALD. "Reprinted (adapted) with permission from (ACS Nano, 2015, 9 (9), pp 8710–8717, DOI: 10.1021/acsnano.5b03125). Copyright (2015) American Chemical Society."
 

Press release Continued :

 

It is well known that next-generation electronic, optoelectronic and sensing devices that contain nanoscale dimensions face increasingly difficult materials and fabrication challenges as the downward scaling of these devices continues. Conventional semiconductor manufacturing processes are time-consuming and expensive, in part due to the need for lithographic patterning. The Stanford research leverages simple ALD and etching processes that eliminate this lithography step and improve selective deposition of dielectric materials by more than 10 times in film thickness compared to similar advanced processes.

Due to difficulties of current top-down fabrication processes that contain multiple deposition, lithography and etching steps, along with problems with misalignment in lithography, using an alternative approach in which the desired materials are directly and selectively deposited would significantly facilitate the process, according to the Stanford team. 

 

 

Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.(Picture from Stanford University)

 

“Our technology is a promising candidate for overcoming the challenges of top-down processing and misalignment because it greatly improves the ability to perform selective deposition of materials. This research introduces a novel processing method to meet the increasingly difficult materials challenges associated with new devices,” said Dr. Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.

Link to Stacy Bent´s Research Group : http://bentgroup.stanford.edu/
 

Current approaches utilize lithography for nanoscale patterning. Using lithography and etching for fabrication of 2D or 3D structures often results in misaligned features and causes a risk of shorting or high resistant areas. However, selective deposition using ALD can reduce these risks and reduce the process time and steps.

Bent explained that selective deposition allows layers of material to be added onto a substrate only where desired without the need for additional lithography steps. However, the high level of selectivity needed for a manufacture-worthy process has not yet been achieved in area selective deposition studies. In addition, most methods for area selective deposition require long processing times.

The Stanford research has been focused on selective deposition of dielectric materials on metal/dielectric patterns. These type of structures can be found in interconnects and back-end-of-line (BEOL) processing. With ALD being used in other stages of the device fabrication process as well, the results from the Stanford experiments can potentially be applied to a variety of nanoscale electronic, optoelectronic and sensing devices.

The research developments occurred during the second year of research on the topic, and the Stanford team is continuing to explore new methods for area selective ALD to improve both selectivity and manufacturability.

“The Stanford team’s research has shown for the first time that, by following selective deposition of a dielectric material using pre-treatment by an inhibitory material, they can significantly reduce the process time (from 48 hours to less than 1 hour) and also improve the limits of selective deposition of dielectrics by more than 10 times,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC.

Beneq ALD - awesome it is

Unbelivable - story from Beneq that was published today on their Blog.

From Beneq Blog: It is a well-known fact that atomic layer deposition provides the ultimate protection against moisture, corrosion and tarnishing. But did you know that ALD can also protect against dark forces? The latest Star Wars movie is actually almost Finnish. Chewbacca is Finnish, the camera crew was partly Finnish and the alien dialect in the movie was created by a Finnish lady. 

 

Princess Leia (Carrie Fisher) wearing Planetoid Valleys necklace by Lapponia Jewelry. Photo © Lucasfilm Ltd
 

The best-known Finnish object in the Star Wars sequel, however, probably still is the Planetoid Valleys necklace Princess Leia wore in the original movie released in 1977.

Read the full story on the Beneq Blog:  http://www.beneq.com/blog/201601/may-the-coating-be-you.html

ALD History Blog: New type of statistics for ALD-history-evolving-fi...

ALD History Blog: New type of statistics for ALD-history-evolving-fi...: Good news: I have learnt how one can collect article reading statistics from the VPHA-reading-overview-file with Google spreadsheets functions. This makes it easy to visualise the status of commenting, whether individual papers have 0, 1, 2, 3, or 3+ comments. Below you find the current situation. With time, I plan to report on trends on how the reading evolves.

Strem Organometallic and inorganic compounds for CVD & ALD

I assume many of you have got your ALD & CVD research success partially thanks to companies like Strem supply us with ALD and CVD precursors. Here is an update as promoted by Strem: Researchers investigating chemical vapour deposition (CVD) would certainly call this field of study a mature research area. The field has grown significantly, with the addition of single atomic layer deposition ALD, from the early days of the mid to late 1980s where precursors had to be synthesized in-house to then decompose by gentle (more or less gentle) thermal treatment.

 

 

 

Rapid developments associated with CVD/ALD derived materials can surely be associated with the ever increasing number of volatile organometallic and inorganic – some may consider them as simple coordination complexes- that are commercially available.

Let’s simply say that the sheer number is impressive and has something for everyone and for whatever purpose the mind can think of. Applications ranging from high dielectric oxides or transparent conductive films within electronics to protective coatings for clothing. The materials include high purity silicon-containing reagents to volatile rare-earth precursors.

Strem has been involved in this field for quite some time and an extensive list of compounds are available for use in CVD/ ALD related chemistry, see its CVD/ALD section at http://www.strem.com/catalog/family/ALD/ listing hundreds of materials. These materials can be supplied on their own, within customers' containers or custom bubblers/cylinders designed to be compatible with commercial equipment. These easily connected units made of stainless steel, come pre-charged with your favorite material and represent a plug-and-play approach to the once tedious synthetic task of actually making and handling such volatile and often harmful materials.

CPI in The UK and Beneq Sign Collaboration Agreement to Commercialise Roll-to-Roll ALD Technology

As reported by AZO Nano: The Centre for Process Innovation (CPI) and Beneq have signed a long term collaboration agreement for the use of atomic layer deposition (ALD) technologies in printable electronics applications.




The agreement brings together Beneq’s expertise in the field of high precision vacuum coating alongside CPI’s specialist capability in the scale up of printed electronics. Working together, the two organisations will provide world leading capability for the commercialisation of ALD techniques, creating an open access environment for companies to develop ultra barrier solutions in areas such as photovoltaics, OLEDs, microelectronics and sensors.

The collaboration agreement follows on from CPI’s recent installation of two atomic layer deposition tools from Beneq for the development of conformal nano-scale coatings; one batch ALD tool and one state of the art roll-to-roll ALD ( R2R ALD) system. In particular the roll-to-roll ALD tool processing technology will be actively developed between the two companies.

The partnership between Beneq and CPI means that we will be able to constantly refine and optimise our capability and associated processes over the coming years to ensure that we remain a world leader in atomic layer deposition coatings.

Through this strategic alliance, the continuing developments will give us the flexibility to constantly meet and exceed the demands of our diverse customer requirements.

Alf Smith - Business Development Manager, CPI
 

Beneq and CPI share a vision of the enabling role of atomic layer deposition in flexible electronics. CPI’s personnel are skilled in using the Beneq ALD equipment so this partnership is a natural continuation to the work we have already carried out together.

Combining CPI’s extensive process capabilities with our know-how of ALD equipment and industrial ALD production allows us to achieve more. Pilot-scale operation and rapid prototyping with our equipment provides Beneq with invaluable information on system performance, and our customers benefit from an established R&D platform and – in the end – faster time to market with ALD applications.

Dr Mikko Söderlund - Head of Industrial Solutions, Beneq
ALD is applied as a specialist barrier coating technique used for the protection of optoelectronic devices and is being utilised by CPI to add moisture ultra-barrier protection layers to flexible polymer substrates used to produce optoelectronic devices using sensitive active electronic materials.

Thin films produced using the ALD method are cost efficient, defect free and completely conformal, thus providing superior barriers and surface passivation compared with other deposition techniques. These properties make them ideal for numerous kinds of critical applications that utilise flexible films such as Organic Light Emitting Diodes (OLED), flexible display screens, photovoltaic cells and wearable electronics to name but a few.

Current commercial barrier films, based on multilayer laminates are typically prohibitively expensive for large area applications while single thin layer barrier structures from ALD deposition have demonstrated the potential to reduce this cost significantly whilst retaining the requisite barrier and flexibility properties.

Further application areas of ALD and R2R ALD will be developed during the collaboration, where conformal nano-scale coatings are beneficial which would include transport, interfacial and contact layers in devices such as OLEDs, PV and sensors for example.

The Critical Materials Council to be managed by TECHCET in 2016

 The Critical Materials Council for Semiconductor Fabricators, originally established by ISMI/SEMATECH in the early 1990’s, will be managed by TECHCET CA LLC starting January 01, 2016. Under its new name CMC Fabs, the membership-based organization of semiconductor fab & fabless manufacturers will continue working to identify and remediate issues impacting the supply, availability, and accessibility of both current and emerging semiconductor process materials. In keeping with SEMATECH tradition, the work of the international council takes place in a non-competitive environment for the benefit of the semi device fabrication community. Topics addressed are identified and prioritized by the member companies.

The organization has a new website at cmcfabs.org, which includes an overview of the Council’s mission, news of upcoming events and a Members Only portal for access to minutes of monthly phone/WebEx meetings and workshop details. The site also features access for Members to the TECHCET Critical Materials Reports and the related quarterly updates.

The next face-to-face meeting of CMC Fabs will take place May 3-6, 2016 in Hillsboro, Oregon. The meeting will include the annual CMC Materials Seminar held on May 5-6 that is open to the public. Sessions include a market briefing, supply chain issues and methods, the evolution of emerging materials in ALD / ALE, and the materials revolution around carbon. Speakers will be drawn from fabs, suppliers and analysts to address topics of concern and interest to the Council, and the semiconductor materials supply chain.


CMC Fabs is a unit of TECHCET CA LLC, a firm focused on Process Materials Supply Chains, Electronic Materials Technology, Materials Market Research and Consulting for the Semiconductor, Display, Solar/PV, and LED Industries. The company has been responsible for producing the SEMATECH Critical Material Reports since 2000.

News Flash - Volvo XC90 first car with ALD High-k/Metal Gate FinFET technology

Recently we had Audi and Samsung announcing that ALD High-k DRAM volatile memory will be used in future joint electronics in Audi cars. At CES in Las Vegas Nvidia Corp. unveiled a new, lunchbox-size super-computer for self-driving cars and said Volvo Car Group will be the new device's first customer. Volvo plans to install the device in 100 cars to be launched in 2017 as part of a large-scale trial of autonomous driving technology in Göteborg, Sweden. [Reuters]

Googling around I found what Logic is used and it seems to be 16 nm TSMC FinFET technology and then we  should have round about 10 ALD process steps or maybe even more!

Nvidia Drive PX 2 (Bild:Nvidia/Screenshot: Golem.de). Since it says 16nm and not 14nm we can assume that the CPU is fabricated by TSMC in Taiwan.

Nvidia CEO Jen-Hsun Huang Keynote speaker at CES shows the Hardware module for Drive PX 2. (Bild: Nvidia)

This is how happy Zlatan Ibrahimovic was the first time he sat in his Volvo 2015 XC90 that he picked up in Paris Auto show from Volvo boss Håkan Samuelsson. Let´s hope Zlatan get the ALD upgrade as well.

Some ASM A412 Large Batch Furnaces form inside a TSMC 300mm Fab (Photo : Copyright® Taiwan Semiconductor Manufacturing Company Limited 2010-2016, All Rights Reserved. )

JVSTA ALD & ALE issue is here!

JVSTA ALD & ALE issue is here - Goldig as they say in German!

Review Articles

Atomic layer deposition on polymer fibers and fabrics for multifunctional and electronic textiles

Alexandra H. Brozena, Christopher J. Oldham and Gregory N. Parsons

J. Vac. Sci. Technol. A 34, 010801 (2016); http://dx.doi.org/10.1116/1.4938104

ALD & CVD Metal Manganese Precursors from Canada

The other day we had a paper by Barry Lab on how to make your own gold ALD precursor and now here another hot topic in ALD & CVD of Metal Manganese and for sure also this paper is from Canada as well! Manganese is being evaluated by Intel, Imec and others for sub 10 nm Cu barrier in BEOL metallization. Even if those barriers are just a couple of nano meters thin it is big business since the potential in BEOL is huge if the processes were to be used for a multiple wafer passes of the BEOL Cu metallization. Recently at 20/14 nm. It will be interesting to follow if Manganese will put up a fight against Cobalt or the slugger Ruthenium for future interconnect barriers and Cu caps.

Base-Free and Bisphosphine Ligand Dialkylmanganese(II) Complexes as Precursors for Manganese Metal Deposition

Jeffrey S. Price, Preeti Chadha, and David J. H. Emslie
Organometallics, Article ASAP, DOI: 10.1021/acs.organomet.5b00907
Publication Date (Web): December 30, 2015

 

 

Graphical abstract

 

The solid-state structures and the physical, solution magnetic, solid-state magnetic, and spectroscopic (NMR and UV/vis) properties of a range of oxygen- and nitrogen-free dialkylmanganese(II) complexes are reported, and the solution reactivity of these complexes toward H₂ and ZnEt₂ is described. The compounds investigated are [{Mn(μ-CH₂SiMe₃)₂}_∞] (1), [{Mn(CH₂CMe₃)(μ-CH₂CMe₃)₂}₂{Mn(μ-CH₂CMe₃)₂Mn}] (2), [Mn(CH₂SiMe₃)₂(dmpe)] (3; dmpe = 1,2-bis(dimethylphosphino)ethane), [{Mn(CH₂CMe₃)₂(μ-dmpe)}₂] (4), [{Mn(CH₂SiMe₃)(μ-CH₂SiMe₃)}₂(μ-dmpe)] (5), [{Mn(CH₂CMe₃)(μ-CH₂CMe₃)}₂(μ-dmpe)] (6), [{Mn(CH₂SiMe₃)(μ-CH₂SiMe₃)}₂(μ-dmpm)] (7; dmpm = bis(dimethylphosphino)methane), and [{Mn(CH₂CMe₃)(μ-CH₂CMe₃)}₂(μ-dmpm)] (8). Syntheses for 1–4 have previously been reported, but the solid-state structures and most properties of 2–4 had not been described. Compounds 5 and 6, with a 1:2 dmpe/Mn ratio, were prepared by reaction of 3 and 4 with base-free 1 and 2, respectively. Compounds 7 and 8 were accessed by reaction of 1 and 2 with 0.5 equiv or more of dmpm per manganese atom. An X-ray structure of 2 revealed a tetrametallic structure with two terminal and six bridging alkyl groups. In the solid state, bisphosphine-coordinated 3–8 adopted three distinct structural types: (a) monometallic [LMnR₂], (b) dimetallic [R₂Mn(μ-L)₂MnR₂], and (c) dimetallic [{RMn(μ-R)}₂(μ-L)] (L = dmpe, dmpm). Compound 3 exhibited particularly desirable properties for an ALD or CVD precursor, melting at 62–63 °C, subliming at 60 °C (5 mTorr), and showing negligible decomposition after 24 h at 120 °C. Comparison of variable-temperature solution and solid-state magnetic data provided insight into the solution structures of 2–8. Solution reactions of 1-8 with H₂ yielded manganese metal, demonstrating the thermodynamic feasibility of the key reaction steps required for manganese(II) dialkyl complexes to serve, in combination with H₂, as precursors for metal ALD or pulsed CVD. In contrast, the solution reactions of 1–8 with ZnEt₂ yielded a zinc–manganese alloy with an approximate 1:1 Zn/Mn ratio.

MV Vacuum Inlet Traps for ALD Processes

Many times I get questions on how to protect the pump for your ALD reactor - last time this afternoon actually. A fist step is to put a trap before the pump. Either a cold trap (e.g. H2 cooled or N2 cooled). A water cooled trap is standard for many processes using metal halides (e.g. TiCl4) and NH3 to condense ammonium chloride. For high-k stuff like TMA and metal alkyl amides  you can use a large surface area trap like this one from MV Products. However for large amounts of precursor in large batch ALD furnaces running 24/7 you have to talk to the experts when designing a reliable abatement system - Saftey first!

NORTH BILLERICA, MA--(Marketwired - Jan 5, 2016) - MV Products has introduced a line of vacuum pump inlet traps that are designed to protect vacuum pumps used in Atomic Layer Deposition (ALD) processes in research and production environments.

MV Vacuum Inlet Traps for ALD Processes are designed to prolong vacuum pump life and reduce service intervals by removing large solids and volatile precursors from the vacuum stream. Featuring stainless steel construction and multiple plumbing options, two models are offered: the MV Multi-Trap® for production use that is capable of up to 2,500 IN³ of solids accumulation and the PosiTrap® for smaller research and development applications.

Utilizing replaceable filter elements, MV Vacuum Inlet Traps for ALD Processes can be equipped with stainless steel gauze, micron-rated polypro-pylene, activated alumina or charcoal, Sodasorb^®, and other types to remove residual solvent vapor acids and particulates. The MV Multi-Trap^® includes a knock-down stage and can be configured with up to six stages of filters or a single large 13" H x 14" dia. pleated high-temp. polyester filter.

MV Vacuum Inlet Traps for ALD Processes are priced depending upon size and configuration. Price quotations are available upon request.

Call for abstracts - Novel High k Application Workshop 2016, NaMLab, Dresden

In collaboration with the EU COST networking project HERALD (working group 4), NaMLab invites to the ‘Novel High-k Application Workshop’ on March 14th and 15th, 2016. New challenges offered by the application of high-k dielectric materials in micro– and nanoelectronics will be discussed by more than 80 participants from industry, research institutes and universities. The workshop was initiated as a stimulating European platform for application-oriented scientists to exchange ideas and discuss latest experimental results on MIM-capacitors, process technologies, leakage & reliability as well as characterization of high-k dielectrics integrated in silicon based micro– and nanoelectronics. In addition, new results in the field of ALD dielectrics in solar cells, transparent conduction oxides (TCOs) and atomic layer etching (ALE) will be discussed.

 A long list of speakers already confirmed their participation at the workshop. A preliminary program can be found here: http://www.namlab.com/news/events-1/novel-high-k-application-workshop

To participate in the workshop, please apply by the end of January 2016 with a ½ page abstract (oral or poster) describing the work you would like to present. Mail your abstract to ALD@namlab.com

Since the HERALD project aims to promote participation from new EU member countries, additional travel grants (up to €300 per person) are available. If you would like to apply for a travel grant, please state this in your email.

Sponsors:

The Conference Registration for ALD2016 in Dublin is now Open!

Conference Registration - 16th International Conference on Atomic Layer Deposition (ALD 2016 Ireland) incorporating Atomic Layer Etching 2016 Workshop: http://ald2016.com/event-registration/

 

Early Registration: until 31 March 2016
Standard: 1 April to 17 June 2016
Late Registration: 18 June to 18 July 2016

CLICK To register!

 

 

Welcome to the 16th Atomic Layer Deposition Conference

The 16^th International Conference on Atomic Layer Deposition (ALD 2016) will be a three-day meeting dedicated to the science and technology of atomic layer controlled deposition of thin films.  In every year since 2001, the conference has been held alternately in United States, Europe and Asia, allowing fruitful exchange of ideas, know-how and practices between scientists. This year, the ALD conference will incorporate the Atomic Layer Etching 2016 Workshop, so that delegates at the two events can interact freely.  The conference will take place on 24-27 July 2016 at the Convention Centre Dublin, Ireland.

Atomic Layer Deposition (ALD) is used to fabricate ultrathin and conformal thin film structures for many semiconductor and thin film device applications. A unique attribute of ALD is that it uses sequential self-limiting surface chemistry to achieve control of film growth in the monolayer or sub-monolayer thickness regime. ALD is receiving attention for its applications in leading-edge electronic technologies, advanced microsystems, displays, energy capture and storage, solid state lighting, biotechnologies and medical technologies. Indeed ALD is particularly advantageous for any advanced technology that requires control of film structure in the nanometer or sub-nanometer scale.

As in past conferences, the meeting will be preceded by one day of tutorials. An industry trade show will be held in conjunction with the conference, to act as common ground for academia and industry to meet and discuss the future applications of ALD. Extra opportunities for collaboration will be provided through working groups of the COST Action ‘Hooking together European research in atomic layer deposition (HERALD)’.

This conference offers an excellent opportunity to learn about the most recent R&D activities in ALD science and technology from researchers around the world. We look forward to your participation.

ALD 2016 Co-Chairs:

Simon Elliott Tyndall National Institute, Ireland	Jonas Sundqvist Division of Solid State Physics, Lund University, Sweden

ALD History Blog: Baltic ALD 2015, Tartu: travel notes by Riikka Puurunen

ALD History Blog: Baltic ALD 2015, Tartu: travel notes by Riikka Puurunen - The 13th International Baltic Conference on Atomic Layer Deposition, Baltic ALD 2015 was organised in Tartu, Estonia, September 28-29, 2015. Conference chairs were Prof. Jaan Aarik and Dr. Kaupo Kukli. Conference website: http://www.bald2015.ee/. Right after the conference, on September 30, 2015, there was the yearly meeting day of the HERALD COST network on ALD (http://www.european-ald.net/). I have not visited Tartu before, and it was very interesting to attend this Baltic ALD conference in the historical city of Tartu, where the first report of ALD (then, ALE) is from year 1983. ... more »

Tokyo Electron release Triase+™ EX-II™ TiN Plus HT, a Single-Wafer Metallization System

Tokyo Electron Single Wafer SFD (Sequential Flow Deposition) has been dominating the market for e.g. TiN DRAM Capacitor electrodes for a long time. Recently (2013) it was updated to AFSD as in Advanced Sequential Flow Deposition. Tokyo Electron used to claim that they had this position because they had ClF3 chamber in-situ clean technology, but there are a number of other reasons. For those of you familiar with the TiCl4/NH3 ALD process know that there are two major issues:

1. Growth nucleation - for thermal oxide it can be as many as 100 deposition cycles before growth starts.
2. Low growth rate of 0.3 to 0.4 Å/cycle

SFD already addressed booth issues and with ASFD Tokyo Electron addressed lower thermal budget and improved conformality for high aspect ratio applications. Now it is very interesting to see what will happen when Tokyo Electron has released their new version of the ASFD process and the Trias Platform - The Triase+TM EX-IITM TiN* Plus HT single-wafer metallization system with HT as in High Temperauture. One reason to target high temprature is to achieve better performance (lover contact resistance) for Ti/TiN/W in for example:

1) Burried Word Lines in DRAM & coming RRAM

Since the introduction by Qimonda in 2008 (65nm DRAM) all companies uses burried tungsten word lines. 2014 Micron also presnted this technology for RRAM. Since this is a front end process there is absolutely no concern of process temperature.

Micron and Sony get together to build a 27-nm 16Gb Cu-ReRAM (IEDM 2014) 

2) High aspect ratio low resistivity electrodes and gates. 

Thinner electrode materials are needed due to geometrical constraints for scaled devices using high aspect ratio electrodes and metal gates like in DRAM and 2nd generation 3DNAND.

Samsung sub 20 nm DRAM technology presented at IEDM 2015 (Solid State Technology)

Samsung 1st generation 3DNAND investigated by Chipworks showing high aspect ratio metal gates and contacts.

Tokyo Electron Limited (TEL) announced today that it will begin accepting orders for the Triase+TM EX-IITM TiN* Plus HT single-wafer metallization system in April 2016.

Its base model, the Triase+ EX-II TiN, is a high-speed single-wafer ASFD* system with an optimized reactor chamber and unique gas injection mechanism. Since its introduction in January 2013, the Triase+ EX-II TiN has established itself as the standard for single-wafer ASFD TiN metallization systems, and has been adopted by memory and logic device manufacturers throughout the world. The Triase+ EX-II TiN Plus, an upgraded model that became available for booking in July 2015, has also been enthusiastically received in the market.

The continued scaling of semiconductor technologies has required that TiN processes in advanced device manufacturing become more detailed and diverse than ever before. TiN deposition systems must now overcome new technical challenges at highly sophisticated levels.

The EX-II TiN Plus HT, which will soon be available to order, has specialized hardware for high-temperature processes and is capable of depositing TiN film of a lower resistance and lower impurity-key technical requirements for advancing semiconductor scaling. Customers already using the Triase+ EX-II TiN or the EX-II TiN Plus can upgrade to the EX-II TiN Plus HT by modifying their existing systems, thereby reducing investment costs.

"The Triase+ EX-II TiN Plus HT is the latest generation system in the series," said Takeshi Okubo, Executive Officer and General Manager, SDBU at TEL. "It is equipped to perform high-temperature processes to satisfy new technical requirements resulting from the scaling of semiconductors, while maintaining the excellent within-wafer uniformity and step coverage achieved by the preceding EX-II TiN Plus. TEL will keep tackling difficult technology development issues to deliver high value-added products for broad-ranging thin film deposition applications."

* TiN: Titanium Nitride; ASFD: Advanced Sequential Flow Deposition, a low-temperature processing method for forming nanoscale metal films with highly-engineered properties.

NovaldMedical - an ALD Life Science Company from Finland

NovaldMedical - Here is a new interesting ALD applications company from Finland for Atomic Layer Deposition (ALD) application development to serve enhanced drug delivery, formulation engineering and industrial pharmaceutical manufacturing. [Thanks Riikka for tweeting this one!] Below is an overview of NovaldMedicals offering

Low temperature coatings

Cost-efficiency is one of the most frequent keywords in the health-care sector. In daily life, products such as instruments for diagnostics sample collection and analysis as well as for therapies,... read more →

Atomic Layer Deposition (ALD)

ALD is an industrial, surface controlled, self-limiting layer-by-layer technique for depositing thin films from gaseous phase of the precursors. The two most important advantages of ALD are excellent conformality and... read more → 

Pharmaceutical Development

The costs and risk of failure in drug discovery and development are increasing and development is becoming more challenging. Drug discovery creates new candidates for drug development. Drug development is... read more →

Medical Devices

The medical device category of products enables an extremely large variety of technical and biological needs to be fulfilled depending on the component or system involved. Proven biocompatibility and biofunctionality... read more →  

 

 

ALD History Blog: VPHA & New Year 2016

ALD History Blog: VPHA & New Year 2016:

At the turn of the new year, it is always good to look back on the past year. Significant progress in VPHA occurred in VPHA in 2015 regarding many aspects:

- Better organization to allow the VPHA to proceed "by itself". VPHA-reading-overview-file, VPHA-reading-workflow and info@ vph-ald.com address enable the VPHA participants to find reading that is useful for the progress of the whole VPHA.
- VPHA organizational presentations were delivered at ALD Russia and Baltic ALD. The goal was to invite more people to get interested in VPHA and join it, which succeeded.... more »

How to make your own Gold ALD Precursor in the lab!

Yay! Now it is here the end of an interesting story 2015 from Barry Lab in Canada on making Gold ALD - all the details on how to make a gold ALD precursor! You can download the supporting information for free to the fresh article in Chemistry of Materials

Shoping List:

• HAuCl4 x H2O (49.9 weight % Au) Strem Chemicals
• 5 gTrimethylphosphine from Strem Chemicals diluted to 1.31 M solution in toluene
• 4 x 25 mL bottles MeLi (1.6 M in diethyl ether) from Sigma-Aldrich
• Anhydrous dichloromethane from Sigma-Aldrich
• tetrahydrothiophene from Sigma-Aldrich
• methyl iodide from Sigma-Aldrich
• Diethyl ether purified using an Mbraun Solvent Purification System.

If you done your synthesis correct you should get a thickness curve like this (with a typical Canadian hockey stick incubation function) (figure from supporting information, Chem. Mater. DOI: 10.1021/acs.chemmater.5b04562)

Read the instructions below carefully & Happy New Year

P.S. by the way you may need one of these too - a Picosun PEALD reactor from Finland  a Picosun Picoplasma Lapin Kulta Edition.