Friday, April 27, 2018

Intel shifts high volume 10 nm shipments to 2019 due to yield issues from multi-patterning

As reported by Reuters [LINK], Intel bet the earnings expectations for the first quarter driven by the biggest-ever quarterly jump in its data centre business and small-but-steady growth in its personal computer business.However, Intel also announced that they are pushing out volume production of their 10 nm Logic process to 2019, which was most recently announced for the 2nd half of 2018. during the 1Q 2018 earnings conference calls more details were given:

[Seeking Alpha, LINK] "We continue to make progress on our 10-nanometer process. We are shipping in low volume and yields are improving, but the rate of improvement is slower than we anticipated. As a result, volume production is moving from the second half of 2018 into 2019. We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify. We have leadership products on the roadmap that continue to take advantage of 14-nanometer, with Whiskey Lake for clients and Cascade Lake for the data center coming later this year.

Moore's Law is essential to our strategy and our product leadership. It continues to create significant value for Intel and our customers. While it's taking longer and costing more to deliver and yield advanced process technologies, we are able to optimize our process and products within the node to deliver meaningful performance improvements.

For example, 14-nanometer process optimizations and architectural improvements have resulted in performance gains of more than 70% since the first 14-nanometer products were launched. We combine these advances in manufacturing technology and architecture to produce truly leadership products. And it's that product leadership that ultimately matters most to our customers and end users."

Brian M. Krzanich - Intel Corp.

Earnings call slides [Seeking Alpha, LINK]

In the Q&A Mr. Krzanich elaborated on the reason behind the 10 nm push out and he explained how it is mainly due to yield issues coming from multiple patterning (SADP and SAQP):

- Intel have 10 nm product and process leadership and are shipping 10 nm products today. 
- Those are the densest, highest performing products out there.
- Intel is slowing the ramp down to fix yield issues related to patterning.
- In multi-multi-patterning (SAQP) there are six layers of patterning to produce a feature. 
- Intel understand the yield issues, which are tied to 10 nm being the last technology tied to not using EUV and the amount of multi-patterning and the effects of that on defects.

Intel’s 10 nm Platform Process was presented in detail at the IEDM 2017 (Dec 2017) “A 10nm High Performance and Low-Power CMOS Technology Featuring 3rd Generation FinFET Transistors, Self-Aligned Quad Patterning, Contact over Active Gate and Cobalt Local Interconnects” and you may study the details in this excellent article by Dick James [Solid State Technology, LINK]

Media coverage:
The Register

Thursday, April 26, 2018

JVSTA Call for papers ALD & ALE

Call for Research Articles
Atomic Layer Deposition and Atomic Layer Etching
Manuscript Deadline: November 1, 2018


This special topic collection is planned in collaboration with ALD 2018 and the ALE 2018 Workshop to be held in Incheon, South Korea during July 29—August 1, 2018. The Special Topic Collection will feature sections dedicated to the science and technology of atomic layer controlled deposition and to the science and technology of controlled etching of thin films. While a significant number of articles will be based on material presented at ALD 2018 and the ALE 2018 Workshop, research articles on ALD and ALE but not presented at this conference are also welcome. The special topic collection will be open to all articles on the science and technology of ALD and ALE.

Authors are encouraged to use the JVST templates. Online, you will have an opportunity to tell us that your paper is a part of the Special Topic Collection by choosing either the “ALD Special Topic Collection” or the “ALE Special Topic Collection.

Tuesday, April 24, 2018

RASIRC to Present Anhydrous Hydrogen Peroxide Surface Preparation and Enhanced Nucleation for ASD at ASD2018

Area selective deposition is becoming increasingly important for the immense scaling effort continuously taking place in the semiconductor industry for Logic and Memory Devices. Today double and multiple pattering schemes using Plasma Enhanced ALD are in High Volume Manufacturing (HVM) for all sub 28 nm nodes and any moment now the industry expect to ramp EUV lithography, possibly at the 7 nm Foundry Node. Beyond that in a joint effort the researchers and the industry are looking for alternative patterning methods and many of them are based on so called bottom-up patterning.

To put things in perspective for ASD, one of the first area selective ALD processes in HVM was introduced in 300 mm DRAM manufacturing by Infineon Technologies in 2004 (90 nm Deep Trench DRAM presented in detail at IEDM 2004). This area selective ALD process relied on controlling the amount of hydroxyl groups in the upper part of a trench structure using the well-known TMA / H2O based process growing Al2O3. The goal was to let the process partially penetrate about 1 micron deep into very deep DRAM trenches to protect the silicon surface from a following isotropic etch that would widen the deep trench creating more surface and therefore allow a higher capacitance of the memory cell which is a key performance parameter in DRAM at about 25 fF/cell at that time.

In addition, the liner protected the collar region from dopant penetration keeping a well-defined dopant profile isolated from the wafer surface where the select transistor would later operate and it also defined a selective area for growth of Hemi-Spherical Grains (HSGs) another surface area expansion technology used in the DRAM industry. Please check the patent visualized below for many more details. This fascinating process was Self-Aligned and Area Selective in so many ways and kicked out a number of complex alternative integration paths saving a lot of $/wafer. By optimizing all process parameters it was possible to control the penetration depth of the liner, the transition region length down to the non-growth area, wafer uniformity and liner quality (density). This process was used until the end of the Deep Trench era which at this time had ~25% of the DRAM market but was killed at 65 nm when all companies had transitioned to stacked memory cells.

The Non-conformal ALD Al2O3 liner application as described in the US patent “Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition” (Figure from US7344953B2) 

Since then several things have happened. For one thing ALD has become a standard processing technology in Logic and Memory HVM forming its own Business Segment with an annual Equipment revenue >USD 1.5 Billion. Secondly, Atomic Layer Etching (ALE) has also entered HVM at the Logic 14 nm FinFET manufacturing. In parallel several efforts have begun to explore novel methods for ASD. These utilize Self-Assembled Monolayers, Patterned Photoresists, Selective CVD processes (e.g. Cobalt CVD), Plasma deposited films and other creative surface blocking agents and employing ALD and ALE in combination to trigger or block surface growth.  In parallel, reactive surfaces must be created for high nucleation and growth of metal oxide films.  An ideal surface treatment for the latter will:

                  Create high density surface functionalization
                  Have zero or minimal sub-surface oxidation
                  Lead to faster and more uniform nucleation versus H2O
                  Remain non-reactive with organic functionality or photoresist on adjacent surfaces

The use of the novel reactive chemistry, anhydrous hydrogen peroxide, has been largely ignored. This is due to: a lack of literature precedent; that H2O2 is typically delivered with H2O (multiple publications from K. Kukli et al at University of Helsinki and Tartu) where water dominates the reaction chemistry; and that only recently did this material become available by RASIRC (San Diego, USA) in an ampoule form that could be integrated into ASD process equipment.

Besides water, Ozone is an important co-reactant and oxidative precursor in ALD of metal oxides for, e.g., High-k dielectrics in DRAM Capacitors. Hydrogen Peroxide has similar oxidation properties to Ozone (oxidation potential O3 = 2.1V versus 1.8V for H2O2) while simultaneously having slightly stronger proton transfer properties than water (water pKa = 7.0 versus 6.5 for H2O2). According to Jeff Spiegelman (CEO and Founder of RASIRC) the key learning from early discoveries is the fact that H2O2 has a very weak O-O bond, where Bond Energy = 36 kcal/mole and you can imagine that it is thus much more readily available to conduct reactive surface chemistry in an ALD process than the oxygen atom in the water molecule.

RASIRC and their collaborative network of leading scientists and customers around the world have in recent years conducted exciting work with anhydrous hydrogen peroxide that demonstrates the following with regard to the required attributes for ASD:

                  Dry H2O2 creates 3-5 times higher nucleation surface density of hydroxyl groups
(-OH) versus water on metal surfaces
                  Monolayer hydroxyl (-OH) surface functionalization can be obtained by dry H2O2 on Si surfaces without sub-surface oxidation
                  Faster nucleation and growth of Al2O3  is observed utilizing dry H2O2 on Si-H surfaces versus H2O
Little to no Photoresist removal occurs from reaction with hydrogen peroxide at temperatures up to 300°C.

BRUTE Peroxide Ideal Chemistry for Area Selective Deposition yielding: High density surface hydroxylation, minimal sub-surface oxidation, faster and more uniform nucleation versus H2O, non-reactive with protecting groups on adjacent surfaces and Peroxide will grow a High Quality Metal Oxide

In addition, RASIRC has demonstrated that metal oxide films such as the most important ones; Aluminum oxide, Hafnium oxide, and Zirconium oxide have high quality film properties nearly identical to those grown by ozone methods.

In 3D-structures with extreme high aspect ratio (DRAM, 3DNAND) ozone will penetrate deep down the structure before reacting with the surface groups since the sticking coefficient is much smaller than H2O or preferably H2O2. This means that area selectivity employing ozone is difficult to achieve. You can imagine that Dry H2O2 would have been very beneficial back in 2004 for the non-conformal liner case described above by allowing use of a much thinner liner with higher density and therefore higher thru-put. Potentially also Dry H2O2 would allow for a sharper transition region – to be discovered!

RASIRC Chief Technology Officer Dan Alvarez will present additional details on the newly discovered reactivity of anhydrous hydrogen peroxide on several surfaces as well as outline some potential ASD pathways at AVS ASD2018, North Carolina State University, April 29 to May 1, 2018. (

This is the 3rd time the ASD Workshop will be held. It is a fully supported AVS event and there has been a growing interest in ASD. In the future we can expect that it will form a solid business segment as ALD and ALE and bring in new players, both academic and industrial, in the exciting field of Atomic Level Processing!