Thursday, January 2, 2020

Picosun’s ALD technology enables 3D silicon-integrated microcapacitors with unprecedented performance

ESPOO, Finland, 2nd January 2020 (LINK) – Picosun Group, global provider of leading AGILE ALD® (Atomic Layer Deposition) thin film coating solutions, reports record performance of silicon-integrated, three-dimensional deep trench microcapacitors manufactured using its ALD technology.

Increasing efficiency and performance demands of portable and wearable electronics, along with their shrinking size in accordance with the Moore’s law, set new challenges to the power management of these devices as well. A solution is further integration of the devices’ key components into so-called SiP (systems-in-package) or SoC (systems-on-chip) architectures, where everything, including the energy storage such as batteries or capacitors, is packed close to each other into one compact, microscale-miniaturized assembly. This calls for novel techniques to increase the performance and shrink the size of the energy storage unit as well. Three-dimensional, high aspect ratio and large surface area deep trench microcapacitors where ultra-thin, alternating layers of conducting and insulating materials form the energy storing structure, provide a potential solution.

Figures above: Main technological steps of 3D microcapacitor fabrication. 1: patterning of a square lattice of holes on the silicon surface; 2: high aspect ratio trenching of silicon by electrochemical micromachining (ECM); 3: atomic layer deposition (ALD) of conformal metal-insulator-metal (MIM) stack; 4: aluminium deposition and contact patterning (*).

Picosun’s ALD technology has now realized unprecedented performance of these 3D microcapacitors. PICOSUN® ALD equipment were used to deposit film stacks of conductive TiN and insulating dielectric Al2O3 and HfAlO3 layers into high aspect ratio (up to 100) trenches etched into silicon. Up to 1 µF/mm2 areal capacitance was obtained, which is the new record for this capacitor type. Also power and energy densities, 566 W/cm2 and 1.7 µWh/cm2, were excellent and surpassing the values achieved with the most of the other capacitor technologies. The ALD microcapacitors showed also outstanding voltage and temperature stability, up to 16 V and 100 oC, over 100 hours continuous operation (*).

Figures above: b) SEM cross-section of an array of cylindrical trenches with a pitch of 4 μm, diameter of 2 μm and aspect ratio of 100, conformally coated with an ALD stack consisting of 40 nm of TiN, 40 nm of Al2O3, and 40 nm of TiN. Insets show a detail of the MIM stack at the top and bottom of a single trench; d) high-resolution TEM image of an MIM stack consisting of 40 nm of TiN, 40 nm of Al2O3, and 40 nm of TiN taken at the bottom of ALD-coated trenches with aspect ratio of 100; e) TEM-EDX elemental maps of Ti (yellow), N 14 (cyan), Al (red), and O (green) of the MIM stack in (d) (*).

These excellent performance indicators pave the way to industrial applications of this capacitor technology. This is further facilitated by ALD’s mature position in modern semiconductor industries, where the technology is already integrated into practically all advanced microchip component manufacturing lines.

“We exploited the room available on the bottom of silicon wafers, of which only a few micrometers of silicon are used for electronic components in integrated circuits, to fabricate silicon-integrated 3D microcapacitors with unprecedented areal capacitance. The electrochemical micromachining technology, developed at the University of Pisa over the past decade, enabled etching of high density trenches with aspect ratios up to 100 in silicon, a value otherwise not achievable with deep reactive ion etching. This posed the basis for increasing the areal capacitance of our 3D microcapacitors upon conformal coating with an ALD metal-insulator-metal stack,” says Prof. Giuseppe Barillaro, group leader at the Information Engineering Department of the University of Pisa, Italy.

“The suberb results achieved with our 3D silicon-integrated microcapacitors show again how imperative ALD technology is to modern microelectronics. We are happy that we can offer our unmatched expertise and decades of cumulative know-how in the field to develop novel solutions for the challenges the industry is facing, when the requirements for system performance and integration level increase inversely to the system size. The environmental aspect is also obvious, when smaller, more compact devices manufactured in the same line mean also smaller consumption of materials and energy,” says Juhana Kostamo, deputy CEO of Picosun Group.
(*) “Three-dimensional silicon-integrated capacitor with unprecedented areal capacitance for on-chip energy storage”, Lucanos M. Strambinib,1, Alessandro Paghia,1, Stefano Mariania, Anjali Soodc, Jesse Kalliomäkic, Päivi Järvinenc, Fabrizio Toiad, Mario Scuratid, Marco Morellid, Alessio Lampertie, Giuseppe Barillaroa,b,, accepted for publication in Nano Energy,
a Dipartimento di Ingegneria dell’Informazione, Università di Pisa, via G. Caruso 16, 57122, Pisa, Italy
b Istituto di Elettronica e di Ingegneria dell’Informazione e delle Telecomunicazioni, Consiglio nazionale delle Ricerche, via G. Caruso 16, 57122, Pisa, Italy
c Picosun Oy, Tietotie 3, Espoo, FI-02150, Finland
d ST Microelectronics, via Olivetti 1, Agrate Brianza, Italy
e IMM-CNR, Unit of Agrate Brianza, Via C. Olivetti 2, 20864, Agrate Brianza, MB, Italy
(Funding from the ECSEL Joint Undertaking through the R2POWER300 project, grant no. 653933)


  1. Very nice work to get 1 μF/mm2 areal capacitance density! Also good propaganda for ALD in trenched silicon.
    Industrially spoken, the throughput (i.e. Cost-of-Ownership) will be a challenge with conventional ALD. Spatial ALD could bring this a few steps forward. 
    Back in ~2006 at Philips-NXP, we deposited the same TiN/Al2O3/TiN layer stacks using the (spatial (!) ALD “Cyclone” reactor of Jusung, Korea. We published this work in 2008, with world-record areal density of 0.44 μF/mm2 for similar ALD-grown MIM capacitor stacks in 3-D silicon trench arrays in IEEE Electron Device Letters 29, 740 (2008).
    In 2008 we predicted 1-4 μF/mm2 at the First Int. Workshop on Power Supply on Chip (PowerSoC08), Sept. 22-24, 2008, in Cork, Ireland; see slide 46 on,4%20uF%20mm-2)%20trench%20capacitors%20in%20Silicon.pdf
    This prediction was based on the high-k materials that we (Philips, NXP, TU Eindhoven, Tyndall, Fraunhofer, …) studied in the European FP6-projects ‘REALISE’ and ‘e-CUBES’ (2006-09), and MEDEA+ ‘MAXCAPS’ (2008-2011).
    Part of the work at Philips has been transferred to and commercialized by what is now MuRata Passive Solutions in Caen, France, where they use the more “open” 3D pillar arrays etched in silicon rather than trenches:

    In the same period (2006-2009) at Fraunhofer Gesellschaft in Dresden, dr. Jonas Sundqvist and co-workers used a total 6 “Cyclone+” chambers running ZrO2, HfO2, SrTiOx, Ru and TiN in R&D and production for their 65 and 45 nm DRAMs. Their capacitors were different but solved the same type of issues with Cost-of- Ownership, again with spatial ALD.

    At TNO in 2017 we published on the good film conformality inside porous substrates using (spatial) ALD, in J. Vac. Sc. Technol. A, 35 021502-1 (2017).
    In this perspective the claim of doubling areal capacitance in 12 years seems a logical, evolutionary step, so one can just expect more to come !

    Fred Roozeboom
    Eindhoven University of Technology
    Dept. of Applied Physics
    Group Plasma & Materials Processing
    PO Box 513, 5600 MB Eindhoven, The Netherlands
    also at:
    TNO – Holst Centre
    High Tech Campus 21
    5656 AE Eindhoven, The Netherlands

  2. Thank you so much Frede for sharing the detailed information. It is always down to the complete CoO including the other processes and especially Litho/Etch I think I will sumarize this all into a new future blog post together with some additional stuff that I have camoe across working with high-k capacitors.

    Take care!

  3. Thanks, Jonas ! Food for expansion of this part of this blog post:
    The obvious applications of high-density capacitors in 3D trench or pillar arrays etched in silicon are in high-volume manufacturing of DRAM capacitors like Fraunhofer, Qimonda and many others did or do, and high-density RF decoupling capacitors (3D “decaps”) in wireless devices. Example: 3D “decaps” are now standard in the Apple iPhone10 (through TSMC), etc.

    New markets are of course in high-power applications and in medical implants. The latter market has undergone tremendous miniaturization enabled by 3D MIM-capacitors: For a roadmap here, see for example the one from MuRata, (former Philips, NXP, IPDiA), Caen (France), that I mentioned in my comment above: . They now manufacture 250 nF/mm2, and we haven’t seen the last at all.
    See also Yole’s review from 2017:

    For quite some time, high-density 3D MIM capacitors are used in pacemakers, but ultrahigh-density capacitors open up improved implantation: Medtronic’s pacemaker Micra is now the world’s smallest pacemaker, implanted no longer by chest incision but through a vein in the leg; see
    There’s cool video about it too:

    The capacitors in several of these examples contain no ALD-grown high-k dielectrics yet, so there is much more to appear, thanks to ALD.. 

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