Intel Sets Record with 2D TMD Transistors for Next-Gen Electronics

Intel researchers have achieved record-breaking performance in transistors using ultra-thin 2D transition metal dichalcogenides (TMDs) like MoS₂ and WSe₂ as channels. These monolayer materials are ideal for scaled devices but present challenges in integration due to their lack of atomic “dangling bonds.” By developing a specialized gate oxide atomic layer deposition (ALD) process and low-temperature gate cleaning, Intel built GAA NMOS and PMOS transistors with record subthreshold slopes and high drain currents. Specifically, they achieved a subthreshold slope of <75 mV/dec and Idmax >900 µA/µm in MoS₂ NMOS transistors, and a slope of 156 mV/dec with Idmax = 132 µA/µm in WSe₂ PMOS devices. These advancements highlight the promise of 2D TMDs for next-gen electronics and the need for further research to overcome integration challenges.

The images above are TEM characterizations of the record GAA NMOS device across the gate, showing a healthy, conformal GAA architecture with 43nm-wide monolayer MoS2 channel and conformal HfO2 with a thickness of ~4.0nm.

Record Performance with 2D Channels: Ultra-thin transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are called monolayer, or 2D, materials because they’re one just atomic layer thick. They are being extensively studied for use as the channel in extremely scaled devices because of their excellent electrical performance. However, interfacing them with other materials in a device structure is difficult because at the atomic level there are no available “dangling bonds” to use. Thus, 2D channels have been a challenge to optimize.

Intel researchers will describe how they used 1) a unique gate oxide atomic layer deposition (ALD) process and 2) a low-temperature gate cleaning process to build GAA devices that demonstrated breakthrough performance for MoS2- and WSe2-based GAA NMOS and PMOS transistors, respectively. This includes record subthreshold slope (<75mv/dec) and drain current (Idmax>900 µA/µm at <50nm gate length) in sub-1nm-thick monolayer MoS2 GAA NMOS transistors. Also, using ruthenium (Ru) source and drain (S/D) contacts, they achieved record subthreshold slope (156mV/dec) and drain current (Idmax = 132µA/µm) in a ~30nm gate-length WSe2 PMOS device. The researchers say these results both underscore the potential of 2D TMDs for use in next-generation electronics, and highlight the critical need for continued research to address the remaining scientific and technological challenges.

Sources:

https://www.ieee-iedm.org/press-kit

(Paper #24.3, “Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900µA/µm at Lg<50nm,” W. Mortelmans et al, Intel)