Intel Sets Record with 2D TMD Transistors for Next-Gen Electronics

Intel researchers have achieved record-breaking performance in transistors using ultra-thin 2D transition metal dichalcogenides (TMDs) like MoS₂ and WSe₂ as channels. These monolayer materials are ideal for scaled devices but present challenges in integration due to their lack of atomic “dangling bonds.” By developing a specialized gate oxide atomic layer deposition (ALD) process and low-temperature gate cleaning, Intel built GAA NMOS and PMOS transistors with record subthreshold slopes and high drain currents. Specifically, they achieved a subthreshold slope of <75 mV/dec and Idmax >900 µA/µm in MoS₂ NMOS transistors, and a slope of 156 mV/dec with Idmax = 132 µA/µm in WSe₂ PMOS devices. These advancements highlight the promise of 2D TMDs for next-gen electronics and the need for further research to overcome integration challenges.

The images above are TEM characterizations of the record GAA NMOS device across the gate, showing a healthy, conformal GAA architecture with 43nm-wide monolayer MoS2 channel and conformal HfO2 with a thickness of ~4.0nm.

Record Performance with 2D Channels: Ultra-thin transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are called monolayer, or 2D, materials because they’re one just atomic layer thick. They are being extensively studied for use as the channel in extremely scaled devices because of their excellent electrical performance. However, interfacing them with other materials in a device structure is difficult because at the atomic level there are no available “dangling bonds” to use. Thus, 2D channels have been a challenge to optimize.

Intel researchers will describe how they used 1) a unique gate oxide atomic layer deposition (ALD) process and 2) a low-temperature gate cleaning process to build GAA devices that demonstrated breakthrough performance for MoS2- and WSe2-based GAA NMOS and PMOS transistors, respectively. This includes record subthreshold slope (<75mv/dec) and drain current (Idmax>900 µA/µm at <50nm gate length) in sub-1nm-thick monolayer MoS2 GAA NMOS transistors. Also, using ruthenium (Ru) source and drain (S/D) contacts, they achieved record subthreshold slope (156mV/dec) and drain current (Idmax = 132µA/µm) in a ~30nm gate-length WSe2 PMOS device. The researchers say these results both underscore the potential of 2D TMDs for use in next-generation electronics, and highlight the critical need for continued research to address the remaining scientific and technological challenges.

Sources:

https://www.ieee-iedm.org/press-kit

(Paper #24.3, “Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900µA/µm at Lg<50nm,” W. Mortelmans et al, Intel)

Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More

Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More

Fred Roozeboom University of Twente, Jonas Sundqvist AlixLabs, Dmitry B. Suyatin AlixLabs, Kuniyuki Kakushima Institute of Science Tokyo (Tokyo Institute of Technology)

ECS-PRiME 2024 in Honolulu

The history of Atomic Layer Deposition (ALD) has been extensively researched in the VPHA-project (www.vph-ald.com/) initiated in 2013 by R. Puurunen [1]. It is commonly accepted that Atomic Layer Deposition (ALD) was conceived in the Baltic area as a unique ultrathin-film growth method based on the repeated, self-terminating gas-solid half-reactions of at least two volatile compounds on a solid substrate surface. Originally, in the 1960’s, the Russians Alekskovski and Kol'tsov [2]) named this method Molecular Layering and exactly 50 years ago, in 1974 the Finnish inventors Suntola and Antson [3] patented the method as Atomic Layer Epitaxy. This fact has been officially celebrated at the 24th ALD Conference in Helsinki (Aug. 5, ’24 ald2024.avs.org).

Atomic Layer Etching (ALE) has lagged behind ALD. For long [4,5] the first patent published on ALE was thought to have been initiated by Max Yoder [6]. In 1987 he conceived the idea on diamond etching with intermittent pulsing of nitrogen dioxide and noble gas ions mixed with hydrogen gas. However, it was Seiichi Iwamatsu (Fig. 1) of Seiko Epson, Japan, who filed in 1981 an application on Si-etching by repeated exposure to iodine (I2) chemistry at moderate temperatures (20 °C to 100 °C) followed by a light or heat pulse up to ~ 300 °C [7]; see Fig. 2. This patent was followed by several others on ALE [8]. One of these patents disclosed quasi-ALE (named “digital etching”) via Si-surface modification by “lamination” of a single Cl-atomic layer from exposure to Cl2 gas, followed by a removal step carried out by Ar+-ion bombardment to etch off “one atomic layer or at most three atomic layers by controlling the kinetic energy” [9].

This presentation will highlight the groundbreaking work and background of the Japanese inventor Seiichi Iwamatsu. Born in 1939 in Kyoto to a family of doctors - his father being a practicing physician- he grew up and studied in Osaka, after which he spent many years as a ‘master inventor’ (over 1200 patents filed in his name) for Seiko Epson (~1970-1990) and others afterwards. He played key roles in thin-film technology and e-beam lithography. He also contributed to the success story of Seiko’s quartz watch, a masterpiece in micromachining a miniature tuning fork from crystalline fused silica, tuning/trimming it to 32,768 Hz (=215 Hz), packaging it in a hermetically sealed case and integrating it with flip-flop frequency dividing and counting electronic circuitry and a step motor [10].

From the above it is clear that Mr. Iwamatsu can be recognized as the original inventor of Atomic Layer Etching.

Source: Late G-5068 - Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More https://ecs.confex.com/ecs/prime2024/meetingapp.cgi/Paper/199461

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Acknowledgement

The authors would like to thank Dr. Masanobu Honda (Tokyo Electron Miyagi Ltd., Japan) for his support in retrieving some of the historic facts mentioned herewith about Dr. Iwamatsu.

References

[1] R.L. Puurunen, Chem. Vap. Deposition 20, pp. 332–344 (2014); doi:10.1002/cvde.201402012.

[2] V.B. Alekskovski and S. I. Kol'tsov, Some characteristics of molecular layering reactions, Abstract of Scientific and Technical Conference, Goskhimizdat, Leningrad, 1965, p. 67 (in Russian).

[3] T. Suntola and J. Antson, FIN 52359, priority Nov. 29, 1974, US Patent 4,058,430, Nov. 15, 1977.

[4] K.J. Kanarik, et al., J. Vac. Sci. Technol. A 33, 020802 (2015); doi/10.1116/1.4913379.

[5] W.M.M. Kessels, www.atomiclimits.com/ March 2, 2020.

[6] M.N. Yoder, Atomic Layer Etching, US Patent 4,756,794, July 12, 1988; assigned to US Navy.

[7] S. Iwamatsu, Atomic Layer Etching Method, JPS5898929A / JPH0379862B2; priority Dec. 9, 1981, published June 13, 1983; assigned to Seiko Epson Corp.

[8] https://worldwide.espacenet.com/patent/search/family/016189802/publication/JPH0472726A?q=iwamatsu%20seiichi%20atomic%20layer%20etching

[9] S. Iwamatsu, Digital Etching Process, JPH0472726A, priority: July 13, 1990, published March 6, 1992; assigned to Seiko Epson Corp.

[10] https://corporate.epson/en/technology/search-by-products/wearable/quartz-watch.html

Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn

In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.

In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.

Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.

NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025

While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.

Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.

Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.

Advanced Logic and Foundry Nodes: Key Growth Segments for Lam

Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.

Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.

Advanced Packaging Driven by AI Fuels Revenue Growth

The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.

Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.

Supporting Installed Base and Productivity in Memory Markets

Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.

As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.

Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance

Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.

Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025

In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.

Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.

Strategic Positioning in 2025 and Beyond

In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.

3D Ferroelectric NAND for Ultra-High Efficiency Analog Computing-in-Memory by SK hynix

3D FeNAND with Ultra-High Computing-in-Memory Efficiency: AI models containing up to trillions of parameters require substantial memory resources to handle the vast amounts of data. Energy-efficient analog computing-in-memory (CIM) devices such as 3D vertical NAND architectures are emerging as potential solutions because they offer high areal density and are non-volatile. SK hynix researchers will detail how they achieved analog computation in ultra-high-density 3D vertical ferroelectric NAND (FeNAND) devices for the first time. They used gate stack engineering techniques to improve the analog switching properties of 3D FeNAND cells, and achieved an unprecedented ≥256-conductance-weight levels/cell. The 3D FeNAND arrays improved analog CIM density by 4,000x versus 2D arrays, and demonstrated stable multiply-accumulate (MAC) operations with high accuracy (87.8%) and 1,000x higher computing efficiency (TOPS/mm²) versus 2D arrays. This work provides an efficient method to implement the processing of hyperscale AI models in analog CIM chips for edge computing applications, where speed and low power operation are the critical requirements, not extreme accuracy.

 

Above:

(1)   is a comparison of 2D and 3D arrays for analog-CIM applications.

(2)   is a TEM analysis  of the 3D FeNAND, showing (a) a top-down view of the device; (b) a cross-sectional view at low magnification; (c) a cross-sectional view at high magnification; and (d) a schematic illustration of the FeFET cells in the 3D FeNAND array.

Source: 

IEDM 2024 Paper #38.1, “Analog Computation in Ultra-High Density 3D FeNAND for TB-Level Hyperscale AI Models,” J.-G. Lee and W.-T. Koo et all, SK hynix https://www.ieee-iedm.org/press-kit

4F² DRAM developed by a Kioxia using ALD IGZO

The new 4F² DRAM developed by a Kioxia-led team combines gate-all-around (GAA) IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) with a unique design that places transistors above high-aspect-ratio capacitors to reduce thermal stress and suppress electrical interference like "row hammer." This structure increases memory density and efficiency, providing a high on/off current ratio essential for low-power operation. The team demonstrated a 275Mbit array with this technology, indicating its potential to enable high-density, low-power DRAM for advanced computing applications.

Kioxia is traditionally known for its expertise in NAND flash memory rather than DRAM. They are one of the leading companies in the NAND space, focusing primarily on storage solutions. However, this new venture into DRAM with innovative 4F² cell structures signals an expansion of their research and development scope, possibly to leverage their materials and process expertise in a closely related area. It suggests Kioxia may be exploring ways to diversify its technology portfolio, potentially addressing high-density memory needs beyond traditional NAND storage

ALD offers atomic-level precision and is beneficial for creating uniform, conformal layers of IGZO in complex, high-aspect-ratio surfaces demonstrated here, which is particularly advantageous in advanced semiconductor applications. ALD works by exposing the substrate to alternating pulses of indium, gallium, and zinc precursors, separated by purges to prevent unwanted reactions. This controlled process achieves a smooth and consistent IGZO layer with excellent thickness control, crucial for sensitive electronic applications like DRAM devices.

New Type of 4F² DRAM: DRAM is the workhorse memory of electronic systems, but patterning the extremely small features of conventional silicon 6F² DRAM memory cells and suppressing “row hammer” electrical interference from nearby cells are major challenges. To overcome them, the industry has been actively developing denser 4F² DRAM designs made with different materials. A Kioxia-led team will describe a new type of 4F² DRAM, comprising GAA IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) and a new integration scheme, where the heat-sensitive transistors are placed on the top of high aspect-ratio capacitors instead of on the bottom, to reduce the thermal impact from BEOL processing below. The vertical architecture also fully suppresses row hammer interference, because the active region isn’t shared with adjacent cells. The InGaZnO VCT achieved more than 15µA/cell ON current and 1aA/cell OFF current. The researchers demonstrated the technology by successfully building a 275Mbit array with it, demonstrating its potential for future high-density, low-power DRAM technologies.

 

Above:

(a)   is a schematic of the oxide-semiconductor channel transistor DRAM. The InGaZnO VCT was integrated on a capacitor array, a different architectural scheme from silicon-based 4F2 DRAM devices.

(b)   is a cross-sectional TEM image of the InGaZnO VCT test structure, with the key technologies needed for DRAM applications described on the right nearby. The gate oxide and InGaZnO were formed in a 26nm-diameter vertical hole.

(c)   is a cross-sectional TEM showing the InGaZnO VCTs on high-aspect-ratio capacitors.

 Source:

IEDM2024 Paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F² Architecture,” S. Fujii et al, Kioxia Corp./Nanya Technology Corp. https://www.ieee-iedm.org/press-kit

Intel's Breakthrough in RibbonFET Transistor Scaling Demonstrates Silicon Viability for Future Nodes

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Extremely Scaled Transistors from Intel: Intel researchers will show that silicon can continue to support the extreme gate length scaling which future technology nodes require. They will describe how they built RibbonFET CMOS transistors (Intel’s version of nanosheets) with 6nm gate lengths at 45nm contacted poly pitch (CPP, the spacing between adjacent transistor gates), with no degradation of electron mobility (how fast electrons can move through a material). The researchers will show that electron mobility doesn’t degrade until 3nm Tsi (silicon thickness), below which electron scattering due to surface roughness becomes an issue. They will describe how they achieved good short channel control (≤100mV/V at <4nm Tsi), with extremely low threshold voltage at these gate lengths through clever workfunction engineering. The work shows that 3nm is a practical scaling limit for RibbonFETs.

The image illustrates the behavior of drain-induced barrier lowering (DIBL) vs. silicon thickness (Tsi) at LG=18nm. It shows a reduction as Tsi is scaled from 10nm to 1.5nm; however, DIBL reduction saturates at Tsi <4nm, below which very little gain is obtained. PMOS DIBL is elevated vs. NMOS DIBL at the same Tsi. Also shown are TEM micrographs of a 1NR transistor with various Tsi values down to 1.5nm.

The series of images are (a) TEM micrograph and EDX scan of a completed 6nm RibbonFET device on a 1NR vehicle, showing a disconnected subfin; (b - d) are high-resolution cross-section TEMs for Tsi=5.5nm, 3.1nm and 1.7nm respectively, at 6nm gate length on a 1NR vehicle

Sources:

IEDM 2024 Press Kit Paper #2.2, “Silicon RibbonFET CMOS at 6nm Gate Length,” A. Agrawal et al, Intel https://www.ieee-iedm.org/press-kit

TSMC 2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects

TSMC’s New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will unveil the world’s most advanced logic technology. It is the company’s forthcoming 2nm CMOS (i.e., N2), platform, designed for energy-efficient computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or 30% power reduction) at >1.15x chip density versus the most advanced logic technology currently in production, TSMC’s own 3nm CMOS (N3) platform, introduced in late 2022.

The new N2 platform features GAA nanosheet transistors; middle-/back-end-of-line interconnects with the densest SRAM macro ever reported (~38Mb/mm²); and a holistic, system-technology co-optimized (STCO) architecture offering great design flexibility. That architecture includes a scalable copper-based redistribution layer and a flat passivation layer (for better performance, robust CPI, and seamless 3D integration); and through-silicon vias, or TSVs (for power/signal with F2F/F2B stacking). The researchers say the N2 platform is currently in risk production and scheduled for mass production in 2H’ 25. N2P (5% speed enhanced version of N2) targets to complete qualification in 2025 and mass production in 2026.

The cross-sectional image shows that the N2 platform’s Cu redistribution layer (RDL) and passivation provide seamless integration with 3D technologies.

Graph showing that the new N2 high-density cells gain 14~15% speed@power vs. N3E FinFlex 2-1 fin cells across the Vdd range; a 35% power savings at higher voltage; and a 24% power savings at lower voltage

The graph above compares two CMOS technology nodes, TSMC's N3E and N2, specifically for Arm's A715 core. N3E FinFlex (2-1 Fin) architecture, represented by the blue dotted line, operates at higher power but achieves higher speed than previous nodes. Operating at voltages between 0.5V and 0.9V, the N3E design can achieve significant performance levels but comes with a power increase. Now, N2 NanoFlex HD (High-Density) Energy-Efficient Cells as in the The N2 node, marked by the green dotted line, introduces "NanoFlex" cells that are optimized for energy efficiency. Compared to N3E, it achieves similar speeds but with substantially lower power consumption, marking a shift toward lower power designs in advanced nodes.

Key Improvements:

• When shifting from 0.6V to 0.55V in the N3E architecture, there's a 15% reduction in speed but a 24% reduction in power.
• For N2, at 0.85V, there's a 14% reduction in speed and a 35% reduction in power compared to similar performance points in N3E.
• These efficiency improvements are essential for high-performance applications in power-sensitive environments.

In summary, TSMC's N3E focuses on performance with FinFlex technology, while N2's NanoFlex HD cells target power efficiency, marking a clear trend in CMOS architecture evolution for balancing power and speed.

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Sources: 

IEDM Press kit Paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” G. Yeap et al, TSMC https://www.ieee-iedm.org/press-kit

GM Ventures Invests $10 Million in Forge Nano to Boost EV Battery Technology with Atomic Armor

GM Ventures, the venture arm of General Motors, recently invested $10 million in Forge Nano, a materials science company known for its advanced battery technology. Forge Nano specializes in Atomic Layer Deposition (ALD), particularly its "Atomic Armor" technology, which enhances battery materials by applying ultra-thin coatings. This innovation improves the performance, lifespan, and charging speed of electric vehicle (EV) batteries. 

“GM Ventures’ primary goal is to bring disruptive technology into the GM ecosystem to improve products and processes,” said Anirvan Coomer, managing director of GM Ventures. “Forge Nano’s Atomic Armor technology has game-changing potential for our battery materials at significant scale. They have already demonstrated the ability to expand cathode capabilities, which is the most expensive battery cell component. This could unlock benefits for customers and the business.”

The investment is part of GM's broader strategy to secure a robust supply chain for its EVs, and the partnership will focus on optimizing battery cathode materials to improve energy density and reduce costs. With this funding, Forge Nano aims to expand its battery coating operations and develop lithium-ion battery prototypes at its Colorado facility. This collaboration is expected to boost the range and fast-charging capabilities of GM’s future EV batteries.

About Forge Nano:

Forge Nano is a materials science company specializing in advanced surface engineering technology, particularly Atomic Layer Deposition (ALD). Its proprietary technology, "Atomic Armor," applies ultra-thin coatings at the atomic scale to improve the performance and durability of materials, particularly for energy storage applications like electric vehicle (EV) batteries. Forge Nano's coatings help enhance battery life, efficiency, and fast-charging capabilities by preventing corrosion and boosting cathode material performance.

Founded in Colorado, Forge Nano has attracted significant investment from major corporations, including General Motors, Volkswagen, LG, and others. The company's solutions extend beyond the automotive industry, targeting sectors such as electronics, aerospace, and defense. With ongoing innovation, Forge Nano aims to revolutionize how materials perform in critical technologies such as semiconductors and batteries.

Sources: 

www.forgenano.com

Forge Nano Receives $10M Investment from GM Ventures to Pursue GM Battery Material Enhancements for Future Electric Vehicles - Forge Nano

ASM launches 200 mm PE2O8 silicon carbide epitaxy system

ASM has launched the PE2O8, a silicon carbide (SiC) epitaxy system designed to enhance power device production with improved yields and reduced costs. The PE2O8 targets key applications in electric vehicles, green energy, and AI data centers, addressing the need for chips with higher power performance in smaller form factors. Its dual-chamber design enables high throughput, process uniformity, and efficient maintenance, while supporting both 6" and 8" wafer processing. With advanced thermal control and recipe transfer capabilities, the PE2O8 system offers high reliability, making it ideal for SiC epitaxy on bare wafers and during chip fabrication.

ASM's PE2O8 is a high-productivity epitaxy system designed for silicon carbide (SiC) applications, enabling the production of power devices with higher yields and lower costs. It plays a crucial role in industries like electric vehicles, green energy, and AI data centers, where chips must meet high power specifications within smaller form factors. The PE2O8 system features dual reactors for easy chamber maintenance, cross-flow hot wall reactors for precise thermal control, and inductive heating for processing 6" and 8" wafers. It ensures process uniformity and recipe transfer from earlier platforms, making it highly reliable and cost-efficient for SiC epitaxy on bare wafers and in power device fabrication.

Raleigh, NC, USA, September 30, 2024 / New system extends ASM’s portfolio of industry benchmark single wafer silicon carbide epitaxy systems, the 6” PE1O6 and 8” PE1O8 systems, with a higher throughput, lower cost of ownership, dual chamber, single wafer, 6” and 8” compatible, silicon carbide epitaxy system.

Today at the 2024 International Conference on Silicon Carbide and Related Materials, ASM International N.V. (Euronext Amsterdam: ASM) introduced the PE2O8 silicon carbide epitaxy system, a new, dual chamber, platform for silicon carbide (SiC) epitaxy (Epi). Designed to address the needs of the advanced SiC power device segment, the PE2O8 is the benchmark epitaxy system for low defectivity, high process uniformity, all with higher throughput and low cost of ownership needed to enable broader adoption of SiC devices.

As the general electrification trend drives more power device manufacturers to utilize SiC for a growing number of high-power applications (such as for electric vehicles, green power, and advanced data centers) the expanded demand and requirements for lower cost for SiC is causing a transition from 6” to 8” SiC substrates. At the same time, SiC device manufacturers are designing higher power devices that will benefit from better SiC epitaxy.

Utilizing a unique design, the dual chamber PE2O8 system deposits SiC with ultra precise control, enabling benchmark higher yield and higher throughput. The highly compact, dual chamber design enables high productivity and low total costs of operation. Additionally, the system features an easy preventive maintenance approach helping to increase uptime and reduce the occurrence of unscheduled downtime. System deliveries have been ongoing to multiple customers globally, among them leaders in SiC power device manufacturing.

“We are at a critical inflection for silicon carbide power products, as our customers transition from 6” to 8” wafers”, said Steven Reiter, Corporate Vice President, and business unit head of Plasma and Epi at ASM. “Delivering a high-quality epitaxy process on larger wafers with defectivity control is critical, and we have been the industry benchmark for process uniformity with our novel chamber design. We have now extended our system capability to improve our process control and our value for customers with lower cost of ownership.”

Since 2022, ASM, through its new SiC Epi product unit has been developing and refining its single wafer SiC epitaxy system. With the structurally higher demand for electric vehicles and improvement of the overall SiC wafer and device yield, the equipment market for SiC epitaxy has grown substantially in recent years.

About ASM International

ASM International N.V., headquartered in Almere, the Netherlands, and its subsidiaries design and manufacture equipment and process solutions to produce semiconductor devices for wafer processing, and have facilities in the United States, Europe, and Asia. ASM International's common stock trades on the Euronext Amsterdam Stock Exchange (symbol: ASM). For more information, visit ASM's website at www.asm.com.

Sources:

PE2O8 SiC epitaxy | ASM