Showing posts with label Lam Reserach. Show all posts
Showing posts with label Lam Reserach. Show all posts

Tuesday, November 7, 2023

Molybdenum: The New Frontier in Semiconductor Metallization according to Lam Research

The semiconductor industry is facing a significant shift as Molybdenum (Mo or Moly as the Americans say) is tipped to replace tungsten in chip manufacturing due to its superior atomic-scale properties. Kaihan Ashtiani, Corporate Vice President and General Manager at Lam Research, highlights the critical attributes of moly that make it the ideal choice for advanced devices. The company is at the forefront, aiding chipmakers in the transition with its ALTUS® product family, drawing from its pioneering work in Tungsten ALD and expertise in 3D NAND technology.

The semiconductor sector is on the cusp of a pivotal transition with molybdenum poised to supersede tungsten for interconnect metallization in response to the stringent scaling demands of modern chipmaking. Molybdenum's edge lies in its low resistivity and ease of integration into existing semiconductor processes, including atomic layer deposition (ALD) and chemical-mechanical planarization (CMP). These properties, combined with its minimal diffusivity into dielectric materials—thus negating the need for a barrier liner—make moly the preferred candidate for next-generation devices. Kaihan Ashtiani of Lam Research articulates the advantages of moly over other metals like cobalt and copper and underscores Lam's commitment to facilitating this industry shift. Leveraging decades of expertise and innovation in tungsten ALD and the transition from 2D to 3D NAND, Lam's ALTUS® product line is instrumental in enabling widespread adoption of molybdenum. This shift is not just theoretical; major chipmakers are actively exploring moly integration, marking a significant evolution in semiconductor fabrication.

The ALTUS® system by Lam Research is a suite of metal deposition tools used in semiconductor manufacturing, particularly for the deposition of tungsten and potentially other metals like molybdenum. These systems are designed to deposit metals by CVD or later named PNL (Pulsed Nanolayer deposition) and today marked as Atomic Layer Deposition (ALD- yeah!), which allows for extremely fine control of film thickness and composition at the atomic level, crucial for creating the tiny, densely packed structures found on modern integrated circuits.

For tungsten, the ALTUS® system has been a workhorse in the industry for the deposition of tungsten films, especially in the fabrication of the contact and via layers of integrated circuits. The ALD process ensures excellent step coverage, conformality, and uniformity even in very high aspect ratio structures. This is particularly important for Logic, DRAM, and 3D NAND applications, where the precise control of the tungsten film's electrical and physical properties is critical for device performance.

ALTUS applications

Logic devices, metallization needs to meet the requirements of increasingly smaller geometries and higher performance. The precision of ALD with tungsten and potentially molybdenum is essential for creating the necessary electrical connections without compromising the device's integrity.
Dynamic Random-Access Memory (DRAM) requires highly reliable and conductive connections as it is constantly refreshed to maintain data. The metallization process for DRAM needs to ensure that the metal films provide low resistivity and high reliability for the memory to function correctly.
In 3D NAND flash memory, multiple layers of memory cells are stacked vertically. This requires extremely uniform metal layers across all the stacked levels. The ability of the ALTUS® system to deposit tungsten and potentially molybdenum with high uniformity and excellent conformal coverage is vital for the success of 3D NAND devices.


Thursday, October 19, 2023

ASML and Lam Research Navigate US Chip Restrictions with Continued Focus on China

The evolving landscape of the global semiconductor industry, marked by the escalating US chip curbs, has seen two industry leaders, ASML and Lam Research, maintain a significant focus on the Chinese market. ASML, the Dutch semiconductor behemoth, has reported a remarkable surge in its sales to China. As they dominate the market for DUV lithography machines, essential for chip production, sales to China for ASML soared to €2.44 billion ($2.58 billion) in the recent quarter, nearly doubling the figures from the previous one. Meanwhile, Lam Research, a US chipmaking equipment supplier for CVD, ALD and Etch, is experiencing a year-on-year decline in revenue by 31.4% to $3.5 billion in the quarter ending Sept. 24, remains buoyant about the Chinese market. With China accounting for a staggering 48% of its total revenue, up from 30% the previous year and 26% in the preceding quarter, CEO Tim Archer remains optimistic. He emphasized that the new U.S. export restrictions brought no unforeseen challenges and anticipates sustainable business growth in China, citing the country's long-term objectives.

Photo : ASML on X

However, it's not all smooth sailing. As the US and the Netherlands tighten their grip on chip equipment exports in an attempt to curb China's burgeoning semiconductor industry, challenges arise for these giants. Notably, Lam Research's shares fell by over 5% in extended trading after Archer's announcement. Furthermore, even though both ASML and Lam Research foresee continued demand from China, the trajectory remains uncertain with the intricate web of export controls and regulations. Still, with giants like KLA, Applied Materials, Tokyo Electron, and the aforementioned firms steering the ship, the semiconductor industry remains hopeful about navigating these turbulent waters.

ASML System sales by region 3Q/2023 (


ASML stays optimistic on China as sales surge amid U.S. chip curbs - Nikkei Asia

Lam Research sees no material impact from new U.S. chip curbs - Nikkei Asia

Thursday, April 8, 2021

Why China denied Applied Materials take over of Hitachi Kokusai

According to a recent analysis by Robert Castellano (Seeking Alpha/The Information Network LINK), Hitachi Kokusai holds a strong position in tube/non-tube LPCVD and oxidation/diffusion semiconductor equipment. For some time Applied Material has planned the acquisition of Kokusai that would have increased its global market share, for silicon wafer processing equipment by adding a big segment that it does not have in its product portfolio - LPCVD, Diffusion, and ALD Furnaces. According to the market assessment, Hitachi Kokusai holds a leading market share in this segment over No. 2. Tokyo Electron. 

Castellano brings up the interesting observation that "China blocked Applied Materials' acquisition of Kokusai while permitting the Marvell-Inphi deal the same week". Basically meaning that there are more than just US-China Trade issues behind the decision. He concludes that "China is developing a home-grown equipment industry infrastructure, and the deal would impede on that effort." and follows up by breaking up the segments and global competitive situation as below.

Summary by Castellano of China OEM active in LPCVD, Diffusion, and ALD segments vs. the global leaders

China’s NAURA makes oxidation and diffusion furnaces and its products have captured a significant share (40-50%) of YMTC’s thermal process equipment purchases, per our channel checks. In RTP, major players include Applied Materials, Tokyo Electron, and Mattson Technology.

NAURA is developing etchers and deposition equipment for 7nm and 5nm nodes. NAURA has a large product offering, and its customers consist of SMIC, Hua Hong, YMTC, and GTA Semiconductors.

NAURA also makes thermal furnaces and has a 45% share of China’s memory maker YMTC purchases. Whereas NAURA sold 8 etch systems and 6 CVD and ALD deposition systems to Chinese semiconductor companies, the company sold 34 furnaces in 2019 as well as 16 cleaning systems.

Shenyang Piotech also supplies PECVD and ALD deposition equipment. Piotech received orders for 4 PECVD (for SiN, SiO2) systems from YMTC, and is also receiving repeat orders from Hua Hong, and SMIC.

The size of the semiconductor equipment market and the small share China's equipment suppliers currently enjoy compared to foreign suppliers (source: The Information Network LINK)

Thursday, January 28, 2021

Micron Delivers Industry’s First 1α DRAM Technology

Micron recently announced that they are shipping memory chips built using the world’s most advanced DRAM process technology, which offers major improvements in bit density, power and performance. This is an astonishing feat of nanofabrication. 

Micron announcement: Micron Delivers Industry’s First 1α DRAM Technology

Micron’s 1α DRAM node will facilitate more power-efficient, reliable memory solutions and provide faster LPDDR5 operating speeds for mobile platforms that require best-in-class LPDRAM performance. Micron’s innovation brings the industry’s lowest-power mobile DRAM, with a 15% improvement in power savings,1 allowing 5G mobile users to perform more tasks on their smartphones without sacrificing battery life.

To find out more watch Thy Tran, vice president of DRAM Process Integration at Micron previously with Qimonda explain how to realize this amazing technology.

According to more details given in a Blog by Thy Tran, Micron uses Quadruple Patterning or Quad Patterning to realize the most critical lithography layers, which employ multiple ALD process steps and has become one of the biggest ALD market segment over recent years. See the video below by Lam Research for some more insights!

Quad patterning process flow (Image: Lam Research)

Wednesday, December 9, 2020

ALD to take over more and more as CVD and spin-on processes no longer are viable for 3D NAND

EE Times reports [LINK] about the recently announced Striker FE from Lam Research, an enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM. It employs advanced dielectric gapfill technology the company has dubbed “ICEFill” for filling 3D NAND and DRAM structures — as well as logic devices — in emerging nodes. 

Lam Research’s recently announced Striker FE enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM
Lam Research Striker FE - Key applications (LINK):
  • Gapfill dielectrics
  • Conformal liners
  • Patterning spacers and masks
  • Hermetic encapsulation
  • Etch stop layers
  • Optical films
The need for gapfill methods isn’t new, said Aaron Fellis, vice president and general manager of Dielectric ALD products, but the traditional ones no longer meet today’s needs, especially as 3D NAND is stacked higher. “They’re so tall and they have a number of different features that get etched through them to enable the integration of different steps,” he said. “Ultimately, they need to get filled back up with a dielectric material, most commonly silicon oxide.”

Legacy techniques, such as chemical vapor deposition, diffusion/furnace, and spin-on processes that are normally used as gapfill for semiconductor manufacturing are no longer viable for 3D NAND, Fellis said, due to trade-offs between quality, shrinkage, and gapfill voids. “They tend to shrink and distort the actual structure that the customer is building and designing.”

According to Risto Puhakka, president of VLSIresearch, Lam Research is a dominant player for ALD technology, and the demands of its technology reflect those placed on memory. It’s all about increasing density for applications, such as artificial intelligence, that require more bits while keeping costs the same, and that includes gapfill capabilities as the memories such as 3D NAND are stacked higher, he said. “The stacking becomes more and more challenging from the manufacturing perspective, but the chip makers themselves get it a little bit little anxious about how much they have to spend.” Sticking with a known material such as silicon oxide adds some predictability because it’s well understood

But just as 3D NAND stacking will eventually hit limits, so will the gapfill techniques and ALD technology, added Puhakka. “It has its own roadmap and limitations.”

Monday, September 21, 2020

Lam Research launch the advanced Striker® FE platform for 3D chip architectures like 3DAND and DRAM

  • Lam has been leading gap fill for a long time and their new proprietary surface modification technique (ICEFill) to achieve highly preferential bottom-up and void-free gapfill while retaining the film quality inherent to atomic layer deposition (ALD).
  • The platform is specially prevalent in 3D NAND devices, as well as prevents collapse issues in DRAM and logic devices.
  • The Striker FE platform with ICEFill technology is part of the Striker ALD product family.
  • Lam applied for ICEFill USPTO Trade Mark February 2020 (LINK)
New Striker® FE enhanced atomic layer deposition platform addresses semiconductor manufacturing challenges for 3D NAND, DRAM, and Logic chipmakers

FREMONT, Calif., Sept. 21, 2020 (LINK) -- Lam Research Corp. (Nasdaq: LRCX) today announced the advanced Striker® FE platform, a new processing solution for manufacturing high-aspect-ratio chip architectures. Striker FE utilizes an innovative, first of its kind ICEFill™ technology for filling extreme structures in 3D NAND, DRAM, and logic devices at emerging nodes. This system delivers the continued cost and technology scaling that is required to meet the semiconductor industry roadmap.


Keyword Cluster for Lam Research Gapfill (Patbase) 
Lam Research ALD Product family Striker.

Traditional methods of gapfill for semiconductor manufacturing include legacy chemical vapor deposition, diffusion/furnace, and spin-on processes. These techniques are no longer viable for today’s 3D NAND requirements, as they are limited by the tradeoffs between quality, shrinkage, and gapfill voids. In contrast, Lam’s Striker ICEFill harnesses a proprietary surface modification technique to achieve highly preferential bottom-up and void-free gapfill while retaining the film quality inherent to atomic layer deposition (ALD). The ICEFill technology removes the existing limitations for filling high-aspect-ratio features which are especially prevalent in 3D NAND devices, as well as prevents collapse issues in DRAM and logic devices.


“Our goal is to provide customers with the most enabling ALD technology,” said Sesha Varadarajan, senior vice president and general manager of the Deposition product group at Lam Research. “This technology combines the ability to produce high quality oxide films with superior gapfill performance, in a single processing system with the productivity advantages offered by our industry leading quad station module architecture.”

The Striker FE platform with ICEFill technology is part of the Striker ALD product family. For more information about the Striker product family visit the product page.

Wednesday, March 4, 2020

Lam’s new Sense.i Etch platform delivers industry-leading output and innovative sensor technology

  • Lam Research (NASDAQ:LRCX) introduces the Sense.i tool, which etches finer 3D details on silicon wafers for chips.
  • The Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs
  • 3D features can help Lam customers like Samsung and SK Hynix put more memory capacity into small areas such as smartphones.
FREMONT, Calif., March 03, 2020 (LINK) -- Lam Research Corp. (Nasdaq: LRCX) today announced the launch of a completely transformed plasma etch technology and system solution, designed to provide chipmakers with advanced functionality and extendibility required for future innovation. Lam’s groundbreaking Sense.i™ platform offers unparalleled system intelligence in a compact, high-density architecture to deliver process performance at the highest productivity, supporting logic and memory device roadmaps through the coming decade.

With core technology evolved from Lam’s industry-leading Kiyo® and Flex® process modules, the Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs. As dimensions shrink and aspect ratios increase, the Sense.i platform is designed to support future technology inflections.

Powered by Lam’s Equipment Intelligence® technology, the self-aware Sense.i platform enables semiconductor manufacturers to capture and analyze data, identify patterns and trends, and specify actions for improvement. Sense.i also features autonomous calibration and maintenance capabilities that reduce downtime and labor costs, and delivers machine learning algorithms that allow the tool to self-adapt to minimize process variations and maximize wafer output.

The Sense.i platform has a revolutionary space-saving architecture that will help customers meet their future wafer output targets by producing more than a 50% improvement in etch output density. As semiconductor manufacturers develop smarter, faster, and denser chips, processes are rapidly growing in complexity and number of steps. This requires a greater number of process chambers in a fab and reduces total output for a given floor space. The Sense.i platform’s smaller footprint benefits either a new fab build or a fab undergoing a node-to-node technology conversion.

“Lam is introducing the most innovative etch product that has been developed in the last 20 years,” said Vahid Vahedi, senior vice president and general manager of the Etch product group at Lam Research (LRCX). “Sense.i extends our technology roadmap to meet our customers’ next-generation requirements while solving the critical cost scaling challenges they’re facing in their business. With more than four million wafers processed on Lam etch systems every month, Lam has an installed-base that provides extraordinary learning to innovate, design, and produce the best tools for semiconductor manufacturing.”

Friday, August 9, 2019

Lam Research Adds Global Wafer Stress Management Solutions to Portfolio to 3D NAND Scaling

FREMONT, Calif., Aug. 07, 2019 (GLOBE NEWSWIRE) — Lam Research Corp. (Nasdaq: LRCX) today announced new solutions to help customers increase chip memory density, which is needed for applications such as artificial intelligence and machine learning. With the introduction of VECTOR® DT for backside deposition and EOS® GS wet etch for film removal on backside and bevel, Lam continues the expansion of its stress management product portfolio.

While high aspect ratio deposition and etching are key enablers for 3D NAND scaling, the combination of increasing the number of layers while controlling wafer bow due to cumulative stress in the film stack has become a major challenge. Such stress-induced wafer distortion has a significant impact on wafer yield due to degraded lithography depth-of-focus, overlay performance, and structural distortion. To improve overall yield, wafer-, die-, and feature-level stresses need to be carefully managed at various steps throughout the entire manufacturing process flow, at times potentially resulting in the preclusion of otherwise performance-enhancing process steps due to their stress characteristics.

Designed to provide a cost-effective solution for controlling wafer bow in 3D NAND manufacturing, the VECTOR DT system is the newest addition to Lam’s plasma-enhanced chemical vapor deposition (PECVD) product family. VECTOR DT provides a single-step solution for wafer shape management by depositing a tunable counter-stress film on the back of the wafer without contacting the front side, thereby enabling improved lithography results, reduced bow-induced failures, and integration of high performance but highly stressed films. With strong customer adoption since its debut, the VECTOR DT installed base continues to grow as customers are transitioning to more than 96 layers.

In addition to depositing a counter stress film, Lam provides the flexibility to remove backside films, allowing customers to adjust wafer stress during the 3D NAND manufacturing flow. Lam’s EOS GS wet etch product complements the VECTOR DT by simultaneously removing backside and bevel films with industry-leading wet etch uniformity, while fully protecting the wafer front side. As part of a comprehensive wafer bow management solution, Lam’s EOS GS has also been adopted by memory manufacturers worldwide.

“As our customers continue to dramatically increase the number of memory cell layers, the cumulative stress and wafer bow can exceed the limits of a lithography tool. Minimizing stress-induced distortion is critical for achieving the desired yield and enabling the cost-per-bit roadmap,” said Sesha Varadarajan, senior vice president and general manager of the deposition product group at Lam Research. “With the addition of the VECTOR DT and EOS GS systems, we are expanding our stress management solutions portfolio for managing global stress in support of our customers’ vertical scaling roadmap.”
Source: Lam Research LINK

By Abhishekkumar Thakur

Thursday, July 4, 2019

Lam Research’s Richard Gottscho shares his perspective advanced processes for 5 and 3 nm

5nm, 3nm, or something in between? Lam Research’s Richard Gottscho shares his perspective on how chipmakers should prepare for the next wave of advanced processes in a Semiconductor Engineering article.

Semiconductor Engineering: LINK

Thursday, September 6, 2018

Atomic Layer Etching: Rethinking the Art of Etch

Yet another Must Read ALE journal publication from Lam Reaserach Keren Kanarik and team. Please enyoy!

Atomic Layer Etching: Rethinking the Art of Etch

Keren J. Kanarik, Samantha Tan, and Richard A. Gottscho
The Journal of Physical Chemistry Letters 2018 9 (16), 4814-4821
DOI: 10.1021/acs.jpclett.8b0099
Atomic layer etching (ALE) is the most advanced etching technique in production today. In this Perspective, we describe ALE in comparison to long-standing conventional etching techniques, relating it to the underlying principles behind the ancient art of etching. Once considered too slow, we show how leveraging plasma has made ALE a thousand times faster than earlier approaches. While Si is the case study ALE material, prospects are better for strongly bound materials such as C, Ta, W, and Ru. Among the ALE advantages discussed, we introduce an ALE benefit with potentially broad application—the ALE smoothing effect—in which the surface flattens. Finally, regarding its well-established counterpart of atomic layer deposition (ALD), we discuss the combination of ALE and ALD in tackling real world challenges at sub-10 nm technology nodes