Showing posts with label CMOS Scaling. Show all posts
Showing posts with label CMOS Scaling. Show all posts

Friday, September 13, 2024

AlixLabs Qualifies APS™ for Use In 300-millimeter Silicon Wafer Designs

Swedish semiconductor startup clears technical hurdle for leading-edge process use on 300 mm wafer design*.

Scanning electron microscopy (SEM) images of amorphous silicon lines before (top) and after the APSTM process: nominal 40 nm line width and 40 nm half-pitch converted to lines with width below 15 nm and a half-pitch of 20 nm. Bild: Alixlabs

Stockholm, Sweden – September 12th, 2024 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), announces that it has qualified its APS™ (ALE Pitch Splitting) process on a 300-millimeter silicon wafer design, marking one of its final steps towards commercial adoption. APS™ provides atomic-scale precision and pattern fidelity with critical dimensions below 15 nanometers for both single crystalline and amorphous silicon.

AlixLabs APS™ is designed to reduce the cost of leading-edge manufacturing, sub-7-nanometer, where feature sizes of less than 20 nanometers are required. An estimated cost saving of up to 40 percent per mask layer can be achieved with APS™ rather than relying on EUV lithography, and complex self-aligned multi patterning schemes.


AlixLabs' patented and wordmarked APS™ IP – short for Atomic Layer Etch (ALE) Pitch Splitting, here demonstrated in a simple animation.

“Proving that APS™ works on lithography designs on 300-millimeter wafers, is what we’ve all worked on since we founded AlixLabs in 2019,” says CEO and co-founder Dr. Jonas Sundqvist. “Not only do we aim to provide chip manufacturers wafer processing equipment that can create 20-nanometer half-pitch lines and critical dimension below 15 nanometers on silicon, we aim to do that at a lower cost and a more sustainable way than other technologies”
“We are also able to provide record breaking 3-nanometer critical dimension features on gallium phosphide (GaP) wafers today showing that APS™ can scale far into the future beyond what is needed today,” adds CTO and co-founder Dmitry Suyatin.

APS™ is positioned as an alternative to self-aligned double and quadruple patterning (SADP and SAQP). It allows for splitting dense line structures that can act as a foundation for transfer-etch into various materials such as dielectrics, metals, metal nitrides, and high-k dielectrics. The structures created with APS™ can also be used as-is for critical device features such as the fins in FinFET-type transistors due to extremely low surface damage.

AlixLabs’ goal is to supply leading semiconductor manufacturers, in both logic and memory segments. By enabling them to simplify and speed up their chip production at least fourfold for each critical mask layer by replacing four plasma wafer processing chambers in the SADP process flow with one APS™ chamber and eightfold correspondingly in SAQP. Finally, AlixLabs contributes overall to more sustainable semiconductor manufacturing.

*EBL patterned 300 mm wafers were provided by Fraunhofer IPMS Center Nanoelectronic Technologies (CNT) and financed by Ascent+ European Union's Horizon 2020 research and innovation program under GA No 871130.

Sources:

Sunday, June 16, 2024

ASML Unveils Hyper-NA EUV: Pioneering New Frontiers in Chip Innovation and Efficiency

ASML, the leader in lithography technology for semiconductor manufacturing, has launched its latest breakthrough: the Hyper-NA EUV tool and Intel being the first customer getting its first machine earlier this year. This leading-edge technology, which boosts the numerical aperture (NA) from 0.55 to 0.75, is poised to revolutionize chip design by enabling unprecedented levels of transistor density. Scheduled for introduction around 2030, Hyper-NA promises to extend the capabilities of chipmakers far beyond current limits, opening up new possibilities for intricate and powerful chip designs.

The presentation announcing ASML's Hyper-NA EUV technology was delivered by the company's former president, Martin van den Brink, at imec's ITF World event in Antwerp. 

Reduction in Double Patterning Complexity: Hyper-NA EUV technology simplifies the lithography process by reducing the need for double patterning, i.e., like Litho-Etch-Litho-Etch (LELE) etc., a method that involves aligning two masks perfectly to create intricate chip designs. By providing higher resolution and precision, Hyper-NA EUV minimizes the challenges and costs associated with double patterning, streamlining production and enhancing overall efficiency for chipmakers. However, there are a myriad of multi-patterning technologies deployed out there and SMIC, the main Chinese foundry, is reportedly using sextuple-patterning for its 5 nm technology.


Hyper-NA EUV technology is designed to significantly increase the productivity of semiconductor manufacturing, enabling the processing of 400 to 500 wafers per hour. This improvement will help chipmakers meet the growing demand for high-performance chips more efficiently, reducing production time and costs while maintaining high precision and quality.

The adoption of Hyper-NA EUV presents a myriad of opportunities for the semiconductor industry. As Intel has already installed the first High-NA systems, showcasing the potential of these advanced tools to enhance processor performance. As other industry leaders like TSMC, Samsung, Micron, and SK Hynix explore the adoption of High-NA and eventually Hyper-NA, the competitive landscape is set for a dynamic transformation. Innovations such as advanced polarizers to overcome light polarization issues and improvements in resist materials and etch selectivity will enable more precise and efficient chip manufacturing.

ASML’s Hyper-NA EUV technology is not just a short-term solution but part of a long-term roadmap that will sustain chip innovation for the next decade and beyond. Collaborative research and development efforts, including Imec’s simulations and Zeiss’s lens designs, highlight the cooperative spirit driving this technological advancement. As chip designers like Nvidia, Apple, and AMD leverage these tools at leading foundries such as TSMC, the future of chip design looks brighter than ever, promising enhanced productivity, technological leadership, and sustained growth. Hyper-NA EUV is set to redefine what is possible in the world of semiconductors, driving the industry towards new heights of efficiency and performance.

Monday, January 8, 2024

Intel Receives ASML's First High-NA EUV Lithography Scanner, Pioneering Next-Gen Semiconductor Manufacturing

ASML has delivered its groundbreaking High-NA EUV lithography scanner, the Twinscan EXE:5000, to Intel Oregon. Marking a significant technological leap, this first-of-its-kind scanner boasts a 0.55 NA lens, enabling 8nm resolution for advanced semiconductor manufacturing. Designed for process technologies beyond 3nm, it promises to enhance chip production efficiency and reduce costs. Intel's early adoption of this state-of-the-art equipment, valued between $300-$400 million, positions them at the forefront of the industry, potentially setting new standards in High-NA manufacturing. This development represents a major milestone in semiconductor technology, signaling a new era of innovation and capability in chip production.



Friday, December 29, 2023

TSMC Set to Revolutionize Chip Technology with Trillion-Transistor Packages by 2030

In a groundbreaking announcement at IEDM, TSMC has unveiled ambitious plans to develop chip packages harboring over one trillion transistors and monolithic chips with more than 200 billion transistors by 2030. This visionary goal is set to be achieved through the development of advanced production nodes, including 2nm-class N2 and N2P, and even finer 1.4nm-class A14 and 1nm-class A10 processes. Despite the slowdown in process technology development and existing technical and financial challenges, TSMC remains optimistic about accomplishing these targets within the next five to six years. The company, renowned as the world's largest semiconductor foundry, is confident in overcoming industry hurdles to bring these complex, multi-chiplet systems and more intricate monolithic chips to the forefront of technology. This development signals a significant leap in chip architecture, promising transformative advancements in the tech industry.



Source:

Monday, December 11, 2023

Intel Showcases Groundbreaking Transistor Innovations at IEDM 2023

At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel introduced significant advancements in transistor technology that continue to drive Moore's Law forward. Intel's Components Research group demonstrated innovative 3D stacked CMOS transistors, enhanced with backside power and direct backside contacts. This breakthrough in transistor architecture allows for more efficient scaling and improved performance, marking a first in the industry.

3D Stacked CMOS Transistors

Intel displayed the ability to vertically stack complementary field effect transistors (CFET) with a scaled gate pitch down to 60 nanometers (nm). This technology, combined with backside power and direct backside contacts, underscores Intel's leadership in gate-all-around transistors and its capacity to innovate beyond RibbonFET.


Beyond Five Nodes in Four Years

Intel's PowerVia, set for manufacturing readiness in 2024, represents the first implementation of backside power delivery. At IEDM 2023, the company identified ways to extend and scale backside power delivery beyond PowerVia, utilizing backside contacts and other novel vertical interconnects for efficient device stacking.

Integration of Silicon and GaN Transistors

Intel successfully integrated silicon transistors with gallium nitride (GaN) transistors on the same 300 mm wafer. The "DrGaN" technology showcased at the event demonstrates Intel's advancements in high-performance integrated circuits for power delivery.

Advances in 2D Transistor Space

Intel presented high-mobility transition metal dichalcogenide (TMD) 2D channel materials, showcasing prototypes of high-mobility TMD transistors for both NMOS and PMOS. Additionally, Intel revealed the world’s first gate-all-around (GAA) 2D TMD PMOS transistor and the first 2D PMOS transistor fabricated on a 300 mm wafer.


These developments by Intel represent a significant stride in semiconductor research, promising to enhance the efficiency and capabilities of future computing technologies.

Friday, December 8, 2023

IBM and Samsung Revolutionize Semiconductor Industry with Groundbreaking VTFET Transistor Technology

In a breakthrough development, IBM and Samsung have introduced a new transistor architecture named Vertical-Transport Nanosheet Field-Effect Transistors (VTFETs), potentially outperforming traditional FinFETs. This exciting innovation was discussed in the AAC Exclusive article, "A Chat With IBM Researchers Who Built the New 'VTFET' Transistor," featuring insights from IBM researchers Brent Anderson and Hemanth Jagannathan.


Comparison of a VTFET (left) vs. a lateral FET (right) transistor with current flowing through them. FinFETs have a limited gate pitch, scaled down to ~48nm, while VTFETs offer more scaling potential with a longer gate length due to their vertical design.

VTFETs offer significant improvements in performance and area scaling, potentially reducing energy usage in devices by up to 85% compared to FinFETs. These transistors operate with a vertical orientation, allowing for longer gates and thicker spacers and source-drains, which reduce resistance and capacitance. This design enables smaller transistor size while enhancing performance.

Anderson and Jagannathan's roles at IBM have been pivotal in the development of VTFETs. Anderson, who joined IBM in 1991, has been instrumental in driving the technology design for various logic nodes, including VTFET. Jagannathan, with IBM for 15 years, has managed process technology groups and played a crucial role in hardware research for VTFET.

Their work signifies a significant step forward in semiconductor technology, promising higher density, performance, and energy efficiency. This innovation represents a potential future for Moore's law scaling, alongside other advancements like monolithic 3D and chip stacking technologies. The real-world implementation of VTFETs is eagerly anticipated, with the technology expected to mature in the coming years.


Monday, October 23, 2023

TSMC To Report Breakthrough in NMOS Nanosheets Using Ultra-Thin MoS2 Channels at IEDM 2023

A TSMC-led research team, in collaboration with National Yang Ming Chiao Tung University and National Applied Research Laboratories, has unveiled promising results for using ultra-thin transition metal dichalcogenides (TMDs), specifically MoS2, as the channel material in NMOS nanosheets. Their innovative approach deviates from the conventional method of thinning Si channels. The team's devices exhibited impressive performance metrics: a positive threshold voltage (VTH) of ~1.0 V, a high on-current of ~370 µA/µm at VDS = 1 V, a large on/off ratio of 1E8, and a low contact resistance ranging between 0.37-0.58 kΩ-µm. These outcomes were primarily attributed to the introduction of a novel C-shaped wrap-around contact, which enhances contact area, and an optimized gate stack. While the devices demonstrated satisfactory mechanical stability, a challenge remains in addressing defect creation within the MoS2 channels. This groundbreaking study, titled "Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact" by Y-Y Chung et al., is a pivotal step forward in nanosheet scaling using TMDs.


ALD is a the technique for the precise and uniform synthesis of MoS₂, especially for semiconductor applications on large-scale wafers. The choice of precursors plays a crucial role in achieving optimal deposition characteristics. Mo (CO) 6 and H2S have been identified as the primary precursors for depositing molybdenum and sulfur components, respectively. These precursors have demonstrated the capacity for self-limiting growth behavior within a specific ALD temperature window, leading to uniform MoS₂ layers. Notably, this process has been successfully scaled up to achieve highly uniform film growth on large 300 mm SiO2/Si wafers, marking its potential for industry-level manufacturing. The ability to maintain uniformity and thickness control on such wafers emphasizes the potential of ALD in integrating MoS₂ into next-generation electronic devices and further underscores the significance of selecting appropriate precursors for optimal deposition outcomes. Other precursors have been investigated. MoCl₅ and MoF₆ serve as alternative molybdenum sources. For the sulfur component, H₂S is commonly paired with molybdenum precursors, but (CH₃)₂S has also been explored. The choice of these precursors directly impacts the properties of the resulting MoS₂ film in the ALD process and therefore precursor development for 2D MoS2 is a hot field of ongoing research.

While deposition methods are abundant, etching processes are comparatively scarce. Recent research by Elton Graugnard et al also introduces a thermal Atomic Layer Etching (ALE) technique for MoS2, leveraging MoF6 for fluorination, alternated with H2O exposures, to etch both crystalline and amorphous MoS2 films. This process has been characterized using various analytical techniques like QCM, FTIR, and QMS. The etching is temperature-dependent, with a significant increase in mass change per cycle as temperature rises. The mechanism involves two-stage oxidation of Mo, producing volatile byproducts. The resultant etch rates were established for different films, and post-etch annealing rendered crystalline MoS2 films. The thermal MoS2 ALE introduces a promising low-temperature method for embedding MoS2 films in large-scale device manufacturing.



Monday, September 26, 2022

Bottom-up PEALD of SiO2 by growth inhibition for seamless gap-fill process

Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process

Yoenju Choi, Taehoon Kim, Hangyul Lee, Jusung Park, Juhwan Park, Dongho Ryu & Woojin Jeon

Scientific Reports volume 12, Article number: 15756 (2022)

The design-rule shrinkage in semiconductor devices is a challenge at every step of the integration process. In the gap-fill process for isolation, the seam and void formation cannot be suppressed by using a deposition process, which even has excellent step coverage. To achieve seamless gap fill in the high-aspect-ratio structure, which has a non-ideal etch profile such as a negative slope, the deposition process should be able to realize the “bottom-up growth” behavior. In this work, the bottom-up growth of a SiO2 plasma-enhanced atomic layer deposition (PE-ALD) process in a trench structure was investigated by using a growth inhibition process employing plasma treatment. N2 and NH3 plasma pre-treatments were employed to suppress the growth of the SiO2 PE-ALD process without any contamination, and the inhibition mechanism was investigated by performing surface chemistry analyses using X-ray photoelectron spectroscopy. Furthermore, the gap-fill characteristics of the SiO2 PE-ALD process were examined, depending on the process conditions of NH3 plasma pre-treatment, by performing cross-sectional field emission scanning electron microscopy measurements. Finally, a seamless gap-fill process in a high-aspect-ratio trench pattern was achieved by the bottom-up growth behavior of SiO2 PE-ALD using NH3 plasma pre-treatment.


Saturday, May 8, 2021

Webinar - Decadal Plan for Semiconductors: New Compute Trajectories for Energy Efficiency

SIA/SRC [LINK]: Computing and, more generally, Information and Communication Technologies (ICT) is the social-economic growth engine of the modern world. Rapid advances in computing have provided increased performance and enhanced features in each new generation of products in nearly every market segment, whether it be servers, PCs, communications, mobile, automotive, or entertainment, among others.

The use of information and communication technologies continues to grow without bounds dominated by the exponential creation of data that must be moved, stored, computed, communicated, secured and converted to end user information. Ever-rising energy demands for computing versus global energy production are creating new risk, therefore new computing paradigms need to be discovered that would result in dramatically improved energy efficiency of computing.

This webinar intends to identify a compelling research agenda based on the Decadal Plan for Semiconductors, led by SRC to discover new approaches to computing with a focus on changing the current mainstream compute trajectory. The underlying technical challenge is bit-utilization efficiency in computation.



Friday, April 30, 2021

The US Patent Office has approved AlixLabs’ patent application for nanofabrication by ALE Pitch Splitting (APS)

(30 April 2021, Lund Sweden). The US Patent Office has approved AlixLabs’ (AlixLabs AB) patent application for nanofabrication by ALE Pitch Splitting (APS).

The US Patent Office has issued a patent (US10930515) on February 23, 2021. The patent covers methods to split nanostructures in half by a single process step using Atomic Layer Etching (ALE). The method has the potential to have a big impact on the semiconductor industry by enabling sustainable scaling of electronic components and shrink chip designs further in a cost-effective way. The method is complementary for single exposure Immersion and Extreme UV (EUV) Lithography and corresponding multiple patterning technologies like self-aligned double and quadruple patterning (SADP resp. SAQP) as well as directed self-assembly (DSA).

In direct comparison to mentioned more complicated and expensive methods, APS may cut the need for certain fab equipment investments considerably, reduce manufacturing cost and energy consumption as well as reduce greenhouse gas emission during the patterning processing by up to 50%, allowing greener and affordable way forward for the semiconductor industry.

AlixLabs aims at applications for the manufacturing of leading-edge sub 5nm Logic Devices and Memory Chips that are used for everyday consumer electronic devices, 5G and AI.

The company’s CEO Dr. Jonas Sundqvist comments:

After founding the company in 2019 we now move into very exciting times. The team has been expanded with Dr. Mohammad Karimi as Principal Scientist and we have several applications and projects in the pipeline for broadening our patent protection and creating further opportunities for commercial agreements starting now. Currently, we are taking on the first round of private investments and will expand operations for both core activities in Lund, Sweden, at NanoLund and Lund Nano Lab, and the IDEON Science Park in Sweden. In addition, we are heading to the heart of the European semiconductor industry in Dresden Germany for a lab to fab transfer to 300 mm silicon wafer process verification to get ready for customer demonstrations of APS.

The company’s CTO Dr. Dmitry Suyatin comments:

This patent is built on a surprising discovery by the inventors, which took place at Lund Nano Lab during the Master project by Dr. Sabbir A. Khan who has recently received his PhD from the University of Copenhagen and now continues his postdoctoral work at Niels Bohr Institute in Copenhagen.

About AlixLabs AB:

AlixLabs (www.alixlabs.com) is an innovative startup enabling the semiconductor industry to scale down Logic and Memory components in a cost-effective manner by the use of ALE Pitch Splitting (APS).

Background Information:



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Saturday, March 6, 2021

Thermal ALE of germanium rich SiGe by CU Boulder and ASM Microchemistry

Epitaxially grown SiGe is an important material for CMOS Logic. It is integrated as the channel material and by inserting a higher concentration of germanium the mobility of the transistor can be improved. The industry calls it Epi, but what is really referred to a thermal CVD process producing an epitaxially grown layer of silicon or silicon-germanium onto a single crystalline silicon wafer.

As CMOS scaling has progressed the IDMs and Foundries have moved from the planar field-effect transistor (FET) architecture to a narrow fin-based transition the FinFET. The next evolutionary step on the horizon will be the transition to a nanowire-based architecture forming a gate-all-around FET (GAA-FET). At some point in time beyond the 2 nm node, the lateral scaling possibility will hit a wall and it is foreseen that the CMOS scaling will gup upwards like other technologies in order to cram in more devices per unit area. In a first approach, it may be that the NMOS and PMOS transistors are rearranged from being processed next to each other to put one of them on top of the other. Intel recently presented this at IEDM2020 (LINK). Having done that you can foresee continuing on a vertical scaling path also for CMOS just like 3DNAND and start to build those skyscrapers.

When going vertical, you will need highly conformal deposition processes as provided by ALD and in high volume production since the event of 90 nm DRAM (Samsung) and 45 nm Logic (Intel), however, etch is a problem since the reactive ion etching process are typically directional with the plasma under low-pressure processing conditions used. Also, the Argon plasma ALE processes to etch Silicon, silicon Germanin gallium nitride, and III/V materials are directional or anisotropic as the etch guys say or non-conformal as we ALD people say.

Typically the best way to achieve isotropic etch conditions, meaning you remove material at the same rate or as for ALE the same amount per cycle (etch per cycle EPC), is to skip the plasma that causes the anisotropic etch. Here Dr Abdulgatov and co-workers in the famous SM George Lab, CU Boulder together with Varun Sharma and friends from ASM Microchemistry, one of Dresden's best shining ALD-Stars, publish a paper on Thermal ALE of germanium rich SiGe that is quite clever. Here using PVD Si0.15Ge0.85 samples, which are difficult to make by Epi due to the high Ge content. I think we will see more of this for also GaN, SiC and III/V materials coming up.


AI Abdulagatov, V Sharma, JA Murdzek, AS Cavanagh, SM George
Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films

Abstract: The thermal atomic layer etching (ALE) of germanium-rich SiGe was demonstrated using an oxidation and “conversion-etch” mechanism with oxygen (O2) or ozone (O3), hydrofluoric acid (HF), and trimethylaluminum [TMA, Al(CH3)3] as the reactants. The crystalline germanium-rich SiGe film was prepared using physical vapor deposition and had a composition of Si0.15Ge0.85. In situ spectroscopic ellipsometry was employed to monitor the thickness of both the SiGe film and the surface oxide layer on the SiGe film during thermal ALE. Using a reactant sequence of O2-HF-TMA, the etch rate of the SiGe film increased progressively with temperatures from 225 to 290 °C. At 290 °C, the SiGe film thickness decreased linearly at a rate of 0.57 Å/cycle with a surface oxide thickness of 18–19 Å. This etch rate was obtained using reactant pressures of 25, 0.2, and 0.4 Torr and doses of 1.5, 1.0, and 1.0 s for O2, HF, and TMA, respectively. The TMA and HF reactions were self-limiting and the O2 reaction was reasonably self-limiting at 290 °C. Using an O3-HF-TMA reaction sequence, the SiGe ALE etch rate was 0.42 Å/cycle at 290 °C. This etch rate was obtained using reactant pressures of 15, 0.2, and 0.4 Torr and dose times of 0.5, 1.0, and 1.0 s for O3, HF, and TMA, respectively. The O3, TMA, and HF reactions were all self-limiting at 290 °C. Atomic force microscopy images revealed that thermal ALE with the O2-HF-TMA or O3-HF-TMA reaction sequences did not roughen the surface of the SiGe film. The SiGe film was etched selectively compared with Si or Si3N4 at 290 °C using an O2-HF-TMA reaction sequence. The etch rate for the SiGe film was >10 times faster than Si(100) or Si3N4 that was prepared using low-pressure chemical vapor deposition. This selectivity for the SiGe film will be useful to fabricate Si nanowires and nanosheets using SiGe as the sacrificial layer.

Full text open source: LINK


Figure from Journal of Vacuum Science & Technology A 39, 022602 (2021); https://doi.org/10.1116/6.0000834

Wednesday, February 3, 2021

LIVE Stream - Advanced Process Technologies to Enable Future Devices and Scaling (invited), Rob Clark Tokyo Electron

SEMICON Korea SEMI Technology Symposium (STS) 2021 - The invited presentation titled "Advanced Process Technologies to Enable Future Devices and Scaling" can be streamed starting Feb. 3 in S. Korea (2/2 evening U.S.). 

This is an overview of new processing technologies required for continued scaling of leading-edge and emerging semiconductor devices. The main drivers and trends affecting future semiconductor device scaling are introduced to explain how these factors are influencing and driving process technology development. Topics explored in this presentation include atomic layer deposition (ALD), atomic layer etching (ALE), selective deposition and etching. In order to enable self-aligned and multiple patterning schemes as well as emerging devices for future manufacturing, atomic level process technologies need to be leveraged holistically. Real-world examples of current and future integration schemes, as well as emerging devices, will be presented and explained so that attendees can understand how advanced process technologies will be used in future device manufacturing as well as what benefits and tradeoffs may be encountered in their use.




Thursday, January 21, 2021

Master Thesis in Nanotechnology with Alixlabs in Sweden on Atomic Level Fragmentation

Come and join us in Lund Sweden for an exciting Master Thesis in Atomic Level Fragmentation - the new option for extending optical lithography cheaper, greener, and faster than any advanced multi-patterning scheme!

Operating within Lind Nano Lab we guarantee a safe & flexible workplace under ISO 5 and ISO 7 Cleanroom conditions, 24/7 operation, and remote working from wherever you need to be when outside the cleanroom.


Lund Nano Lab : LINK

Thesis description and application : LINK


View across The Science City of Lund in South Sweden direction Copenhagen in Denmark across the straight of Öresend connected by the longest bridge in Europe.


Thursday, December 17, 2020

Imec introduces 2D materials in the logic device scaling roadmap

[IEDM 2020 Virtual, Imec Belgium LINK] At the 2020 IEDM conference, imec proposes that 2D semiconductors like tungsten disulfide (WS2) can further extend the logic transistor scaling roadmap. The team laid the groundwork for integrating 2D semiconductors in a 300mm CMOS fab, and worked towards improved device performance. These findings are presented in four IEDM papers, one of which was selected as IEDM highlight.

More details can be found in 4 papers presented at the 2020 IEDM conference:

[1] ‘Introducing 2D-FETs in device scaling roadmap using DTCO’, Z. Ahmed et al.
[2] ‘Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab’, I. Asselberghs et al.
[3] ‘Dual gate synthetic WS2 MOSFETs with 120µS/µm Gm 2.7µF/cm2 capacitance and ambipolar channel’, D. Lin et al.
[4] ‘Sources of variability in scaled MoS2 FETs’, Q. Smets et al. (IEDM highlight paper)

TEM image of a 2D device fabricated with 300mm processes. (Source: Imec)


Thursday, November 19, 2020

Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling at IEDM 2020

Intel to present stacked gate-all-around FET (GAA-FET) technology, i.e., a complementary FET (CFET) at IEDM2020. In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires. This ‘folding’ of the nFET and pFET eliminates the n-to-p separation bottleneck, reducing the cell active area footprint (LINK). Please find the announcement below:

Home-2020 - IEDM 2020 ieee-iedm.org IEDM Conference 2020. To Be Held Virtually December 12-18. The on demand portion of the conference will begin on December 5th. Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling: 

Stacked NMOS-on-PMOS Nanoribbons: From planar MOSFETs, to FinFETs, to gate-all-around (GAA) or nanoribbon devices, novel transistor architectures have played a critical role in driving performance predicted by Moore’s Law. Intel researchers will describe what may be the next step in that evolution: NMOS-on-PMOS transistors built from multiple self-aligned stacked nanoribbons. This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons. The approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (<30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking. These devices were used to build a functional CMOS inverter with well-balanced voltage transfer characteristics. (Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” C.-Y. Huang et al, Intel) 

Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling,” C.-Y. Huang et al, Intel

Paper Information (IEDM 2020) : LINK

Figures from IEDM 2020 Press briefing Material -Press kit : LINK

In the images above:

·        (1) shows the evolution of transistor architectures from planar, to FinFETs, to nanoribbons and to a 3D CMOS architecture.

·        (2) (a) shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (Vss) and outer (Vcc) contacts, a common gate input (VIN) and an inverter output node (VOUT); while (d) is a TEM image of two Si NMOS nanoribbons atop 3 Si PMOS nanoribbons.

·       (3) (a) is a process flow of the vertically stacked dual S/D EPI process, while (b) shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI selectively grown on the top two nanoribbons, and (d) features TEM and EDS images showing selective N-EPI and P-EPI growth on the stacked nanoribbon transistors.

·       (4) (a) is a process flow of the vertically stacked dual metal gate process; (b) is a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM = work function metal) on the top two nanoribbons and P-WFM on the bottom three nanoribbons.



Thursday, April 2, 2020

TSMC hit by 3nm delay fears over Covid-19 Lock-downs

TSMC is on schedule with its 5 nm process plan, but its 3 nm trial production may get delayed: The world's largest contract chipmaker is planning to launch mass production of its 3 nm process sometime in 2022, and media reported Monday that installation of production equipment in its 3 nm wafer fab in Tainan will be delayed to October from June this year, which will delay its trial production set for 2021. The COVID-19 escalation has hit Europe, and [Netherlands-based] ASML Holding, which is TSMC's major production equipment supplier, has been affected by a lockdown. It is understandable that the progress of TSMC's new technology has been affected.

Below a comparison of the Covid-19 daily new confirmed deaths, which is the only comparable parameter to use due to different testing capabilities and frequencies, in time and nation to nation. As can be seen the situation in Asian is under control after the gotten hit by the first wave of the Coronavirus. The European situation is stabilizing: Italy, Netherlands, Germany France, others look similar and are flattening the curve. In The USA situation is escalating. Many nations in Europe are forecasting a lift of Lockdown in May but are very careful, as an example Germany will decide in 19 April how to proceed according to Chancellor Dr. Angela Merkel.

BALD Engineering AB continues to monitor the Covid-19 situation due to lockdowns that affect the  the semiconductor industry – Stay Safe!

Google Finance (2020-04-02, 10:39 CET)

Sources:

Taiwan shares edge lower, TSMC hit by 3nm delay fears

Our World of data: https://ourworldindata.org/coronavirus

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By Abhishekkumar Thakur, Jonas Sundqvist

Friday, January 24, 2020

Russian researchers obtain atomically thin molybdenum disulfide (2D) films on large-area substrates by ALD

[Press release: LINK] Researchers from the Moscow Institute of Physics and Technology have managed to grow atomically thin films of molybdenum disulfide spanning up to several tens of square centimeters. It was demonstrated that the material’s structure can be modified by varying the synthesis temperature. The films, which are of interest to electronics and optoelectronics, were obtained at 900-1,000 degrees Celsius. The findings were published in the journal ACS Applied Nano Materials.



An atomic layer deposition reactor from Picosun used for obtaining ultrathin molybdenum oxide films, which were subsequently sulfurized to 2D molybdenum disulfide. Image courtesy of the Atomic Layer Deposition Lab, MIPT

Two-dimensional materials are attracting considerable interest due to their unique properties stemming from their structure and quantum mechanical restrictions. The family of 2D materials includes metals, semimetals, semiconductors, and insulators. Graphene, which is perhaps the most famous 2D material, is a monolayer of carbon atoms. It has the highest charge-carrier mobility recorded to date. However, graphene has no band gap under standard conditions, and that limits its applications.



Saturday, December 14, 2019

IEDM 2019 News - Intel roadmap to 1.4 nm by 2029

Limitless - Intel disclosed its extended roadmap to 1.4 nm process node by 2029 including back porting: One of the interesting disclosures at the IEEE International Electron Devices Meeting (IEDM) was that Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7 nm EUV in 2021, then 5 nm in 2023, 3 nm in 2025, 2 nm in 2027, and 1.4 nm in 2029. 
 
In between each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. The interesting element is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older ‘++’ version of a process node in the same timeframe.

 
Intel's slide with ASML's animations overlayed, as shown in the slide deck distributed by ASML. Note by Anandtech: "After some emailing back and forth, we can confirm that the slide that Intel's partner ASML presented at the IEDM conference is actually an altered version of what Intel presented for the September 2019 source. ASML added animations to the slide such that the bottom row of dates correspond to specific nodes, however at the time we didn't spot these animations (neither did it seem did the rest of the press). It should be noted that the correlation that ASML made to exact node names isn't so much a stretch of the imagination to piece together, however it has been requested that we also add the original Intel slide to provide context to what Intel is saying compared to what was presented by ASML. Some of the wording in the article has changed to reflect this. Our analysis is still relevant." Please see the full article in Anandtech for all the details: LINK
 
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By Abhishekkumar Thakur

Wednesday, December 11, 2019

Imec shows excellent performance in ultra-scaled FETs with 2D-material channel

[Press release, imec, LINK] SAN FRANCISCO (USA), December 8, 2019 — At this year’s IEEE International Electron Devices Meeting (Dec 7-11 2019), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, reports an in-depth study of scaled transistors with MoS2 and demonstrates best device performance to date for such materials. 

TEM pictures showing (a) 3 monolayers MoS2 channel, with contact length 13nm and channel length 29nm Transfer characteristics have improved sub-threshold swing (SS) with thinner HfO2. (www.imec.be)

MoS2 is a 2D material, meaning that it can be grown in stable form with nearly atomic thickness and atomic precision. Imec synthesized the material down to monolayer (0.6nm thickness) and fabricated devices with scaled contact and channel length, as small as 13nm and 30nm respectively. These very scaled dimensions, combined with scaled gate oxide thickness and high K dielectric, have enabled the demonstration of some of the best device performances so far. Most importantly, these transistors enable a comprehensive study of fundamental device properties and calibration of TCAD models. The calibrated TCAD model is used to propose a realistic path for performance improvement. The results presented here confirm the potential of 2D-materials for extreme transistor scaling – benefiting both high-performance logic and memory applications.

Saturday, November 23, 2019

Imec updates semiconductor miniaturization roadmap to 1nm-ITF Japan 2019

Imec held an annual research result presentation event “imec Technology Forum Japan 2019 (ITF Japan 2019)” in Tokyo on October 11.




This is what we are to expect coming next for Logic scaling: Nanosheet transistors (Gate All Around transistors), Buried Power Rails, Ruthenium incorporation, Forksheet transistor architecture, CFET (complementary FET by 3D stacking of nanosheet PFET and NFET), deployment of 2D materials, spintronics, and quantum computing as the way to continued chip scaling for keeping a modified Moore's Law alive.
Source: LINK

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By Abhishekkumar Thakur