Bottom-up PEALD of SiO2 by growth inhibition for seamless gap-fill process

Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process

Yoenju Choi, Taehoon Kim, Hangyul Lee, Jusung Park, Juhwan Park, Dongho Ryu & Woojin Jeon

Scientific Reports volume 12, Article number: 15756 (2022)

The design-rule shrinkage in semiconductor devices is a challenge at every step of the integration process. In the gap-fill process for isolation, the seam and void formation cannot be suppressed by using a deposition process, which even has excellent step coverage. To achieve seamless gap fill in the high-aspect-ratio structure, which has a non-ideal etch profile such as a negative slope, the deposition process should be able to realize the “bottom-up growth” behavior. In this work, the bottom-up growth of a SiO2 plasma-enhanced atomic layer deposition (PE-ALD) process in a trench structure was investigated by using a growth inhibition process employing plasma treatment. N2 and NH3 plasma pre-treatments were employed to suppress the growth of the SiO2 PE-ALD process without any contamination, and the inhibition mechanism was investigated by performing surface chemistry analyses using X-ray photoelectron spectroscopy. Furthermore, the gap-fill characteristics of the SiO2 PE-ALD process were examined, depending on the process conditions of NH3 plasma pre-treatment, by performing cross-sectional field emission scanning electron microscopy measurements. Finally, a seamless gap-fill process in a high-aspect-ratio trench pattern was achieved by the bottom-up growth behavior of SiO2 PE-ALD using NH3 plasma pre-treatment.

From: Bottom-up plasma-enhanced atomic layer deposition of SiO2 by utilizing growth inhibition using NH3 plasma pre-treatment for seamless gap-fill process

Webinar - Decadal Plan for Semiconductors: New Compute Trajectories for Energy Efficiency

SIA/SRC [LINK]: Computing and, more generally, Information and Communication Technologies (ICT) is the social-economic growth engine of the modern world. Rapid advances in computing have provided increased performance and enhanced features in each new generation of products in nearly every market segment, whether it be servers, PCs, communications, mobile, automotive, or entertainment, among others.

The use of information and communication technologies continues to grow without bounds dominated by the exponential creation of data that must be moved, stored, computed, communicated, secured and converted to end user information. Ever-rising energy demands for computing versus global energy production are creating new risk, therefore new computing paradigms need to be discovered that would result in dramatically improved energy efficiency of computing.

This webinar intends to identify a compelling research agenda based on the Decadal Plan for Semiconductors, led by SRC to discover new approaches to computing with a focus on changing the current mainstream compute trajectory. The underlying technical challenge is bit-utilization efficiency in computation.

The US Patent Office has approved AlixLabs’ patent application for nanofabrication by ALE Pitch Splitting (APS)

(30 April 2021, Lund Sweden). The US Patent Office has approved AlixLabs’ (AlixLabs AB) patent application for nanofabrication by ALE Pitch Splitting (APS).

The US Patent Office has issued a patent (US10930515) on February 23, 2021. The patent covers methods to split nanostructures in half by a single process step using Atomic Layer Etching (ALE). The method has the potential to have a big impact on the semiconductor industry by enabling sustainable scaling of electronic components and shrink chip designs further in a cost-effective way. The method is complementary for single exposure Immersion and Extreme UV (EUV) Lithography and corresponding multiple patterning technologies like self-aligned double and quadruple patterning (SADP resp. SAQP) as well as directed self-assembly (DSA).

In direct comparison to mentioned more complicated and expensive methods, APS may cut the need for certain fab equipment investments considerably, reduce manufacturing cost and energy consumption as well as reduce greenhouse gas emission during the patterning processing by up to 50%, allowing greener and affordable way forward for the semiconductor industry.

AlixLabs aims at applications for the manufacturing of leading-edge sub 5nm Logic Devices and Memory Chips that are used for everyday consumer electronic devices, 5G and AI.

The company’s CEO Dr. Jonas Sundqvist comments:

After founding the company in 2019 we now move into very exciting times. The team has been expanded with Dr. Mohammad Karimi as Principal Scientist and we have several applications and projects in the pipeline for broadening our patent protection and creating further opportunities for commercial agreements starting now. Currently, we are taking on the first round of private investments and will expand operations for both core activities in Lund, Sweden, at NanoLund and Lund Nano Lab, and the IDEON Science Park in Sweden. In addition, we are heading to the heart of the European semiconductor industry in Dresden Germany for a lab to fab transfer to 300 mm silicon wafer process verification to get ready for customer demonstrations of APS.

The company’s CTO Dr. Dmitry Suyatin comments:

This patent is built on a surprising discovery by the inventors, which took place at Lund Nano Lab during the Master project by Dr. Sabbir A. Khan who has recently received his PhD from the University of Copenhagen and now continues his postdoctoral work at Niels Bohr Institute in Copenhagen.

About AlixLabs AB:

AlixLabs (www.alixlabs.com) is an innovative startup enabling the semiconductor industry to scale down Logic and Memory components in a cost-effective manner by the use of ALE Pitch Splitting (APS).

Background Information:

Lund Nano Lab: https://www.nano.lu.se/facilities/lund-nano-lab

IDEON Science Park: https://www.ideoninnovation.se/our-startups

Picture:

Thermal ALE of germanium rich SiGe by CU Boulder and ASM Microchemistry

Epitaxially grown SiGe is an important material for CMOS Logic. It is integrated as the channel material and by inserting a higher concentration of germanium the mobility of the transistor can be improved. The industry calls it Epi, but what is really referred to a thermal CVD process producing an epitaxially grown layer of silicon or silicon-germanium onto a single crystalline silicon wafer.

As CMOS scaling has progressed the IDMs and Foundries have moved from the planar field-effect transistor (FET) architecture to a narrow fin-based transition the FinFET. The next evolutionary step on the horizon will be the transition to a nanowire-based architecture forming a gate-all-around FET (GAA-FET). At some point in time beyond the 2 nm node, the lateral scaling possibility will hit a wall and it is foreseen that the CMOS scaling will gup upwards like other technologies in order to cram in more devices per unit area. In a first approach, it may be that the NMOS and PMOS transistors are rearranged from being processed next to each other to put one of them on top of the other. Intel recently presented this at IEDM2020 (LINK). Having done that you can foresee continuing on a vertical scaling path also for CMOS just like 3DNAND and start to build those skyscrapers.

When going vertical, you will need highly conformal deposition processes as provided by ALD and in high volume production since the event of 90 nm DRAM (Samsung) and 45 nm Logic (Intel), however, etch is a problem since the reactive ion etching process are typically directional with the plasma under low-pressure processing conditions used. Also, the Argon plasma ALE processes to etch Silicon, silicon Germanin gallium nitride, and III/V materials are directional or anisotropic as the etch guys say or non-conformal as we ALD people say.

Typically the best way to achieve isotropic etch conditions, meaning you remove material at the same rate or as for ALE the same amount per cycle (etch per cycle EPC), is to skip the plasma that causes the anisotropic etch. Here Dr Abdulgatov and co-workers in the famous SM George Lab, CU Boulder together with Varun Sharma and friends from ASM Microchemistry, one of Dresden's best shining ALD-Stars, publish a paper on Thermal ALE of germanium rich SiGe that is quite clever. Here using PVD Si0.15Ge0.85 samples, which are difficult to make by Epi due to the high Ge content. I think we will see more of this for also GaN, SiC and III/V materials coming up.

Thermal atomic layer etching of germanium-rich SiGe using an oxidation and “conversion-etch” mechanism

AI Abdulagatov, V Sharma, JA Murdzek, AS Cavanagh, SM George

Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films

Abstract: The thermal atomic layer etching (ALE) of germanium-rich SiGe was demonstrated using an oxidation and “conversion-etch” mechanism with oxygen (O2) or ozone (O3), hydrofluoric acid (HF), and trimethylaluminum [TMA, Al(CH3)3] as the reactants. The crystalline germanium-rich SiGe film was prepared using physical vapor deposition and had a composition of Si0.15Ge0.85. In situ spectroscopic ellipsometry was employed to monitor the thickness of both the SiGe film and the surface oxide layer on the SiGe film during thermal ALE. Using a reactant sequence of O2-HF-TMA, the etch rate of the SiGe film increased progressively with temperatures from 225 to 290 °C. At 290 °C, the SiGe film thickness decreased linearly at a rate of 0.57 Å/cycle with a surface oxide thickness of 18–19 Å. This etch rate was obtained using reactant pressures of 25, 0.2, and 0.4 Torr and doses of 1.5, 1.0, and 1.0 s for O2, HF, and TMA, respectively. The TMA and HF reactions were self-limiting and the O2 reaction was reasonably self-limiting at 290 °C. Using an O3-HF-TMA reaction sequence, the SiGe ALE etch rate was 0.42 Å/cycle at 290 °C. This etch rate was obtained using reactant pressures of 15, 0.2, and 0.4 Torr and dose times of 0.5, 1.0, and 1.0 s for O3, HF, and TMA, respectively. The O3, TMA, and HF reactions were all self-limiting at 290 °C. Atomic force microscopy images revealed that thermal ALE with the O2-HF-TMA or O3-HF-TMA reaction sequences did not roughen the surface of the SiGe film. The SiGe film was etched selectively compared with Si or Si3N4 at 290 °C using an O2-HF-TMA reaction sequence. The etch rate for the SiGe film was >10 times faster than Si(100) or Si3N4 that was prepared using low-pressure chemical vapor deposition. This selectivity for the SiGe film will be useful to fabricate Si nanowires and nanosheets using SiGe as the sacrificial layer.

Full text open source: LINK

Figure from Journal of Vacuum Science & Technology A 39, 022602 (2021); https://doi.org/10.1116/6.0000834

LIVE Stream - Advanced Process Technologies to Enable Future Devices and Scaling (invited), Rob Clark Tokyo Electron

SEMICON Korea SEMI Technology Symposium (STS) 2021 - The invited presentation titled "Advanced Process Technologies to Enable Future Devices and Scaling" can be streamed starting Feb. 3 in S. Korea (2/2 evening U.S.). 

This is an overview of new processing technologies required for continued scaling of leading-edge and emerging semiconductor devices. The main drivers and trends affecting future semiconductor device scaling are introduced to explain how these factors are influencing and driving process technology development. Topics explored in this presentation include atomic layer deposition (ALD), atomic layer etching (ALE), selective deposition and etching. In order to enable self-aligned and multiple patterning schemes as well as emerging devices for future manufacturing, atomic level process technologies need to be leveraged holistically. Real-world examples of current and future integration schemes, as well as emerging devices, will be presented and explained so that attendees can understand how advanced process technologies will be used in future device manufacturing as well as what benefits and tradeoffs may be encountered in their use.

LINK: https://www.semiconkorea.org/ko/node/3701

Master Thesis in Nanotechnology with Alixlabs in Sweden on Atomic Level Fragmentation

Come and join us in Lund Sweden for an exciting Master Thesis in Atomic Level Fragmentation - the new option for extending optical lithography cheaper, greener, and faster than any advanced multi-patterning scheme!

Operating within Lind Nano Lab we guarantee a safe & flexible workplace under ISO 5 and ISO 7 Cleanroom conditions, 24/7 operation, and remote working from wherever you need to be when outside the cleanroom.

Lund Nano Lab : LINK

Thesis description and application : LINK

View across The Science City of Lund in South Sweden direction Copenhagen in Denmark across the straight of Öresend connected by the longest bridge in Europe.

Imec introduces 2D materials in the logic device scaling roadmap

[IEDM 2020 Virtual, Imec Belgium LINK] At the 2020 IEDM conference, imec proposes that 2D semiconductors like tungsten disulfide (WS2) can further extend the logic transistor scaling roadmap. The team laid the groundwork for integrating 2D semiconductors in a 300mm CMOS fab, and worked towards improved device performance. These findings are presented in four IEDM papers, one of which was selected as IEDM highlight.

More details can be found in 4 papers presented at the 2020 IEDM conference:

[1] ‘Introducing 2D-FETs in device scaling roadmap using DTCO’, Z. Ahmed et al.
[2] ‘Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab’, I. Asselberghs et al.
[3] ‘Dual gate synthetic WS2 MOSFETs with 120µS/µm Gm 2.7µF/cm2 capacitance and ambipolar channel’, D. Lin et al.
[4] ‘Sources of variability in scaled MoS2 FETs’, Q. Smets et al. (IEDM highlight paper)

TEM image of a 2D device fabricated with 300mm processes. (Source: Imec)

Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling at IEDM 2020

Intel to present stacked gate-all-around FET (GAA-FET) technology, i.e., a complementary FET (CFET) at IEDM2020. In CFETs, the idea is to stack both nFET and pFET wires on each other. A CFET could stack one nFET on top of a pFET wire, or two nFETs on top of two pFET wires. This ‘folding’ of the nFET and pFET eliminates the n-to-p separation bottleneck, reducing the cell active area footprint (LINK). Please find the announcement below:

Home-2020 - IEDM 2020 ieee-iedm.org IEDM Conference 2020. To Be Held Virtually December 12-18. The on demand portion of the conference will begin on December 5th. Intel to present 3D stacked Nanoribbon Transistors for Continued Moore’s Law Scaling: 

Stacked NMOS-on-PMOS Nanoribbons: From planar MOSFETs, to FinFETs, to gate-all-around (GAA) or nanoribbon devices, novel transistor architectures have played a critical role in driving performance predicted by Moore’s Law. Intel researchers will describe what may be the next step in that evolution: NMOS-on-PMOS transistors built from multiple self-aligned stacked nanoribbons. This architecture employs a vertically stacked dual source/drain epitaxial process and a dual metal gate fabrication process, enabling different conductive types of nanoribbons to be built so that threshold voltage adjustments can be made for both top and bottom nanoribbons. The approach combines excellent electrostatics (subthreshold slope of <75 mV/dec) and DIBL (<30mV/V for gates ≥30nm) with a path to significant cell size reduction due to the self-aligned stacking. These devices were used to build a functional CMOS inverter with well-balanced voltage transfer characteristics. (Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore’s Law Scaling,” C.-Y. Huang et al, Intel) 

Paper #20.6, “3-D Self-Aligned Stacked NMOS-on-PMOS Nanoribbon Transistors for Continued Moore's Law Scaling,” C.-Y. Huang et al, Intel

Paper Information (IEDM 2020) : LINK

Figures from IEDM 2020 Press briefing Material -Press kit : LINK

In the images above:

·        (1) shows the evolution of transistor architectures from planar, to FinFETs, to nanoribbons and to a 3D CMOS architecture.

·        (2) (a) shows a 3D schematic diagram of stacked CMOS Si nanoribbon transistors with NMOS on PMOS, (b) describes the process flow; (c) is a TEM image of a stacked multiple-nanoribbon CMOS inverter with a 40-nm gate length and inner (V_ss) and outer (V_cc) contacts, a common gate input (V_IN) and an inverter output node (V_OUT); while (d) is a TEM image of two Si NMOS nanoribbons atop 3 Si PMOS nanoribbons.

·       (3) (a) is a process flow of the vertically stacked dual S/D EPI process, while (b) shows P-EPI selectively grown on the bottom three nanoribbons, (c) shows N-EPI selectively grown on the top two nanoribbons, and (d) features TEM and EDS images showing selective N-EPI and P-EPI growth on the stacked nanoribbon transistors.

·       (4) (a) is a process flow of the vertically stacked dual metal gate process; (b) is a TEM image and (c, d) are EDS images of the dual metal gate with N-WFM (WFM = work function metal) on the top two nanoribbons and P-WFM on the bottom three nanoribbons.

TSMC hit by 3nm delay fears over Covid-19 Lock-downs

TSMC is on schedule with its 5 nm process plan, but its 3 nm trial production may get delayed: The world's largest contract chipmaker is planning to launch mass production of its 3 nm process sometime in 2022, and media reported Monday that installation of production equipment in its 3 nm wafer fab in Tainan will be delayed to October from June this year, which will delay its trial production set for 2021. The COVID-19 escalation has hit Europe, and [Netherlands-based] ASML Holding, which is TSMC's major production equipment supplier, has been affected by a lockdown. It is understandable that the progress of TSMC's new technology has been affected.

Below a comparison of the Covid-19 daily new confirmed deaths, which is the only comparable parameter to use due to different testing capabilities and frequencies, in time and nation to nation. As can be seen the situation in Asian is under control after the gotten hit by the first wave of the Coronavirus. The European situation is stabilizing: Italy, Netherlands, Germany France, others look similar and are flattening the curve. In The USA situation is escalating. Many nations in Europe are forecasting a lift of Lockdown in May but are very careful, as an example Germany will decide in 19 April how to proceed according to Chancellor Dr. Angela Merkel.

BALD Engineering AB continues to monitor the Covid-19 situation due to lockdowns that affect the  the semiconductor industry – Stay Safe!

Google Finance (2020-04-02, 10:39 CET)

Sources:

Taiwan shares edge lower, TSMC hit by 3nm delay fears

https://focustaiwan.tw/business/202003300015

Our World of data: https://ourworldindata.org/coronavirus

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By Abhishekkumar Thakur, Jonas Sundqvist

Russian researchers obtain atomically thin molybdenum disulfide (2D) films on large-area substrates by ALD

[Press release: LINK] Researchers from the Moscow Institute of Physics and Technology have managed to grow atomically thin films of molybdenum disulfide spanning up to several tens of square centimeters. It was demonstrated that the material’s structure can be modified by varying the synthesis temperature. The films, which are of interest to electronics and optoelectronics, were obtained at 900-1,000 degrees Celsius. The findings were published in the journal ACS Applied Nano Materials.

An atomic layer deposition reactor from Picosun used for obtaining ultrathin molybdenum oxide films, which were subsequently sulfurized to 2D molybdenum disulfide. Image courtesy of the Atomic Layer Deposition Lab, MIPT

Two-dimensional materials are attracting considerable interest due to their unique properties stemming from their structure and quantum mechanical restrictions. The family of 2D materials includes metals, semimetals, semiconductors, and insulators. Graphene, which is perhaps the most famous 2D material, is a monolayer of carbon atoms. It has the highest charge-carrier mobility recorded to date. However, graphene has no band gap under standard conditions, and that limits its applications.

IEDM 2019 News - Intel roadmap to 1.4 nm by 2029

Limitless - Intel disclosed its extended roadmap to 1.4 nm process node by 2029 including back porting: One of the interesting disclosures at the IEEE International Electron Devices Meeting (IEDM) was that Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7 nm EUV in 2021, then 5 nm in 2023, 3 nm in 2025, 2 nm in 2027, and 1.4 nm in 2029. 

 

In between each process node, as Intel has stated before, there will be iterative + and ++ versions of each in order to extract performance from each process node. The only exception to this is 10nm, which is already on 10+, so we will see 10++ and 10+++ in 2020 and 2021 respectively. The interesting element is the mention of back porting. This is the ability for a chip to be designed with one process node in mind, but perhaps due to delays, can be remade on an older ‘++’ version of a process node in the same timeframe.

 

Intel's slide with ASML's animations overlayed, as shown in the slide deck distributed by ASML. Note by Anandtech: "After some emailing back and forth, we can confirm that the slide that Intel's partner ASML presented at the IEDM conference is actually an altered version of what Intel presented for the September 2019 source. ASML added animations to the slide such that the bottom row of dates correspond to specific nodes, however at the time we didn't spot these animations (neither did it seem did the rest of the press). It should be noted that the correlation that ASML made to exact node names isn't so much a stretch of the imagination to piece together, however it has been requested that we also add the original Intel slide to provide context to what Intel is saying compared to what was presented by ASML. Some of the wording in the article has changed to reflect this. Our analysis is still relevant." Please see the full article in Anandtech for all the details: LINK

 

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By Abhishekkumar Thakur

Imec shows excellent performance in ultra-scaled FETs with 2D-material channel

[Press release, imec, LINK] SAN FRANCISCO (USA), December 8, 2019 — At this year’s IEEE International Electron Devices Meeting (Dec 7-11 2019), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, reports an in-depth study of scaled transistors with MoS2 and demonstrates best device performance to date for such materials. 

TEM pictures showing (a) 3 monolayers MoS2 channel, with contact length 13nm and channel length 29nm Transfer characteristics have improved sub-threshold swing (SS) with thinner HfO2. (www.imec.be)

MoS2 is a 2D material, meaning that it can be grown in stable form with nearly atomic thickness and atomic precision. Imec synthesized the material down to monolayer (0.6nm thickness) and fabricated devices with scaled contact and channel length, as small as 13nm and 30nm respectively. These very scaled dimensions, combined with scaled gate oxide thickness and high K dielectric, have enabled the demonstration of some of the best device performances so far. Most importantly, these transistors enable a comprehensive study of fundamental device properties and calibration of TCAD models. The calibrated TCAD model is used to propose a realistic path for performance improvement. The results presented here confirm the potential of 2D-materials for extreme transistor scaling – benefiting both high-performance logic and memory applications.

Imec updates semiconductor miniaturization roadmap to 1nm-ITF Japan 2019

Imec held an annual research result presentation event “imec Technology Forum Japan 2019 (ITF Japan 2019)” in Tokyo on October 11.

This is what we are to expect coming next for Logic scaling: Nanosheet transistors (Gate All Around transistors), Buried Power Rails, Ruthenium incorporation, Forksheet transistor architecture, CFET (complementary FET by 3D stacking of nanosheet PFET and NFET), deployment of 2D materials, spintronics, and quantum computing as the way to continued chip scaling for keeping a modified Moore's Law alive.

Source: LINK

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By Abhishekkumar Thakur

Lund University Holding invests in newly started AlixLabs

LU Holding invests in newly started AlixLabs, which have developed a method to manufacture electronic circuits for the semiconductor industry in a very cost-effective way.

[Published on September 27, 2019: Original in Swedish: LINK]

Researchers from NanoLund have developed and patented the method and all three, Jonas Sundqvist, Dmitry Suyatin, and Sabbir Kahn, are part of the newly started company (AlixLabs AB), and Co-founder Stefan Svedberg joins as CEO. Svedberg was previously Director of Corporate Development at Ericsson.

Displaying the Edge Effect: This is a new method of nanostructure fabrication using the atomic layer etching process, which is inherently a damage-free etch process. The recently discovered etching process selectivity to inclined surfaces, can be used as a mask and in this way walls of tapered structures. The inclined surfaces can be readily fabricated by e.g. dry etching or epitaxial growth, and will provide masking during the atomic layer etching process. This process therefore provides access to fabrication of extremely small structures in a very precise and efficient way.

Electronic circuits are needed in all types of hardware, but the cost of producing them has increased as the electronics become smaller. With the AlixLab method, which is based on a recently identified physical phenomenon, the manufacturing process of the electronic circuits becomes both faster and significantly cheaper.

Dr. Dmitry Suyatin, Co-founder and CTO and Dr. Jonas Sundqvist, Co-founder and Senior Technical Adviser at AlixLabs inspecting the new Atomic Layer Etching Equipment at Lund Nano Lab from PlasmaTherm.
 

"AlixLabs has an exciting technology, and now we have a good team in place," says Erik Larsson, portfolio manager at LU Holding.

Alixlabs plans to implement an expanded proof of concept in 2020 as the basis for continued customer discussions.

AlixLabs Team : LINK

Moore's Law graphed vs real CPUs & GPUs 1965 - 2019

(Youtube: https://www.youtube.com/watch?v=7uvUiq_jTLM) Moore's Law has been ridiculously accurate for more than 50 years - how long will it hold up? See in this visualization how the actual transistors in CPUs and GPUs compare to the linear progression of Moore's Law. From the early days of microprocessors, to Intel dominance and the rise of GPUs. 

 

Music: Dizaro - Aurora Borealis https://theartistunion.com/dizarofr 

Data sources: Too many to list here, see wikipedia article: https://en.wikipedia.org/w/index.php?... for Moore's Law, I took a starting point of 8000 in 1975, and worked my way forward and backward from there.

Intel at EECS Colloquium "Moore’s Law Is Not Dead"

Intel’s Jim Keller: “We’re all building nanowires… Intel, TSMC, Samsung” Keller in his "Moore’s Law Is Not Dead" talk at UC Berkeley this week said, “We had planar transistors, we went to FinFET. We’re all building nanowires in the fab. Intel, TSMC, Samsung, everybody’s working on it. There’s a really interesting thing. While the world thinks Moore’s Law’s dead, the fabs and the technologists think it’s not and everybody’s announced now a 10-year roadmap for Moore’s Law.” 

The UC Berkeley EECS Events team has live streamed the entire talk over on YouTube and you can catch up on this fascinating, intimate little talk (below).

 

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By Abhishekkumar Thakur

Intel 2019 Investor Meeting: 7 nm Product in 2021

Intel held its 2019 investor meeting May 8, 2019 (LINK), it's first since 2017, and CEO Bob Swan announced that Intel would launch its 7 nm process in 2021 to challenge TSMC's 5 nm products.

Intel's Xe graphics will be the leading 7 nm product, which will come on the heels of Intel's first discrete 10 nm GPU that arrives in 2020. The company also unveiled its first block diagram of the Ice Lake architecture and announced that its new 10nm Tiger Lake processors will come to market in 2020.

Source: Tom´s Hardware LINK

 (intel.com)

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By Abhishekkumar Thakur

4th CMC Conference Enabled Critical Information and Connections

Fab materials event in Albany, New York area April 25-26 featured GlobalFoundries keynote and Intel and TI presentations. Plan now for the 2020 April 23-24 event in Hillsboro, Oregon. 

(SAN DIEGO (PRWEB) May 07, 2019) Over 150 leading executives and managers within the semiconductor manufacturing ecosystem gathered on April 25th and 26th in the Albany area of New York state for an important event on fabrication (fab) materials. The fourth-annual Critical Materials Council (CMC) Conference, produced by TECHCET, included topical presentations, a fab tour, exhibits by specialty materials suppliers, and networking roundtable discussions to learn about best-practices in a pre-competitive environment. Folks who missed attending the event this year can register to access the posted presentations for a nominal fee at https://cmcfabs.org/cmc-conference-2019/.

The event opened again, as in each of the prior three years, on an extremely strong business and technology keynote address by an executive from one of the CMC Fab member companies. The 2019 CMC Conference keynote was given by Dr. John Pellerin, Deputy CTO and VP of Worldwide R&D, GlobalFoundries. Pellerin talked about how demand for new high-volume manufacturing (HVM) semiconductor devices over the next few years will drive needs for increased numbers of new specialty materials as well as volumes of existing materials in his presentation on "Materials Challenges & Opportunities in Differentiated Technologies."

In the first session of the event covering global supply-chain issues of economics and regulations, G. Dan Hutcheson, CEO of VLSI Research, presented on "Slowdown: When did it start? What drove it? And When will the recovery come?" Hutcheson showed data from leading economic indicators that the recent decline in global semiconductor fab industry revenues due to memory chip prices may have already turned around.

TECHCET Sr. Analysts Dr. Jonas Sundqvist and Terry Francis presented updated information on demand drivers and forecasts for ALD/CVD precursors and Rare Earths, respectively. Sundqvist--also leader of the Thin Film Technologies Group at Fraunhofer IKTS--focused on how new 3D memory and logic chips demand more deposition precursors such that chemical volume growth will outpace that of silicon wafers, shown in the Figure. Francis showed how "Rare Earth" elements are not so rare at the elemental level, but complex dynamics between mining and refining and capitalism have led to a situation where mainland China currently controls most of the market for elements such as lanthanum (used in advanced ICs to create CMOS logic gates). Deep dives into all such materials matters are found in the TECHCET Critical Materials Reports (CMR), and you can find all of them online at https://techcet.com/shop/. 

Global semiconductor silicon quarterly wafer shipments 2015-2019 in millions of square inches (MSI). (Source: TECHCET)

The 2020 spring CMC Conference is scheduled for April 24-25 in Hillsboro, Oregon. The CMC Fab members and Associate members will again gather for two days of private face-to-face meetings before attending the public CMC Conference.

In addition to the annual spring CMC Conference in the US, there is also an annual fall CMC Seminar in Asia. The 2019 CMC Seminar will be held on October 17 in Taoyuan, Taiwan. For more information on CMC events see https://techcet.com/cmc-events/.

About CMC:
The Critical Materials Council (CMC) of Semiconductor Fabricators (CMCFabs.org) is a membership-based organization that works to anticipate and solve critical materials issues in a pre-competitive environment. The CMC is a business unit of TECHCET, and includes materials supplier Associate Members.

About TECHCET:
TECHCET CA LLC is an advisory services firm focused on process materials supply-chains, electronic materials business, and materials market analysis for the semiconductor, display, solar/PV, and LED industries. Since 2000, the company has been responsible for producing the SEMATECH Critical Material Reports™, covering silicon wafers, semiconductor gases, wet chemicals, CMP consumables, Photoresists, and ALD/CVD Precursors. For additional information about reports, market briefings, CMC membership, or custom consulting please contact info(at)cmcfabs(dot)org, +1-480-332-8336, or go to http://www.techcet.com or http://www.cmcfabs.org.

Samsung’s GAA Transistor, MBCFET™ aims at Reduced Size and Increased Performance

While chipmakers are struggling with the FinFET based chip production below 5 nm process nodes, Samsung has planned to opt for GAA (gate all around) architecture. Samsung’s GAA redesigns the transistor, making it more power-efficient and better-performing than the existing Multi Bridge Channel FET (MBCFET™) that utilize stacked nanosheets. 

 

Samsung’s patented MBCFET™ is formed as a nanosheet, allowing for a larger current and simpler device integration. It allows to reduce the operating voltage below 0.75 V that had been extremely difficult with FinFET. This yields to 50% less power consumption or 30% more performance at 45% less chip area compared to 7 nm FinFET technology. Also, Samsung's GAA technology is compatible with current FinFET production line that means the today's fab running on mature process tools and methodology can be utilized for GAA transistors. Here is the infographic to learn more about how Samsung’s GAA is advancing the future of semiconductor technology.

Source: Samsung LINK

Written by : Abhishekkumar Thakur and Jonas Sundqvist

 

Researchers from MIT and University of Colorado produce smallest 3-D transistor yet

 

Using a new manufacturing technique, MIT researchers fabricated a 3-D transistor less than half the width of today’s slimmest commercial models, which could help cram far more transistors onto a single computer chip. Pictured is a cross-section of one of the researchers’ transistors that measures only 3 nanometers wide. Credits Courtesy of the researchers: Published under a Creative Commons Attribution Non-Commercial No Derivatives license

 

[MIT News] Researchers from MIT and the University of Colorado have fabricated a 3-D transistor that’s less than half the size of today’s smallest commercial models. To do so, they developed a novel microfabrication technique that modifies semiconductor material atom by atom.

As described in a paper presented at this week’s IEEE International Electron Devices Meeting, the researchers modified a recently invented chemical-etching technique, called thermal atomic level etching (thermal ALE), to enable precision modification of semiconductor materials at the atomic level. Using that technique, the researchers fabricated 3-D transistors that are as narrow as 2.5 nanometers and more efficient than their commercial counterparts.

Full story : MIT News LINK