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At the 2023 IEEE International Electron Devices Meeting (IEDM), Intel introduced significant advancements in transistor technology that continue to drive Moore's Law forward. Intel's Components Research group demonstrated innovative 3D stacked CMOS transistors, enhanced with backside power and direct backside contacts. This breakthrough in transistor architecture allows for more efficient scaling and improved performance, marking a first in the industry.
3D Stacked CMOS Transistors
Intel displayed the ability to vertically stack complementary field effect transistors (CFET) with a scaled gate pitch down to 60 nanometers (nm). This technology, combined with backside power and direct backside contacts, underscores Intel's leadership in gate-all-around transistors and its capacity to innovate beyond RibbonFET.
Beyond Five Nodes in Four Years
Intel's PowerVia, set for manufacturing readiness in 2024, represents the first implementation of backside power delivery. At IEDM 2023, the company identified ways to extend and scale backside power delivery beyond PowerVia, utilizing backside contacts and other novel vertical interconnects for efficient device stacking.
Integration of Silicon and GaN Transistors
Intel successfully integrated silicon transistors with gallium nitride (GaN) transistors on the same 300 mm wafer. The "DrGaN" technology showcased at the event demonstrates Intel's advancements in high-performance integrated circuits for power delivery.
Advances in 2D Transistor Space
Intel presented high-mobility transition metal dichalcogenide (TMD) 2D channel materials, showcasing prototypes of high-mobility TMD transistors for both NMOS and PMOS. Additionally, Intel revealed the world’s first gate-all-around (GAA) 2D TMD PMOS transistor and the first 2D PMOS transistor fabricated on a 300 mm wafer.
These developments by Intel represent a significant stride in semiconductor research, promising to enhance the efficiency and capabilities of future computing technologies.
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