AlixLabs Demonstrates 3 nanometers on Intel Silicon – Without EUV

The Swedish semiconductor company has fabricated leading-edge structures without using complex and costly lithography techniques.

The Swedish semiconductor company AlixLabs announces that it has used its technology to etch structures equivalent to commercial 3-nanometer circuits on Intel test silicon. Notably, this has been achieved without the use of extreme ultraviolet lithography (EUV) or advanced multi-patterning techniques such as SADP and SAQP (Self-Aligned Double Patterning and Self-Aligned Quad Patterning, respectively).

AlixLabs, a startup based in Lund, specializes in the development of Atomic Layer Etching (ALE), a type of plasma-based dry etching for cutting-edge structures, and ALE Pitch Splitting (APS), which enables transistor fins to be split using etching. The advantage of this approach is that it significantly reduces costs at the cutting edge, where wafer prices skyrocket with each new generation.

"We are pleased to demonstrate how APS can help the industry reduce its dependence on multi-patterning while lowering costs and environmental impact. Our technology enables the fabrication of sub-10-nanometer structures on silicon, and through Intel’s Test Vehicle Program, we have proven that sub-5-nanometer structures can be achieved using etching alone."

– Dmitry Suyatin, CTO and Co-Founder of AlixLabs

According to Dmitry Suyatin, AlixLabs’ CTO, this demonstration was made possible through Intel’s Test Vehicle Program, which provided test silicon for AlixLabs to process with its APS technology. While ALE has traditionally been limited to structures in the 10-nanometer class, AlixLabs' APS technique has significantly simplified the manufacturing of structures smaller than 5 nanometers.

Etching 3-nanometer-class structures without advanced EUV lithography, using only immersion lithography, is a significant breakthrough—provided the technology can be scaled and applied in practical manufacturing. AlixLabs has previously stated its goal of seeing its technology adopted by TSMC and Samsung for their 2-nanometer processes.

Since the industry moved past the 28-nanometer node, multi-patterning has become increasingly necessary to create smaller structures and transistors. This lithographic technique involves breaking down complex patterns into simpler ones and sequentially patterning them onto the silicon wafer for higher precision and detail. Lithography can perform this in two, three, or four steps (SADP, SAQP), though more steps are theoretically possible, they are considered too complex and costly for practical use at smaller nodes.

"APS technology demonstrates that complex multi-patterning techniques such as SADP and SAQP are not needed to manufacture circuits at 5 nanometers and below. This increases the potential to use immersion lithography for critical mask layers in 3-nanometer processes. These results were achieved with our early Alpha equipment, and Beta equipment will follow later in 2025. We thank Intel for enabling this demonstration and providing high-quality test silicon."

– Jonas Sundqvist, CEO and Co-Founder of AlixLabs

While lithographic multi-patterning is often necessary, it comes with several downsides. Each additional step requires more masks, which must be precisely aligned to form the final, complex pattern. Even a slight misalignment can lower yield and performance, but more importantly, it significantly extends production time. Avoiding multi-patterning whenever possible is therefore always preferable.

It is essential to distinguish between "nanometer-class" structures and actual physical nanometer measurements. What AlixLabs has achieved is a metal pitch (the distance between metal interconnects connecting transistor gates) of 25 nanometers through dry etching. This compares to TSMC’s most advanced 3-nanometer process, which achieves a metal pitch as low as 23 nanometers in certain high-density configurations.

AlixLabs highlights this test silicon as a major milestone towards commercialization and announces that more updates will follow later in 2025. Additional details will be presented by CTO Dmitry Suyatin at SPIE Advanced Lithography + Patterning in San Jose, California, on February 27, from 9:00–9:20 AM (local time).

Sources:

AlixLabs demonsterar 3 nanometer på Intel-kisel – utan EUV – Semi14

AlixLabs to Showcase Latest APS™ Findings at SPIE Advanced Lithography + Patterning – AlixLabs

Browse the 2025 program for SPIE Advanced Lithography + Patterning

JSR Expands Global Semiconductor Material Capabilities with New Photoresist Facilities, Advanced MOR Variants, and Strategic Acquisition of CVD/ALD Precursor Firm

JSR Corporation is expanding its global development and production of advanced photoresists by establishing a new R&D center in Japan and constructing a semiconductor photoresist plant in Korea. Since acquiring Inpria Corporation in 2021, JSR has been commercializing Metal Oxide Resist (MOR) for EUV lithography. The new R&D center in Japan’s Kanto region will enhance collaboration with global customers and partners, while the Korean plant, expected to begin operations in 2026, will handle the final production process for MOR to support local adoption. JSR aims to drive innovation in photoresists and help customers establish commercial production processes worldwide.

JSR's MOR, developed through its 2021 acquisition of Inpria Corporation, is a next-generation photoresist designed for EUV lithography. MOR is based on metal oxide nanoparticles, offering superior etch resistance and improved pattern resolution compared to traditional chemically amplified resists (CARs). This allows for finer feature definition and reduced line-edge roughness, critical for advanced semiconductor manufacturing below 10 nm. JSR has been scaling MOR for commercial adoption, with major semiconductor manufacturers evaluating its use in high-volume production. The company is expanding its R&D and manufacturing capacity, including a new R&D center in Japan and a production facility in Korea, to support global adoption of MOR.

JSR have investigated different flavors of MOR for EUV lithography, primarily focusing on variations in metal cores and process optimizations. Initially, zirconium (Zr) and hafnium (Hf) based MORs were explored, but their relatively low EUV absorption led researchers to investigate alternative metal cores such as titanium (Ti), zinc (Zn), indium (In), and tin (Sn). These new metal cores exhibited improved lithographic performance, achieving higher EUV absorption, smaller particle size, and better scum reduction. Additionally, process optimizations such as using higher dissolution rate photoacid generators (PAGs), new organic solvent developers, and lower soft bake temperatures were tested to improve scum removal and resolution. The new metal core variants demonstrated resolutions down to 13 nm with reduced defects, suggesting their potential for advanced semiconductor manufacturing.

In August 2024, JSR Corporation completed the acquisition of Yamanaka Hutech Corporation (YHC), a Kyoto-based manufacturer specializing in high-purity chemicals for semiconductor manufacturing. This strategic move allows JSR to expand its product portfolio to include Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) precursors, which are essential for forming advanced and complex semiconductor device structures. YHC, established in 1960, has over 60 years of experience in advanced molecular design, synthesis technology, and quality control systems, supplying high-quality CVD/ALD precursors to leading-edge semiconductor device manufacturers. The acquisition aligns with JSR's strategy to strengthen its position as a global supplier of semiconductor materials, enhancing its capabilities in both miniaturization and device structure innovation.

Sources:

JSR Expands Global Development and Production Functions for Leading-Edge Photoresists | 2024 | News | JSR Corporation

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High-Precision ALD and Etching Techniques Enable Sub-1nm EOT in Monolayer MoS₂ Transistors

Researchers from Stanford University and Yonsei University have investigated the role of silicon seed layers in enabling high-quality atomic layer deposition (ALD) of HfO₂ on monolayer MoS₂, achieving sub-nanometer equivalent oxide thickness (EOT) and precise threshold voltage control.

Researchers developed a method to achieve sub-1 nm equivalent oxide thickness (EOT) in monolayer MoS2 transistors using atomic layer deposition (ALD) of HfO2 with a silicon seed layer, enabling improved threshold voltage control and low hysteresis. They investigated six seed layer candidates (Si, Ge, Hf, La, Gd, Al2O3) and found that only Si and Ge preserved the integrity of MoS2. The Si seed provided the best interface, allowing for the fabrication of normally-off transistors with a well-behaved threshold voltage. The resulting devices demonstrated a low EOT of approximately 0.9 nm, minimal leakage current (<0.6 μA/cm²), and a subthreshold swing of ~80 mV/dec at room temperature. This method offers a simple and accessible approach to depositing high-quality top-gate dielectrics in common nanofabrication facilities.

The manufacturing process of monolayer MoS2 transistors in the study involves several key steps, including atomic layer deposition (ALD) and etching processes:

1. MoS2 Growth and Device Preparation: Monolayer MoS2 is synthesized using chemical vapor deposition (CVD) at 750°C on a SiO2 (90 nm) / p++ Si substrate. Alignment markers are deposited, and large contact pads (SiO2/Ti/Pd) are patterned and lifted off.

2. Channel Patterning and Etching: The transistor channels are defined via electron-beam lithography and etched using xenon difluoride (XeF2) chemistry. Gold source and drain contacts are then deposited using electron-beam evaporation.

3. Seed Layer Deposition: For the top-gate structure, ultrathin Si and Ge seed layers (~1 nm) are deposited using e-beam evaporation under high vacuum (~10⁻⁷ Torr). These seed layers are exposed to air before undergoing characterization via Raman and XPS measurements.

4. Atomic Layer Deposition (ALD) of HfO₂: The Si or Ge-seeded samples are placed in the ALD chamber at 200°C for 30 minutes before initiating the deposition process. HfO₂ is grown using tetrakis(dimethylamido)hafnium (TDMAH) and H₂O as precursors at 200°C. The ultrathin Si seed oxidizes into SiOx, forming a high-quality interface for dielectric growth.

5. Top-Gate Metallization and Etching: The Pd top gate is patterned and deposited using e-beam evaporation. To expose the contact pads for probing, the top-gate oxide is selectively removed using inductively coupled plasma (ICP) etching with CF₄.

6. Annealing: The top-gated devices undergo vacuum annealing at 150°C, while back-gated devices without top gates are annealed at 250°C for two hours to remove moisture and stabilize electrical characteristics.

This process enables the formation of high-quality MoS₂ transistors with sub-1 nm equivalent oxide thickness (EOT), low leakage, and precise threshold voltage control.

Sources:

Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS2 Transistors | Nano Letters

nl4c01775_si_001.pdf

Accuron Acquires Trymax to Strengthen Plasma Etch Equipment Portfolio and Expand Global Reach

Accuron Technologies has acquired a controlling interest in Trymax Semiconductor Equipment, a specialist in plasma-based and UV-based process equipment for semiconductor manufacturing. This acquisition strengthens Accuron’s presence in the semiconductor equipment sector and enhances its portfolio in the Etch & Clean process segment. Trymax, headquartered in the Netherlands, will continue to be led by its existing management team, ensuring continuity and execution of its expansion strategy. With Accuron’s resources and network, Trymax aims to accelerate its growth, broaden its customer base, and enhance product development. This move marks a strategic step for both companies, leveraging synergies to drive innovation and global expansion in semiconductor manufacturing solutions.

Sources:

Trymax joins Accuron Technologies group for further growth and expansion - Trymax Semiconductor

 

TU Eindhoven and LONGi Advance ALD ZnO Passivating Contacts, Achieving 24.3 Percent Efficiency in Silicon Solar Cells

Atomic layer deposition of ZnO for contact passivation in silicon solar cells has emerged as a promising alternative to TOPCon technology, with the recent breakthrough of zinc oxide passivating contacts achieving 24.3 percent efficiency in a LONGi solar cell. This development builds on research led by Bart Macco’s group at Eindhoven University of Technology, which pioneered the concept of ZnO passivating contacts. The breakthrough was further demonstrated by LONGi, which successfully integrated the technology into high-efficiency solar cells.

Key advancements include the use of an interfacial SiO2 layer for passivation, Al2O3 capping to retain hydrogen during annealing, and selective Al2O3 removal to enable electrical contact while preserving passivation. The integration of a low-work-function LiF layer has improved contact resistivity, reducing the need for heavy silicon doping.

ALD ZnO offers lower-temperature processing, thinner layers around five nanometers, and elimination of toxic dopants compared to doped poly-Si in TOPCon. With potential advantages in scalability, industrial feasibility, and initial efficiency gains, ZOPCon could surpass TOPCon, though further research is needed to enable bifacial designs, optimize lateral conductivity, and enhance stability for large-scale production.

Sources

Passivating Contacts for Silicon Solar Cells: A Zinc Oxide Breakthrough? – Atomic Limits

Jusung Engineering Records Strong Financial Performance and Expands ALD Equipment Shipments in 2024

Jusung Engineering Ltd. (KOSDAQ:036930) maintains a strong financial position with a net cash balance of ₩187.2 billion, as its cash reserves of ₩232.2 billion significantly exceed its ₩45.0 billion in debt. Despite total liabilities exceeding cash and receivables by ₩109.4 billion, the company's market capitalization of ₩1.37 trillion suggests that these obligations do not pose a substantial risk. Jusung Engineering's EBIT grew by an impressive 211% over the past year, further strengthening its ability to manage debt. Additionally, with free cash flow amounting to 80% of EBIT over the last three years, the company demonstrates solid cash flow management, reducing concerns over its debt burden. Given these factors, Jusung Engineering appears financially stable, with strong earnings and liquidity to support future growth.

Jusung Engineering shipped atomic layer deposition equipment for DTC silicon capacitor production on the 17th of last month.

In May 2024, Jusung Engineering unveiled plans to restructure its business by spinning off its semiconductor, solar, and display divisions into separate entities. The strategic move aimed to enhance operational efficiency and create greater shareholder value. However, by October 2024, the company decided to cancel the spin-off due to opposition from shareholders. The total stock purchase price for the stocks exercised in opposition exceeded KRW 50 billion, leading to the decision to maintain the company's current structure.

Beyond its financial success, Jusung Engineering made notable advancements in its technology offerings. In November 2024, the company shipped Atomic Layer Deposition (ALD) equipment for the production of Deep Trench Capacitor (DTC) Silicon Capacitors to Elspeth. 

Jusung Engineering's strong financial results, strategic decisions, and technological advancements reinforce its position as a key player in the global semiconductor industry. 

References:

JUSUNG ENGINEERINGLtd (KOSDAQ:036930) Could Easily Take On More Debt - Simply Wall St News

https://www.mk.co.kr/en/business/11231493
https://www.businesskorea.co.kr/news/articleView.html?idxno=216376
https://www.marketscreener.com/quote/stock/JUSUNG-ENGINEERING-CO-LTD-6494704/news/JUSUNG-ENGINEERING-Co-Ltd-cancelled-the-Spin-Off-of-Semiconductor-equipment-research-and-developme-48189649/
https://www.mk.co.kr/en/business/11164246