ASML Posts Strong Q1 2025 Results Amid AI-Driven Demand and Tariff Uncertainty

ASML kicked off 2025 with solid first-quarter performance, beating expectations on both earnings and revenue as demand for advanced lithography tools—driven by AI and next-generation semiconductor nodes—remained robust. While the company reaffirmed its growth outlook for 2025 and 2026, it also flagged increasing geopolitical uncertainty, particularly around US-China tariffs, as a risk factor for the months ahead.

ASML delivered strong Q1 2025 results, with earnings per share of $6.82 and revenue of $8.80 billion, reflecting a 56% year-over-year increase. The company met or exceeded guidance across major financial metrics, with gross margins at 54%, supported by favorable EUV system configurations and higher average selling prices. Net system sales reached €5.7 billion—€3.2 billion from EUV and €2.5 billion from non-EUV—while Installed Base Management sales added €2 billion. Bookings totaled €3.9 billion, mostly from logic customers. Despite a seasonal dip in free cash flow due to payment timing and capital investments, ASML remains financially strong with €9.1 billion in cash.

CEO Christophe Fouquet and CFO Roger Dassen emphasized the ongoing strength of AI as a demand driver, particularly in advanced logic and memory, while acknowledging growing macroeconomic and geopolitical uncertainties—especially around tariffs. They reiterated revenue expectations for 2025 between €30 billion and €35 billion, with 2026 also anticipated to be a growth year. However, they cautioned that new tariff dynamics introduce significant unknowns for both ASML and its customers, which may affect gross margins and the broader supply chain.

On the technology front, ASML made progress with both its Low NA and High NA EUV systems. The NXE:3800E tool is now shipping at full spec and is seeing strong adoption among logic and memory customers aiming for single-expose EUV. Meanwhile, the High NA NXE:5000 has demonstrated better maturity compared to the Low NA at a similar stage, with customers like Intel and Samsung reporting substantial gains in productivity and process simplification. ASML shipped its fifth NXE:5000 in Q1 and is beginning shipments of the NXE:5200, which will be critical for phase two customer evaluations. Full-scale adoption is expected from 2026–2028, contributing to ASML’s long-term revenue forecast of €44 billion to €60 billion by 2030.

ASML addressed growing concerns over US and China tariffs, highlighting the high level of uncertainty surrounding their scope and impact. The company is actively assessing both direct and indirect consequences, including tariffs on system sales, parts imports, and servicing operations. ASML emphasized that it is working closely with customers and suppliers to mitigate disruptions and ensure that tariff-related costs are fairly distributed across the value chain, rather than being absorbed solely by ASML. While management acknowledged that these discussions are still evolving and outcomes remain unclear, they cautioned that tariffs could introduce volatility in margins, supply chain planning, and customer delivery schedules. Despite this, ASML noted that the current business conversations with customers remain unchanged and the long-term strategic investment momentum—especially in logic and AI-related capacity—appears resilient.

Sources:

ASML Holding N.V. 2025 Q1 - Results - Earnings Call Presentation (NASDAQ:ASML) | Seeking Alpha

ASML Holding N.V. (ASML) Q1 2025 Earnings Call Transcript | Seeking Alpha

Applied Materials Unveils Industry-First Ruthenium-Cobalt Liner and Next-Gen Dielectrics to Enable 2nm Chip Wiring and Boost 3D Stacking for Energy-Efficient AI Computing

Applied Materials has announced new materials engineering breakthroughs aimed at improving energy efficiency in computing by enabling copper wiring to scale down to the 2nm node and beyond. Central to this innovation is the industry’s first high-volume use of ruthenium in a binary metal liner with cobalt (RuCo), which allows for thinner liners, improved copper fill, and up to 25% lower electrical resistance. This innovation, part of the new Endura™ Copper Barrier Seed IMS™ system, combines six process technologies in one high-vacuum system and is already being adopted by major logic chipmakers. These advances address the increasing challenges of interconnect resistance and mechanical weakness as chip feature sizes shrink.

Applied Materials’ new Endura™ Copper Barrier Seed IMS™ with Volta™ Ruthenium CVD combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond.

Complementing this, Applied also introduced an enhanced version of its long-standing Black Diamond™ low-k dielectric material, designed to reduce capacitance and reinforce chip strength — critical for advanced 3D stacking in logic and memory chips. These solutions help overcome scaling limitations associated with Moore’s Law and are critical for sustaining AI-driven computing advancements. As demand for high-performance, energy-efficient chips grows, Applied’s innovations are expanding its served market for interconnect technologies, which is projected to reach $7 billion per 100K wafer starts per month with the addition of backside power delivery.

With the semiconductor industry’s first use of ruthenium in high-volume production, Applied Materials' new binary metal combination of ruthenium and cobalt (RuCo) enables copper chip wiring to be scaled to the 2nm node and beyond and reduces electrical line resistance by as much as 25 percent.

Applied Materials today introduced an enhanced version of the company’s Producer™ Black Diamond™ PECVD dielectric film. This new material enables chip scaling to 2nm and below, while offering increased mechanical strength to help take 3D logic and memory stacking to new heights.

The new Producer™ Enhanced Black Diamond™ dielectric is a revolutionary product, enabling next-generation chips of the AI era. Enhanced Black Diamond™ addresses two key issues in leading-edge chips. As wires become closer together, parasitic capacitance increases. The phenomenon slows signals down, worsening performance and energy consumption. Additionally, damaging plasma manufacturing processes can cause the thinner insulating dielectric material between wires to fracture or collapse, potentially leading to chip failure (Embedded from Youtube : https://youtu.be/uJju9KNA-yE?si=ae-Eqc0Qaf5J8e0W).

Sources:

Applied Materials Unveils Chip Wiring Innovations for More Energy-Efficient Computing | Applied Materials

Photos accompanying this announcement are available at

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AlixLabs to Demonstrate APS™ on 300-millimeter UMC wafers at the 2025 CMC Conference

Atomic Layer Etching Pitch Splitting (APS) proven on more industry-leading wafers, doubling fin density and proving flexibility without EUV.

Austin, TX, USA/Stockholm, Sweden – April 10th, 2025 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), today demonstrates the latest in its line of groundbreaking development in advanced chip fabrication unveiling additional research into its novel semiconductor manufacturing process known as APS™ (Atomic Layer Etching Pitch Splitting) capable of doubling fin density while introducing the unprecedented flexibility to vary pitch and critical dimensions within the same wafer area.

Proven on 300-millimeter wafers provided by United Microelectronics Corporation (UMC), the APS™ technology successfully halved pitch compared to current industry benchmarks. This significant advancement was achieved entirely without relying on expensive and energy-intensive Extreme Ultraviolet (EUV) lithography.

Instead, APS™ leverages advanced etching techniques that substantially enhance sustainability, drastically reducing energy consumption without compromising throughput. Previous demonstrations of the APS™ process, validated through Intel’s Test Vehicle Program[1], confirmed its potential by achieving metal pitches as small as 25 nanometers.

“Today we are sharing more proof that the APS™ process can be a game changer for leading foundries. Thanks to UMC, we have been able to verify our process on production wafers that are shipped in quantities measured in millions of wafers annually,” said Dr. Robin Athle, Principal Researcher at AlixLabs. “Our mission is to create equipment that allows companies that don’t have access to EUV tools to scale down their production to 5 nanometer and beyond. By eliminating the dependency on EUV lithography, we are offering the industry a path towards more sustainable and economically feasible high-density chip production.”

Detailed results from AlixLabs’ UMC wafer tests and further insights into APS™ technology will be presented at the 2025 CMC Conference, scheduled for April 10th in Austin, Texas. Dr. Athle’s presentation “Atomic Layer Etching Pitch Splitting (APS™): a New Alternative to Multi Patterning” will be held at 4:00 PM at the Bergstrom Ballroom in Hilton Austin Airport Hotel.

Semiconductor Equipment Not Listed in Tariff Exemptions and EU and Japanese Suppliers Show Market Resilience

As of April 6, 2025, semiconductor equipment is not explicitly included in the list of exempted products under the U.S. tariffs detailed in Annex II of President Donald Trump’s executive order. While semiconductors and electronic components such as integrated circuits and diodes are covered, the exemption does not extend to manufacturing equipment.

Since the April 2, 2025 tariff announcement, ASML’s stock fell about 9.5%, showing more resilience than the Philadelphia Semiconductor Index (SOX), which dropped approximately 16.7% (deepest point).

Semiconductor equipment not listed in tariff exemptions, but EU and Japanese suppliers show market resilience

Despite this, European and Japanese semiconductor equipment companies have shown relative resilience in the wake of the April 2 tariff announcement. ASML, the Netherlands-based manufacturer of advanced lithography tools, saw its stock fall by about 9.5 percent, compared to a sharper 16.7 percent drop at the lowest point for the Philadelphia Semiconductor Index (SOX). This suggests continued investor confidence in ASML’s position and the essential nature of its equipment in semiconductor manufacturing.

Other global equipment firms also experienced moderate declines. ASM International, also from the Netherlands, saw an 8.3 percent drop. Tokyo Electron, Japan’s leading chip tool supplier, declined by 8.1 percent. In contrast, US-based companies faced more significant losses: Applied Materials dropped 14.1 percent, Lam Research fell 19.9 percent, and KLA Corporation declined by 16 percent between April 2 and April 4.

The broader tariff policy applies a 10 percent baseline rate on most imports starting April 5, with higher rates—up to 50 percent—for goods from 83 countries (including EU members) beginning April 9. Annex II outlines exemptions across multiple sectors: critical minerals, pharmaceuticals, energy products, integrated circuits, and fertilizers. However, semiconductor manufacturing equipment is not among the listed exemptions, indicating it remains subject to the new tariffs unless otherwise specified in future regulatory clarifications.

Despite this, the muted market response for EU and Japanese equipment makers highlights their global significance and the likelihood that US firms will continue to source vital tools from these suppliers, tariffs notwithstanding.

Background:

Starting on April 5, a 10% baseline tariff will be applied to nearly all products from all countries, with a few notable exceptions explained later. The executive order’s Annex I lists 57 countries (83 when accounting for all European Union member states) that will face higher tariffs of up to 50%, which go into effect on April 9. The new tariffs will stack on previous product-specific tariff rates. As a reminder, a tariff is a tax paid at the border by an importer seeking to bring products into the United States from a foreign country.

The exempted items in Annex II include, but are not limited to: copper, pharmaceuticals, semiconductors, lumber articles, certain critical minerals, energy/energy products, and products facing section 232 tariffs from the current administration (steel, aluminum, automobiles and any future section 232 investigations). While some of these industries were exempted due to their important roles in the economy (energy and critical minerals), others were excluded as they are a target for future restrictions (copper, lumber, pharmaceuticals and semiconductors).

Annex II lists a range of products exempted from trade actions, categorized across several sectors. It includes critical minerals and ores, such as copper, cobalt, lithium, tungsten, manganese, rare-earth elements, and graphite.

It also covers a wide array of chemicals and industrial compounds, including hydrofluoric acid, titanium dioxide, aluminum oxide, and various oxides, chlorides, and sulfates.

A significant portion of the list includes energy products, such as crude oil, natural gas (liquefied and gaseous), coal, petroleum derivatives, lubricants, and electricity.

The Annex lists several electronic components, including integrated circuits (processors, memory, amplifiers, other ICs), semiconductor devices (diodes, transistors, thyristors, optical isolators), and parts for these devices.

In agriculture, exempted products include fertilizers containing potash and NPK compounds, peat, and veterinary vaccines.

The document also includes many pharmaceuticals and medical products, such as antibiotics, hormones, vitamins, vaccines, and active pharmaceutical ingredients (APIs), along with cell therapy products and clinical trial materials.

There are exemptions for polymers and plastics in primary forms, including polyethylene, polypropylene, PTFE, silicones, and epoxide resins.

Additionally, doped materials for electronics, such as silicon wafers (HTS 38180000), and pigments and colorants like titanium dioxide and copper phthalocyanine, are listed.

Sources:

Understanding the New Tariffs | Market Intel | American Farm Bureau Federation

Tariffs Won’t Stop Companies Buying ASML’s Machines—Heard on the Street

AlixLabs Demonstrates 3 nanometers on Intel Silicon – Without EUV

The Swedish semiconductor company has fabricated leading-edge structures without using complex and costly lithography techniques.

The Swedish semiconductor company AlixLabs announces that it has used its technology to etch structures equivalent to commercial 3-nanometer circuits on Intel test silicon. Notably, this has been achieved without the use of extreme ultraviolet lithography (EUV) or advanced multi-patterning techniques such as SADP and SAQP (Self-Aligned Double Patterning and Self-Aligned Quad Patterning, respectively).

AlixLabs, a startup based in Lund, specializes in the development of Atomic Layer Etching (ALE), a type of plasma-based dry etching for cutting-edge structures, and ALE Pitch Splitting (APS), which enables transistor fins to be split using etching. The advantage of this approach is that it significantly reduces costs at the cutting edge, where wafer prices skyrocket with each new generation.

"We are pleased to demonstrate how APS can help the industry reduce its dependence on multi-patterning while lowering costs and environmental impact. Our technology enables the fabrication of sub-10-nanometer structures on silicon, and through Intel’s Test Vehicle Program, we have proven that sub-5-nanometer structures can be achieved using etching alone."

– Dmitry Suyatin, CTO and Co-Founder of AlixLabs

According to Dmitry Suyatin, AlixLabs’ CTO, this demonstration was made possible through Intel’s Test Vehicle Program, which provided test silicon for AlixLabs to process with its APS technology. While ALE has traditionally been limited to structures in the 10-nanometer class, AlixLabs' APS technique has significantly simplified the manufacturing of structures smaller than 5 nanometers.

Etching 3-nanometer-class structures without advanced EUV lithography, using only immersion lithography, is a significant breakthrough—provided the technology can be scaled and applied in practical manufacturing. AlixLabs has previously stated its goal of seeing its technology adopted by TSMC and Samsung for their 2-nanometer processes.

Since the industry moved past the 28-nanometer node, multi-patterning has become increasingly necessary to create smaller structures and transistors. This lithographic technique involves breaking down complex patterns into simpler ones and sequentially patterning them onto the silicon wafer for higher precision and detail. Lithography can perform this in two, three, or four steps (SADP, SAQP), though more steps are theoretically possible, they are considered too complex and costly for practical use at smaller nodes.

"APS technology demonstrates that complex multi-patterning techniques such as SADP and SAQP are not needed to manufacture circuits at 5 nanometers and below. This increases the potential to use immersion lithography for critical mask layers in 3-nanometer processes. These results were achieved with our early Alpha equipment, and Beta equipment will follow later in 2025. We thank Intel for enabling this demonstration and providing high-quality test silicon."

– Jonas Sundqvist, CEO and Co-Founder of AlixLabs

While lithographic multi-patterning is often necessary, it comes with several downsides. Each additional step requires more masks, which must be precisely aligned to form the final, complex pattern. Even a slight misalignment can lower yield and performance, but more importantly, it significantly extends production time. Avoiding multi-patterning whenever possible is therefore always preferable.

It is essential to distinguish between "nanometer-class" structures and actual physical nanometer measurements. What AlixLabs has achieved is a metal pitch (the distance between metal interconnects connecting transistor gates) of 25 nanometers through dry etching. This compares to TSMC’s most advanced 3-nanometer process, which achieves a metal pitch as low as 23 nanometers in certain high-density configurations.

AlixLabs highlights this test silicon as a major milestone towards commercialization and announces that more updates will follow later in 2025. Additional details will be presented by CTO Dmitry Suyatin at SPIE Advanced Lithography + Patterning in San Jose, California, on February 27, from 9:00–9:20 AM (local time).

Sources:

AlixLabs demonsterar 3 nanometer på Intel-kisel – utan EUV – Semi14

AlixLabs to Showcase Latest APS™ Findings at SPIE Advanced Lithography + Patterning – AlixLabs

Browse the 2025 program for SPIE Advanced Lithography + Patterning

Revolutionizing Silicon Photonics: First Electrically Pumped Group IV Laser Achieved for Seamless Integration on Silicon Chips

Researchers have achieved a groundbreaking milestone in silicon photonics by developing the first electrically pumped Group IV laser, made from silicon-germanium-tin layers directly grown on silicon wafers. This innovation paves the way for cost-effective, energy-efficient photonic integrated circuits in next-gen silicon chips.

The breakthrough in silicon photonics achieved by an international research team marks a transformative step in the materials and manufacturability of photonic devices. By developing the first electrically pumped continuous-wave laser made entirely of Group IV materials—silicon, germanium, and tin—the researchers overcame a long-standing challenge in integrating efficient light sources directly into silicon-based technologies. This laser is built using ultrathin layers of silicon-germanium-tin and germanium-tin, grown directly on silicon wafers. Its compatibility with conventional CMOS processes promises seamless integration into existing silicon manufacturing workflows, reducing costs and enhancing scalability. Unlike traditional lasers based on III-V materials, which are costly and complex to integrate with silicon, this innovation makes use of widely available Group IV elements, providing an energy-efficient and manufacturable solution for on-chip photonics.

This laser not only operates with a low current of 5 milliamperes at 2 volts but also features a sophisticated multi-quantum well structure and ring geometry to minimize power consumption and heat generation. Though the device currently functions at cryogenic temperatures, its development path mirrors earlier advancements in germanium-tin lasers that achieved room-temperature operation within a few years. The laser’s manufacturability is further underscored by its growth on standard silicon wafers, aligning with industry-standard processes. This achievement is poised to catalyze the adoption of low-cost photonic integrated circuits (PICs) in microchips, meeting the growing demand for energy-efficient hardware in AI and IoT applications while paving the way for advances in optical data transmission and next-generation silicon photonics.

Sources:

Silicon Photonics Breakthrough: The “Last Missing Piece” Now a Reality

SEMI World Fab Forecast Highlights Strong Fab Investments and New Fabs in 2025

The latest World Fab Forecast by SEMI, published on December 19, 2024, highlights strong growth in global semiconductor manufacturing from 2023 to 2025. Key takeaways from the report include increased investments in fab equipment and capacity expansions across both memory and foundry segments, indicating a resilient and growing industry.

SEMI’s latest World Fab Forecast report reveals that 18 new semiconductor fabs will begin construction in 2025, including three 200mm and fifteen 300mm facilities, primarily in the Americas, Japan, China, and Europe. These projects, set to start operations between 2026 and 2027, reflect the industry's focus on advanced nodes for AI and high-performance computing (HPC). Total semiconductor capacity is expected to grow at a 6.6% annual rate, driven by leading-edge logic technologies, while mainstream and mature nodes continue to support automotive, IoT, and power applications. Foundries remain key drivers of capacity growth, with generative AI demand boosting memory markets, particularly high-bandwidth memory (HBM). [Semiconductor Digest, LINK below]

For 2024, global fab equipment spending is projected to rise by 8% year-over-year to approximately 111 billion dollars, surpassing previous projections. The foundry segment is expected to account for 59 billion dollars of this investment, marking a 2% increase from 2023. The memory segment is set to see the most significant growth, with spending projected to jump by 50% to 34 billion dollars. This surge in memory investments reflects a rebound from the recent downturn and aligns with rising demand for advanced semiconductor technologies.

Looking ahead to 2025, fab equipment spending is expected to grow by an additional 4%, reaching approximately 116 billion dollars. The foundry segment will likely invest around 65 billion dollars, while the memory segment is forecasted to maintain robust spending at 33 billion dollars.

In terms of capacity expansion, the report predicts continued growth in both memory and foundry capacity. Memory capacity is expected to grow by 4% in 2024 and 3% in 2025, while foundry capacity, including pure-play foundries and IDM fabs, is projected to see 12% growth in 2024 and 11% in 2025. This reflects strong demand for advanced logic chips and specialty processes.

On the construction front, investments in new fab construction are expected to dip slightly in 2024, with a 5% decline to 39 billion dollars. However, SEMI anticipates 45 new construction projects for volume fabs, excluding R&D and pilot facilities, between 2025 and 2030. These projects are expected to support long-term demand growth across various segments, including AI chips, automotive semiconductors, and memory.

In 2025, the industry is expected to see the completion of several new fabs that are currently under construction. These new fabs will be crucial for meeting growing demand for advanced semiconductor technologies and are expected to bring significant additional capacity online. Many of these facilities will focus on next-generation nodes, particularly for applications in AI, high-performance computing, and automotive sectors. The report highlights that regions such as Taiwan, South Korea, and the US will see major investments in these new fabs, further strengthening their positions as key players in the global semiconductor supply chain.

Sources:

For more details, visit the official SEMI World Fab Forecast page:

https://www.semi.org/en/products-services/market-data/world-fab-forecast

Semiconductor Digest:

Eighteen New Semiconductor Fabs to Start Construction in 2025 - Semiconductor Digest

Intel Unveils 6 nm Gate Length Silicon RibbonFET CMOS and Breakthroughs in Semiconductor Scaling at IEDM 2024

Intel Corporation / Intel Foundry has demonstrated and extensively characterized gate-all-around Silicon RibbonFET CMOS transistors with a 6 nm gate length (LG). The study showcases nanoribbon silicon thickness (Tsi) scaling down to 3 nm, enhancing short-channel effects without compromising performance. Effective workfunction engineering mitigates threshold voltage increases caused by quantum confinement at scaled Tsi, enabling reduced threshold voltage at highly scaled gate lengths. Injection velocity of 1.13x10^7 cm/s is maintained at LG=6nm without degradation down to Tsi=3 nm, highlighting advancements crucial for continued gate length scaling and the ongoing realization of Moore's Law.

Intel Foundry made groundbreaking announcements at the IEEE International Electron Devices Meeting (IEDM) 2024, showcasing advancements that propel semiconductor technology into the next decade and beyond. Highlights include innovations in transistor and interconnect scaling, advanced packaging, and emerging materials to support the industry’s roadmap toward achieving 1 trillion transistors on a chip by 2030. Intel demonstrated a 25% capacitance reduction using subtractive ruthenium for interconnections, achieved a 100x throughput improvement in advanced packaging through Selective Layer Transfer (SLT), and advanced gate-all-around (GAA) transistor scaling with Silicon RibbonFET CMOS at a 6 nm gate length. Additionally, Intel unveiled new work on gate oxide modules for scaled 2D FETs, addressing the next phase of GAA scaling.

Among the key technical breakthroughs, subtractive ruthenium stands out as a metallization alternative to copper for interconnects, offering significant capacitance reductions at tight pitches while being cost-effective and scalable for high-volume manufacturing. SLT further revolutionizes advanced packaging with ultra-fast, flexible chip-to-chip assembly, enabling smaller, higher-density chiplets for AI and other demanding applications. For transistor scaling, Intel’s demonstration of Silicon RibbonFET CMOS at 6 nm gate length delivers industry-leading short-channel effects and performance, paving the way for continued scaling under Moore’s Law. Additionally, Intel’s progress with 2D GAA NMOS and PMOS transistors and gate oxide development signals readiness for post-silicon semiconductor technologies.

Intel also highlighted progress in gallium nitride (GaN) technology, demonstrating the first 300 mm GaN-on-TRSOI substrates for high-performance power and RF electronics. These developments, alongside Intel’s continued focus on advanced memory integration, hybrid bonding, and modular system expansion, underscore its commitment to addressing challenges in AI, energy efficiency, and thermal management. With these innovations, Intel Foundry continues to lead the charge in semiconductor advancements, ensuring a robust path forward for the trillion-transistor era.

Source: Intel IEDM 2024 Innovations

Decoupling from Dependence: The Global Semiconductor Industry Races to Diversify Amid Geopolitical Risks

The semiconductor industry is at a critical juncture, driven by the dual pressures of rising demand for advanced chips in artificial intelligence (AI) and the urgent need to mitigate geopolitical vulnerabilities. With Taiwan’s fabs, particularly TSMC, supplying over 90% of the world’s cutting-edge semiconductors, nations are rapidly investing in new fabs to reduce reliance on both Taiwan and China. While TSMC, Samsung, and Intel lead efforts to expand capacity in regions like the US, Europe, and Japan, these initiatives fall short of replacing Taiwan’s unparalleled output of 2 nm and below chips by 2030. Simultaneously, China’s struggle to compete at leading-edge nodes, compounded by export restrictions on critical tools, further underscores the fragility of the global semiconductor supply chain. These dynamics signal a transformative era as the free world works to establish more resilient and geographically diversified semiconductor ecosystems.

According to a recent article by FT (Source), the primary drivers for 2 nm technology development are the surging demand for custom and specialized chips, particularly in artificial intelligence (AI), and the need to create competitive alternatives to current large-scale semiconductor manufacturers. Rapidus, for instance, is targeting a niche in the AI market by producing bespoke chips that prioritize efficiency and can outperform more generic chips, such as those produced by Nvidia, in specific applications.

The motivation also includes addressing capacity limitations from dominant players like TSMC, which prioritizes large orders. Rapidus sees an opportunity to capture smaller customers who are willing to pay a premium for speed and customization. Additionally, geopolitical factors are influencing the push for advanced technology, with Japan aiming to reduce reliance on Taiwan's semiconductor manufacturing expertise and establish its own ecosystem for leading-edge production. 

This is why the semiconductor industry is advancing rapidly toward 3 nm and 2 nm process nodes, with leading players outlining production timelines and capacity expansions over the next five years. Below is a detailed overview of these developments, including plans from TSMC, Samsung, Intel, and Rapidus.

The forecast predicts a 540% growth in the global AI semiconductor market between 2020 and 2030, driven by increasing adoption across key segments such as servers, networking, edge devices, and PCs/smartphones. Servers are projected to dominate the market, reflecting the growing demand for AI in data centers and cloud computing, while networking and edge computing are expected to see rapid expansion, driven by real-time processing needs in IoT and automotive applications. Moderate growth is anticipated in the PCs/smartphone segment as AI integration in consumer electronics continues. Tokyo’s recent $65 billion investment in AI and semiconductor industries underscores the importance of this market, which is expected to exceed $400 billion by 2030, highlighting the transformative role of semiconductors in powering AI advancements across industries.

TSMC

Taiwan Semiconductor Manufacturing Company (TSMC) is enhancing its semiconductor fabrication capabilities globally, focusing on 3 nm and 2 nm and below nodes.

• 3 nm Production (Taiwan): TSMC began volume production of its 3 nm process technology in December 2022 at Fab 18, located in the Southern Taiwan Science Park (STSP). Fab 18 consists of eight phases, each featuring a cleanroom area of 58,000 square meters, roughly double the size of a standard logic fab. TSMC has invested over NT$1.86 trillion in Fab 18, creating more than 11,300 high-tech jobs.
  Source

• 2 nm Development (Taiwan): TSMC’s 2 nm process is scheduled for risk production in late 2024 and mass production in 2025. A new facility in Hsinchu Science Park is under construction, with equipment installation set for April 2024.
  Source

• 2 nm (Arizona, USA): TSMC is building a second fab in Arizona to produce 2 nm nodes, with production expected to begin in 2028. A third fab, focused on cutting-edge technologies, is planned for later this decade. This is part of a $40 billion investment, the largest foreign investment in Arizona's history.
  Source

Samsung

Samsung Electronics is expanding its semiconductor manufacturing capabilities in South Korea and the United States, focusing on 3 nm and 2 nm nodes.

• 3 nm Production (South Korea): Samsung began mass production of its first-generation 3 nm chips in the second half of 2022, using its proprietary Multi-Bridge Channel Field-Effect Transistor (MBCFET) technology, a Gate-All-Around (GAA) architecture. Second-generation 3 nm production began in 2023, offering improved energy efficiency and performance.
  Source

• 2 nm Development (South Korea): Samsung plans to start 2 nm production in 2025 for mobile devices, followed by high-performance computing in 2026 and automotive semiconductors by 2027. The 2 nm (SF2) process is expected to deliver a 12% performance increase, 25% power efficiency improvement, and 5% area reduction compared to 3 nm.
  Source

• Taylor Fab (Texas, USA): Samsung is constructing a $17 billion fab in Taylor, Texas. Initially planned for 4 nm production in late 2024, the fab may start directly with 2 nm technology in 2026 to align with Samsung’s broader roadmap.
  Source

Intel

Intel Corporation is investing in global semiconductor manufacturing, focusing on advanced nodes like Intel 3, Intel 20A, and Intel 18A.

• United States: Intel’s Fab 42 in Arizona produces 10 nm chips and is transitioning to Intel 7 and Intel 4 nodes. In Ohio, Intel is building two fabs with a $20 billion investment to produce Intel 18A by the decade's end.
  Source

• Europe: Intel’s Fab 34 in Ireland will produce Intel 4 technology using EUV lithography. In Germany, Intel delayed its is investing €17 billion to construct two fabs in Magdeburg, focusing on advanced nodes.
  Source

• Israel: Intel’s Fab 28 in Kiryat Gat, Israel, is transitioning from 10 nm to Intel 7 and Intel 4 processes. Intel has committed $10 billion to expand this facility.
  Source

Rapidus

Rapidus, a Japanese semiconductor start-up, aims to produce 2 nm chips, positioning itself as a significant player in the advanced semiconductor market.

• 2 nm Development: Rapidus plans to start trial production of 2 nm chips in April 2025, with mass production by 2027. The company is collaborating with IBM to integrate cutting-edge technology, including Extreme Ultraviolet (EUV) lithography.
  Source

• Manufacturing Facilities: Rapidus is building its IIM-1 fab in Chitose City, Hokkaido, Japan. The first EUV machine from ASML is expected to arrive in mid-December 2024.
  Source

• Strategic Approach: Rapidus is rethinking traditional manufacturing models by emphasizing smaller batch production with faster cycle times, aiming for greater efficiency and adaptability.
  Source

SMIC

China’s stake in leading-edge semiconductor manufacturing and AI is hindered by significant technological and geopolitical challenges. While domestic efforts, such as those by SMIC, have made strides in producing 7 nm chips, China remains far behind global leaders like TSMC, Samsung, and Intel, who are advancing toward 2 nm production. Critical dependencies on foreign equipment, such as ASML's EUV lithography machines, and U.S.-led export restrictions on advanced semiconductor tools and high-performance GPUs have further constrained its progress. Although China has invested heavily in AI development, its capabilities remain primarily focused on practical applications like surveillance and automation rather than leading innovation in foundational AI technologies. To conclude, China has an uphill battle to compete in the global semiconductor and AI industries.

Is the free world Decoupling from China and future risk of relying on Taiwan Fabs?

The global semiconductor industry is undergoing significant restructuring as it increasingly decouples from China and prepares for potential decoupling from Taiwan’s fabs. Geopolitical tensions, driven by concerns over China's ambitions toward Taiwan and its own restricted access to advanced chip-making technologies, have accelerated efforts by the US, Europe, and their allies to diversify supply chains and reduce dependency on both regions. Export controls targeting China, including restrictions on advanced chips and manufacturing tools, have prompted heavy investments in domestic semiconductor manufacturing in the US, Japan, South Korea, and Europe. Simultaneously, Taiwan’s pivotal role in leading-edge semiconductor production, dominated by TSMC, has highlighted vulnerabilities, spurring new fabs outside the island, such as TSMC’s facilities in Arizona and Samsung’s in Texas. These shifts reflect a broader trend toward creating more resilient, geographically dispersed semiconductor ecosystems that mitigate risks associated with reliance on any single region for critical technologies.

Current global plans for semiconductor manufacturing expansion aim to reduce dependency on Taiwan but fall short of ensuring sufficient non-Taiwan capacity for 2 nm and below nodes in the near term. Taiwan, led by TSMC, still dominates leading-edge semiconductor production, supplying over 90% of the world’s advanced chips. While significant investments are underway—such as TSMC's Arizona fabs, Samsung’s expansions in South Korea and Texas, and Intel's facilities in the US, Europe, and Israel—these efforts are unlikely to match Taiwan’s scale and technological leadership at 2 nm and below by 2027-2030.

For example, TSMC’s planned Arizona fab is projected to produce 2 nm chips by 2028, but its capacity will be a fraction of TSMC's output in Taiwan. Similarly, Samsung and Intel are progressing toward advanced nodes, but both face challenges in matching TSMC’s efficiency and yield at these cutting-edge technologies. Additionally, the complexity of EUV lithography and the industry's high R&D costs further limit the pace at which non-Taiwan fabs can scale to competitive capacities.

China’s Semiconductor Growth Slows Amid Sanctions, Legacy Chips Drive Output While Advanced Tech Struggle - what about ALD?

China's semiconductor industry is at a crossroads, navigating both growth opportunities and significant challenges. As US sanctions restrict access to critical technologies like EUV lithography, China's ambitions in advanced chip manufacturing are stifled, particularly in areas like AI and next-generation devices. While the country remains a strong player in legacy chip production, driven by robust demand from multinational corporations and its booming EV sector, the lack of advanced capabilities limits its ability to compete globally in cutting-edge technologies. At the same time, Atomic Layer Deposition (ALD), a cornerstone for technologies like GAAFET, DRAM, and 3D NAND, is seeing robust growth globally, with leading OEMs like ASMI, TEL, Applied Materials, and Lam Research emphasizing its pivotal role in scaling advanced architectures. However, China’s ALD market is expected to pivot towards supporting legacy nodes, as geopolitical constraints and domestic manufacturing dynamics shape its future. This evolving landscape underscores a shift in focus, with global players capitalizing on innovation while China's market transitions towards domestic and legacy-driven demand.

China’s semiconductor industry experienced slowing growth in October, reflecting the impact of looming US sanctions on advanced chip manufacturing. While legacy chip production and the EV sector drove industrial growth, advanced semiconductor capabilities remain constrained by restrictions on critical lithography equipment, such as ASML's EUV tools. This has stifled China’s ambitions in leading-edge technologies used in smartphones and AI. Despite producing 353 billion IC units from January to October, a 24.8% year-on-year increase, most of this growth was in legacy chips, heavily demanded by multinational corporations and export markets. Advanced production, meanwhile, lags behind as companies like TSMC and Samsung tighten services to Chinese firms, reflecting a broader global effort to limit China's technological advancement. These restrictions have heightened China's dependence on imported chips, which reached $315 billion in the first 10 months of 2024.

This chart shows the production output of integrated circuits (in hundred million units). China's IC production reflects the semiconductor cycle. The Chinese government sees semiconductors as an important focus for domestic production based on its Made in China 2025 plan. Note: Data for February are the cumulative total of January and February combined.

In Applied Materials' Q4 2024 earnings call, CEO Gary Dickerson highlighted the company's advancements in ALD technology. He emphasized that ALD is crucial for enabling next-generation semiconductor architectures, particularly in the development of gate-all-around transistors and advanced packaging solutions. Dickerson noted that Applied Materials' leadership in ALD positions the company to meet the increasing demand for energy-efficient computing and artificial intelligence applications. Applied Materials reported strong Q4 2024 earnings, highlighting the significant role of China despite challenges from US restrictions. China contributed approximately 30% of revenue, normalized after elevated demand for DRAM and NAND earlier in the year. The company's revenue from ICAPS (IoT, communications, automotive, power, and sensors) nodes remains strong in China, though potential slowing in automotive and industrial sectors may impact future growth. Applied is focusing on advanced materials engineering for cutting-edge technologies like gate-all-around transistors and high-bandwidth memory, areas critical for AI and energy-efficient computing. While China remains a key market for legacy technologies, restrictions on leading-edge technology sales are reshaping Applied’s growth trajectory, emphasizing global collaboration and innovation outside China. Looking ahead, Applied anticipates steady ICAPS demand and continued contributions from China at current levels.

Is the China market gloomy in ALD Equipment demand - hwat does the Tier 1 OMEs report on future ALD demand?

ALD is increasingly vital in semiconductor manufacturing, particularly for Gate-All-Around Field-Effect Transistors (GAAFET), DRAM, and 3D NAND technologies. Leading equipment manufacturers—ASM International (ASMI), Tokyo Electron (TEL), Applied Materials (AMAT), and Lam Research (LAM)—have highlighted ALD's significance in these areas.

ASM International:

ASMI has reported strong demand for its ALD equipment, driven by applications in advanced semiconductor nodes. The company noted that artificial intelligence (AI) and high-performance computing are propelling the need for GAAFET structures, where ALD processes are essential for precise material deposition. ASMI's recent financial results reflect this trend, with increased bookings attributed to robust demand in these sectors. 

Tokyo Electron:

TEL has been focusing on developing ALD technologies to enhance its position in the 3D NAND market. The company announced advancements aimed at improving 3D NAND flash memory production, positioning itself as a competitor to Lam Research in this domain. TEL's efforts underscore the growing importance of ALD in fabricating complex 3D structures required for high-density memory applications. 

Applied Materials:

AMAT has emphasized its leadership in materials engineering, including ALD, to support next-generation semiconductor architectures like GAAFETs. The company highlighted that ALD is crucial for developing advanced transistors and packaging solutions, which are essential for energy-efficient computing and AI applications. AMAT's focus on ALD aligns with the industry's shift towards more complex device structures. 

Lam Research:

LAM has been at the forefront of ALD technology, particularly for memory applications. The company introduced the ALTUS® Max E Series, featuring an all-ALD low-fluorine tungsten fill process, addressing challenges in scaling 3D NAND and DRAM devices. This innovation enables the production of higher aspect ratio structures with improved performance, demonstrating ALD's critical role in advancing memory technologies. 

In summary, leading OEMs recognize ALD as a pivotal technology for advancing semiconductor manufacturing, especially in GAAFET, DRAM, and 3D NAND applications. The continuous development and adoption of ALD processes are essential to meet the industry's evolving demands for higher performance and greater efficiency. 

China's demand for ALD equipment reflects a mixed outlook, influenced by geopolitical restrictions and market dynamics. Advanced semiconductor manufacturing in China faces constraints due to limited access to critical tools like EUV lithography, stifling progress in leading-edge applications like AI and smartphones. However, the market for legacy chip production remains robust, with strong output driven by demand from multinational corporations and export markets. Leading OEMs like Applied Materials and Lam Research report sustained engagement in the Chinese market, particularly in legacy nodes and AI-driven technologies, though future growth may slow due to challenges in automotive and industrial sectors. Despite these hurdles, Tier 1 OEMs, including ASML, have seen better-than-expected sales in China, highlighting its continued relevance in the global semiconductor landscape. Given that ALD is expected to have double digit growth for GAAFET, DRAM and NAND in leading edge nodes and memory going 3D the China market may be less important looking ahead and will transform to a legacy market for domestic and possibly Korean ALD OEMs.

Sources:

Applied Materials, Inc. (AMAT) Q4 2024 Earnings Call Transcript | Seeking Alpha

https://www.techedt.com/chinas-chip-production-slows-in-october-as-us-sanctions-loom

https://en.macromicro.me/collections/4345/mm-semiconductor/316/cn-china-output-of-integrated-circuit

Intel Sets Record with 2D TMD Transistors for Next-Gen Electronics

Intel researchers have achieved record-breaking performance in transistors using ultra-thin 2D transition metal dichalcogenides (TMDs) like MoS₂ and WSe₂ as channels. These monolayer materials are ideal for scaled devices but present challenges in integration due to their lack of atomic “dangling bonds.” By developing a specialized gate oxide atomic layer deposition (ALD) process and low-temperature gate cleaning, Intel built GAA NMOS and PMOS transistors with record subthreshold slopes and high drain currents. Specifically, they achieved a subthreshold slope of <75 mV/dec and Idmax >900 µA/µm in MoS₂ NMOS transistors, and a slope of 156 mV/dec with Idmax = 132 µA/µm in WSe₂ PMOS devices. These advancements highlight the promise of 2D TMDs for next-gen electronics and the need for further research to overcome integration challenges.

The images above are TEM characterizations of the record GAA NMOS device across the gate, showing a healthy, conformal GAA architecture with 43nm-wide monolayer MoS2 channel and conformal HfO2 with a thickness of ~4.0nm.

Record Performance with 2D Channels: Ultra-thin transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, are called monolayer, or 2D, materials because they’re one just atomic layer thick. They are being extensively studied for use as the channel in extremely scaled devices because of their excellent electrical performance. However, interfacing them with other materials in a device structure is difficult because at the atomic level there are no available “dangling bonds” to use. Thus, 2D channels have been a challenge to optimize.

Intel researchers will describe how they used 1) a unique gate oxide atomic layer deposition (ALD) process and 2) a low-temperature gate cleaning process to build GAA devices that demonstrated breakthrough performance for MoS2- and WSe2-based GAA NMOS and PMOS transistors, respectively. This includes record subthreshold slope (<75mv/dec) and drain current (Idmax>900 µA/µm at <50nm gate length) in sub-1nm-thick monolayer MoS2 GAA NMOS transistors. Also, using ruthenium (Ru) source and drain (S/D) contacts, they achieved record subthreshold slope (156mV/dec) and drain current (Idmax = 132µA/µm) in a ~30nm gate-length WSe2 PMOS device. The researchers say these results both underscore the potential of 2D TMDs for use in next-generation electronics, and highlight the critical need for continued research to address the remaining scientific and technological challenges.

Sources:

https://www.ieee-iedm.org/press-kit

(Paper #24.3, “Gate Oxide Module Development for Scaled GAA 2D FETs Enabling SS<75mV/d and Record Idmax>900µA/µm at Lg<50nm,” W. Mortelmans et al, Intel)

Intel's Breakthrough in RibbonFET Transistor Scaling Demonstrates Silicon Viability for Future Nodes

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Extremely Scaled Transistors from Intel: Intel researchers will show that silicon can continue to support the extreme gate length scaling which future technology nodes require. They will describe how they built RibbonFET CMOS transistors (Intel’s version of nanosheets) with 6nm gate lengths at 45nm contacted poly pitch (CPP, the spacing between adjacent transistor gates), with no degradation of electron mobility (how fast electrons can move through a material). The researchers will show that electron mobility doesn’t degrade until 3nm Tsi (silicon thickness), below which electron scattering due to surface roughness becomes an issue. They will describe how they achieved good short channel control (≤100mV/V at <4nm Tsi), with extremely low threshold voltage at these gate lengths through clever workfunction engineering. The work shows that 3nm is a practical scaling limit for RibbonFETs.

The image illustrates the behavior of drain-induced barrier lowering (DIBL) vs. silicon thickness (Tsi) at LG=18nm. It shows a reduction as Tsi is scaled from 10nm to 1.5nm; however, DIBL reduction saturates at Tsi <4nm, below which very little gain is obtained. PMOS DIBL is elevated vs. NMOS DIBL at the same Tsi. Also shown are TEM micrographs of a 1NR transistor with various Tsi values down to 1.5nm.

The series of images are (a) TEM micrograph and EDX scan of a completed 6nm RibbonFET device on a 1NR vehicle, showing a disconnected subfin; (b - d) are high-resolution cross-section TEMs for Tsi=5.5nm, 3.1nm and 1.7nm respectively, at 6nm gate length on a 1NR vehicle

Sources:

IEDM 2024 Press Kit Paper #2.2, “Silicon RibbonFET CMOS at 6nm Gate Length,” A. Agrawal et al, Intel https://www.ieee-iedm.org/press-kit

TSMC 2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects

TSMC’s New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will unveil the world’s most advanced logic technology. It is the company’s forthcoming 2nm CMOS (i.e., N2), platform, designed for energy-efficient computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or 30% power reduction) at >1.15x chip density versus the most advanced logic technology currently in production, TSMC’s own 3nm CMOS (N3) platform, introduced in late 2022.

The new N2 platform features GAA nanosheet transistors; middle-/back-end-of-line interconnects with the densest SRAM macro ever reported (~38Mb/mm²); and a holistic, system-technology co-optimized (STCO) architecture offering great design flexibility. That architecture includes a scalable copper-based redistribution layer and a flat passivation layer (for better performance, robust CPI, and seamless 3D integration); and through-silicon vias, or TSVs (for power/signal with F2F/F2B stacking). The researchers say the N2 platform is currently in risk production and scheduled for mass production in 2H’ 25. N2P (5% speed enhanced version of N2) targets to complete qualification in 2025 and mass production in 2026.

The cross-sectional image shows that the N2 platform’s Cu redistribution layer (RDL) and passivation provide seamless integration with 3D technologies.

Graph showing that the new N2 high-density cells gain 14~15% speed@power vs. N3E FinFlex 2-1 fin cells across the Vdd range; a 35% power savings at higher voltage; and a 24% power savings at lower voltage

The graph above compares two CMOS technology nodes, TSMC's N3E and N2, specifically for Arm's A715 core. N3E FinFlex (2-1 Fin) architecture, represented by the blue dotted line, operates at higher power but achieves higher speed than previous nodes. Operating at voltages between 0.5V and 0.9V, the N3E design can achieve significant performance levels but comes with a power increase. Now, N2 NanoFlex HD (High-Density) Energy-Efficient Cells as in the The N2 node, marked by the green dotted line, introduces "NanoFlex" cells that are optimized for energy efficiency. Compared to N3E, it achieves similar speeds but with substantially lower power consumption, marking a shift toward lower power designs in advanced nodes.

Key Improvements:

• When shifting from 0.6V to 0.55V in the N3E architecture, there's a 15% reduction in speed but a 24% reduction in power.
• For N2, at 0.85V, there's a 14% reduction in speed and a 35% reduction in power compared to similar performance points in N3E.
• These efficiency improvements are essential for high-performance applications in power-sensitive environments.

In summary, TSMC's N3E focuses on performance with FinFlex technology, while N2's NanoFlex HD cells target power efficiency, marking a clear trend in CMOS architecture evolution for balancing power and speed.

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Sources: 

IEDM Press kit Paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” G. Yeap et al, TSMC https://www.ieee-iedm.org/press-kit

Jusung Engineering Posts Stellar Q2 Recovery with 207% Sales Surge, Driven by Semiconductor Market Rebound

Jusung Engineering reported a robust financial recovery in the second quarter of 2024, with sales soaring by 207% to 97.3 billion won ($72.0 million) compared to the same period last year, and an operating profit margin of 37%. This turnaround follows a challenging first quarter and is driven by increased orders and deliveries of semiconductor equipment, including a significant contract with SK Hynix for DRAM manufacturing in China. The company's expertise in Atomic Layer Deposition (ALD) technology and its expansion into OLED and solar power sectors position it well for continued growth as the semiconductor market rebounds.

Sources:

Jusung Engineering Reports Robust Q2 Results with 207% Sales Growth - Businesskorea

Boosting the Future: Increased ALD Use Paves the Way for Advanced GAAFET Technology

The Biden administration is considering a complete ban on the export of chips utilizing Gate All-Around Field Effect Transistor (GAAFET) technology to China, Bloomberg reports (LINK). The rationale behind this potential ban is the concern that such advanced transistors could be leveraged for military applications and artificial intelligence (AI) advancements by China. This move follows previous restrictions from 2022, when the U.S. barred its Electronic Design and Automation (EDA) companies from selling tools necessary for GAAFET development to China. In addition, advanced chip exports from companies like Nvidia were restricted, with these measures being progressively tightened and expanded over time.

Atomic Layer Deposition (ALD) is celebrating its 50th anniversary in 2024. The anniversary marks 50 years since Dr. Tuomo Suntola and his colleagues filed the first patent for Atomic Layer Epitaxy in 1974, which laid the foundation for ALD technology. This milestone will be celebrated at various events, including the ALD 2024 conference, where Dr. Suntola is expected to deliver the opening remarks .

ASM International, a leader in Atomic Layer Deposition (ALD), plays a crucial role in enabling Gate-All-Around Field Effect Transistors (GAAFETs) and continued semiconductor scaling. ALD's precision in depositing ultra-thin, uniform films is essential for creating the high-performance, low-power structures required by GAAFETs. This technology, along with other advanced processes such as epitaxy and selective etching, supports the intricate fabrication steps needed for these next-generation transistors.

The production of GAAFETs requires a significant increase in the use of ALD technology - maybe up to 40% more according to ASM. ALD is essential for creating the ultra-thin, uniform films needed for GAAFET structures, ensuring high-quality, defect-free layers that are critical for advanced transistor performance. This technology enables precise control over the deposition process, crucial for developing high-k dielectrics and other materials that enhance GAAFET performance and efficiency. As the semiconductor industry now transitions from FinFET to GAAFET technology, leveraging ALD's capabilities is vital for maintaining and advancing Moore's Law, enabling more powerful and energy-efficient chips using existing manufacturing infrastructure

Applied Materials has outlined next-generation tools essential for producing 3nm and GAA transistors, such as those in Samsung's upcoming 3GAE and 3GAP technologies. These advanced tools address the complexities of GAA transistor manufacturing, including precise lithography, epitaxy, and selective materials removal. Applied's Producer Selectra Selective Etch IMS tool is pivotal in defining channel width without damaging surrounding materials, while the Centura Prime Epi tool ensures clean deposition of Si and SiGe nanosheets. Additionally, their Integrated Materials Solution (IMS) systems integrate atomic layer deposition (ALD), thermal steps, and plasma treatments to optimize the gate oxide stack, enhancing performance and reducing gate leakage. These innovations are crucial as they enable higher performance, lower power consumption, and greater transistor density, aligning with the industry's move from FinFET to GAA technology.

Today GAA transistors are currently in mass production only by Samsung, which offered the technology to customers with its 3-nanometer process in 2022. Intel is set to follow, producing GAAFET on its 2-nanometer process expected to be available in its products later this year. TSMC, the market leader, plans to introduce GAAFET with its own 2 nm process in 2025. The GAAFET technology itself is not inherently suited for AI or military applications but represents an evolution in transistor design, enabling denser packing of transistors as lithography equipment and manufacturing processes advance. This technology shift, akin to transitioning to a new node, typically results in either reduced power consumption or improved performance by 15-25%.

The improvements facilitated by GAAFET could significantly enhance the capabilities available to China. SMIC, China's largest contract manufacturer, currently produces chips on a 7 nm process and is believed to be capable of reaching at least 5 nanometers with existing tools. The combination of this process with GAAFET could theoretically prevent China from falling too far behind Western advancements. However, China has been effectively shut out from developing GAAFET using tools from leading EDA companies, all of which are American. Additionally, the Dutch company ASML, dominant in the lithography equipment market, has not sold its EUV (Extreme Ultraviolet) machines to China and faced further restrictions in 2023 on selling its advanced DUV (Deep Ultraviolet) equipment. In April 2024, ASML took another step in the tech war against China by announcing that it would no longer service existing equipment in China, potentially crippling the country's semiconductor manufacturing capabilities. The specific details of the new export bans are still unclear, but Reuters notes that initial proposals have faced criticism from the U.S. semiconductor industry for being overly broad and extensive.

Source: USA överväger ytterligare GAAFET-sanktioner mot Kina – Semi14, www.ASM.com, Applied Materials Outlines Next-Gen Tools for 3nm and GAA Transistor Era (anandtech.com), Atomic layer deposition, next-gen transistors, and ASM (techfund.one)

ASML Unveils Hyper-NA EUV: Pioneering New Frontiers in Chip Innovation and Efficiency

ASML, the leader in lithography technology for semiconductor manufacturing, has launched its latest breakthrough: the Hyper-NA EUV tool and Intel being the first customer getting its first machine earlier this year. This leading-edge technology, which boosts the numerical aperture (NA) from 0.55 to 0.75, is poised to revolutionize chip design by enabling unprecedented levels of transistor density. Scheduled for introduction around 2030, Hyper-NA promises to extend the capabilities of chipmakers far beyond current limits, opening up new possibilities for intricate and powerful chip designs.

The presentation announcing ASML's Hyper-NA EUV technology was delivered by the company's former president, Martin van den Brink, at imec's ITF World event in Antwerp. 

Reduction in Double Patterning Complexity: Hyper-NA EUV technology simplifies the lithography process by reducing the need for double patterning, i.e., like Litho-Etch-Litho-Etch (LELE) etc., a method that involves aligning two masks perfectly to create intricate chip designs. By providing higher resolution and precision, Hyper-NA EUV minimizes the challenges and costs associated with double patterning, streamlining production and enhancing overall efficiency for chipmakers. However, there are a myriad of multi-patterning technologies deployed out there and SMIC, the main Chinese foundry, is reportedly using sextuple-patterning for its 5 nm technology.

Hyper-NA EUV technology is designed to significantly increase the productivity of semiconductor manufacturing, enabling the processing of 400 to 500 wafers per hour. This improvement will help chipmakers meet the growing demand for high-performance chips more efficiently, reducing production time and costs while maintaining high precision and quality.

The adoption of Hyper-NA EUV presents a myriad of opportunities for the semiconductor industry. As Intel has already installed the first High-NA systems, showcasing the potential of these advanced tools to enhance processor performance. As other industry leaders like TSMC, Samsung, Micron, and SK Hynix explore the adoption of High-NA and eventually Hyper-NA, the competitive landscape is set for a dynamic transformation. Innovations such as advanced polarizers to overcome light polarization issues and improvements in resist materials and etch selectivity will enable more precise and efficient chip manufacturing.

ASML’s Hyper-NA EUV technology is not just a short-term solution but part of a long-term roadmap that will sustain chip innovation for the next decade and beyond. Collaborative research and development efforts, including Imec’s simulations and Zeiss’s lens designs, highlight the cooperative spirit driving this technological advancement. As chip designers like Nvidia, Apple, and AMD leverage these tools at leading foundries such as TSMC, the future of chip design looks brighter than ever, promising enhanced productivity, technological leadership, and sustained growth. Hyper-NA EUV is set to redefine what is possible in the world of semiconductors, driving the industry towards new heights of efficiency and performance.

Sources: ASML Aims for Hyper-NA EUV, Shrinking Chip Limits - EE Times