Showing posts with label Semiconductor. Show all posts
Showing posts with label Semiconductor. Show all posts

Sunday, May 18, 2025

SiCarrier Seeks $2.8 Billion to Advance Chipmaking Equipment

SiCarrier, a Chinese chip equipment manufacturer closely associated with Huawei and owned by the Shenzhen city government, is seeking $2.8 billion in funding to advance its ambitions of becoming China's leading chipmaking equipment provider. Founded in 2021, the company aims to surpass domestic rivals such as Naura and AMEC, amid U.S. export restrictions that have fueled China's drive for semiconductor self-sufficiency. The fundraising, targeting a valuation of $11 billion, is expected to conclude soon, with proceeds allocated primarily to R&D. State-owned firms and domestic investors have shown strong interest. Despite showcasing 30 products at Semicon China 2025, most of its tools remain under development and are not yet production-ready. SiCarrier has filed 92 patents, indicating plans to offer a comprehensive suite of chipmaking tools, including lithography and AI-driven inspection systems. However, its deep ties to Huawei have raised concerns among potential customers over data security and trade secret protection. Industry experts suggest full operational independence from Huawei is essential for broader market acceptance and long-term growth.

"Founded in 2021 and owned by the Shenzhen city government, SiCarrier is largely seen as a Huawei supplier. But it wants to become the leading domestic provider of chipmaking equipment in China, surpassing Naura and Advanced Micro-Fabrication Equipment China (AMEC), according to four people with knowledge of its goals."


A Reuters review of 92 patents filed by Shenzhen SiCarrier Industry Machines and its parent Shenzhen SiCarrier Technologies between October 2022 and March 2025 reveals the company’s ambitious plan to establish itself as a comprehensive supplier of semiconductor manufacturing equipment. Unlike domestic peers such as Naura and AMEC, which have taken more focused approaches, SiCarrier is pursuing an expansive product roadmap that spans the entire chip production chain—from wafer metrology and defect inspection to etching and atomic layer deposition (ALD) systems. These filings, verified through Anaqua’s AcclaimIP database, illustrate SiCarrier’s intention to compete head-on with established global players such as KLA, Lam Research, and Tokyo Electron, particularly in process-critical segments like thin-film deposition and etch uniformity control. Notably, SiCarrier is investing in AI-powered wafer defect recognition, a frontier area aimed at enhancing production yields, especially important in advanced nodes where precision is paramount. Industry observers cited by Reuters suggest metrology and inspection tools offer SiCarrier the most immediate opportunity, given the absence of a dominant Chinese competitor in that space. The patent portfolio also reveals efforts to close the technological gap in lithography by focusing on components for deep ultraviolet (DUV) systems and multi-patterning techniques. These are presented as domestic alternatives to extreme ultraviolet (EUV) lithography, which remains out of reach due to US export controls. However, experts like Dan Hutcheson of TechInsights caution that the multi-patterning approach—though pioneered by Intel and used by TSMC at 7 nm—carries known drawbacks such as increased complexity and yield challenges, stemming from its reliance on sequential deposition and several etch processes. 



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Tuesday, May 6, 2025

Tokyo Electron Delivers Record FY2025 Results Amid AI Boom, Eyes Growth Through CVD Innovation and Geopolitical Resilience

Tokyo Electron (TEL) achieved a record-breaking financial year in FY2025, with strong top- and bottom-line growth driven by robust global demand for advanced semiconductor equipment. Net sales rose by 32.8% year-on-year to approximately ¥2.43 trillion (around $15.7 billion USD), marking the highest in the company's history. Operating profit surged to ¥697.3 billion (about $4.5 billion USD), supported by an improved operating margin of 28.7%. Growth was underpinned by increased investment in leading-edge logic and memory, particularly High Bandwidth Memory (HBM) and advanced DRAM nodes, where TEL maintained or expanded market share through key Process of Record (POR) wins in etch and wafer bonding technologies. Revenue contributions diversified geographically, with notable gains in South Korea and Taiwan, even as China remained a key market. TEL also demonstrated strong cash flow, increased its R&D and capital investments, and returned significant value to shareholders through dividends and buybacks. Looking ahead, TEL forecasts continued growth in FY2026, positioning itself to capitalise on accelerating AI, 2nm logic, and heterogeneous integration trends.

Tokyo Electron TEL has demonstrated strong financial performance and strategic market expansion through FY2025, according to their investor presentation dated April 30, 2025. Their net sales, gross profit, operating profit, and net income have all reached record highs, signaling both operational efficiency and favorable market conditions.

LINK: Tokyo Electron Limited 2025 Q4 - Results - Earnings Call Presentation (OTCMKTS:TOELY) | Seeking Alpha

Tokyo Electron's Q4 FY2025 earnings call highlighted strong financial performance and an optimistic forward outlook amid geopolitical uncertainties. Despite global concerns around US tariffs and export controls—particularly in China, which saw its WFE market share fall to 35%—TEL stated that it has not observed any significant changes in customer investment sentiment or competitive dynamics. The company reaffirmed its strategy of focusing on long-term innovation rather than short-term regulatory shifts, underscoring its commitment to developing higher-productivity tools to offset potential external headwinds. Looking ahead, TEL forecasts continued double-digit WFE market growth into calendar 2026, driven by AI infrastructure demand, 2nm logic, and HBM scaling. The company plans record-high investments of ¥300 billion in R&D and ¥240 billion in CapEx for FY2026, reflecting confidence in sustained momentum across DRAM, advanced logic, and packaging technologies. TEL aims to expand global market share and reach ambitious mid-term goals, including over ¥1 trillion in operating profit and 35%+ OPM, by capitalising on technology transitions such as GAA, backside PDN, and heterogeneous integration.

LINK: Tokyo Electron Limited (TOELY) Q4 2025 Earnings Call Transcript | Seeking Alpha

Revenue and Profitability Growth:
Net sales increased significantly from ¥1,399.1 billion in FY2021 to ¥2,431.5 billion in FY2025, a 74% increase over four years. The gross profit also rose steadily, reaching ¥1,146.2 billion in FY2025, up from ¥564.9 billion in FY2021. Operating profit followed suit, more than doubling from ¥320.6 billion to ¥697.3 billion. These trends underscore TEL’s ability to scale profitably, with operating margins rising from 22.9% in FY2021 to 28.7% in FY2025. Return on equity (ROE) also remained strong, peaking at 37.2% in FY2022 and settling at 30.3% in FY2025, a testament to effective capital management.


Regional Sales Composition:

The revenue breakdown by region from Q1 FY2024 to Q4 FY2025 shows growing diversification. Notably, China has remained the single largest market, although its share declined from 47.4% in Q4 FY2024 to 34.3% in Q4 FY2025, reflecting a strategic balancing across geographies. South Korea, Taiwan, and North America significantly increased their contributions, with South Korea reaching ¥147.0 billion and Taiwan ¥135.8 billion in Q4 FY2025. This reflects growing demand from advanced logic and memory fabrication customers in these regions.


In FY2025, Tokyo Electron’s semiconductor production equipment (SPE) sales reached ¥1.86 trillion, driven by a sharp rise in DRAM-related investments, particularly for high-bandwidth memory (HBM), which accounted for 31% of total sales. Non-volatile memory (NAND) remained stable at 7%, while non-memory segments, including logic and foundry, continued to dominate with 62%, reflecting robust demand from both advanced and mature nodes. The overall recovery and expansion of customer investments across segments underpinned this strong performance.


Market Segment Performance

Tokyo Electron’s global market share in CY2024 demonstrates its leadership across multiple core segments of the semiconductor production equipment market. The company holds a commanding 92% share in coater/developer systems, underlining its unparalleled position in photoresist processing for advanced lithography applications. It also leads the wafer prober segment with a 38% share and maintains robust positions in key deposition categories, including 38% in CVD and 37% in oxidation/diffusion systems. In contrast, TEL’s market share in ALD stands at 16%, notably behind ASM International, highlighting an opportunity for expansion in this strategically important technology as the industry moves towards GAA and other 3D device structures. Performance in dry etch (27%), cleaning systems (21%), and wafer bonding (32%) rounds out a broadly competitive portfolio that positions TEL to effectively support ongoing advancements in scaling, heterogeneous integration, and high-performance packaging across logic, memory, and AI-related applications.




To further expand our future profit, we made steady progress in penetrating into new technology domains. Specifically, we released multiple new outstanding products contributing to the semiconductor technology innovation. For example, penetration to untapped segments such as single-wafer plasma CVD and PVD, gas cluster beam system which improves efficiency of leading-edge lithography, and laser-lift-off system to drastically decrease environmental footprint of processing. In fiscal 2025, we conducted share repurchase of about ¥150 billion in total.
- Toshiki Kawai - Representative Director, President and CEO


 

New product 2025 Episode™ single-wafer CVD platform

Episode™ 1 is Tokyo Electron's latest single-wafer CVD platform, launched in 2024 to address the challenges of advanced device scaling in logic, DRAM, and future AI processors. It supports up to eight process modules, enabling complex, uninterrupted multi-step processing. The system integrates the OPTCURE™ module for native oxide removal and ORTAS™ for titanium CVD, allowing immediate Ti deposition to minimise contact resistance in advanced interconnects. Episode™ 1 replaces traditional PVD with CVD to achieve uniform, low-resistivity films in high aspect ratio structures such as deep contact holes. With a 45% smaller footprint than its predecessor and advanced edge computing, data analytics, and environmental tracking capabilities, the system enhances fab productivity, engineer efficiency, and readiness for new materials in next-generation device manufacturing.

The TEL Episode™ 1 system shown in the image seems to feature twin or dual single-wafer process chambers, which is typical in modular CVD tools designed for high throughput. Each visible module (with two load ports per unit) likely contains two process chambers within the same footprint to maximise wafer handling efficiency and enable parallel processing—common in tools aimed at advanced logic and memory manufacturing.


Episode™ 1 offers a reduced footprint. Compared with the Triase+™ series, twice as many smaller modules can be installed in a system. With the same number of modules installed, Episode™ 1 takes up about 45% less fab space than its predecessor

LINK: Episode™ 1 Single-Wafer Deposition System for Semiconductors: Driving the Evolution of AI Semiconductors to Transform Everyday Life | Blog | Tokyo Electron Ltd.


Monday, May 5, 2025

ASM International Strengthens ALD Market Leadership Amid Strong Q1 Results, Growing GAA Adoption, and Strategic Positioning for Advanced Node Demand

ASM International’s Q1 2025 results reaffirm its leadership in Atomic Layer Deposition (ALD), a technology central to enabling advanced semiconductor nodes such as 2nm and beyond. With ALD accounting for more than half of its equipment revenue and strong customer engagement in leading-edge logic and memory, ASM is well-positioned to capitalise on rising demand driven by GAA architectures, high-bandwidth memory, and ongoing technology node transitions.

ASM International’s Q1 2025 results reinforce its leadership in ALD, a foundational technology for enabling advanced semiconductor nodes. ALD represented more than half of ASM’s equipment revenue, with the market expected to grow at a compound annual rate of 10–14% through 2027, and ASM maintaining a leading market share above 55% in the segments they compete in:

Single-Wafer ALD Tools

ASM’s flagship ALD platforms are single-wafer systems, which provide high precision, conformality, and process flexibility. These are used primarily in leading-edge logic and memory production.

  • Key Platforms:

    • XP8 and XP8 QCM: High-productivity platforms supporting multiple process chambers; widely used for high-volume manufacturing.

    • Previum and Previum Pro: Previum systems incorporate an integrated epitaxial (EPI) pre-clean step that effectively removes 15–20 monolayers of native oxide from the substrate surface. This step is crucial for ensuring high-quality EPI film growth.

    • Pulsar®: Specialised for high-k dielectrics, such as hafnium oxide (HfO₂) typically used in gate stacks.

    • Eagle® XP8: Designed for advanced metal ALD (e.g. TiN, W), often used in logic and memory applications including barrier and liner layers.

ASM International’s strategic alignment with the prevailing trends in the wafer fab equipment (WFE) market and its concentrated customer base. Logic and foundry applications are set to remain the dominant segment of WFE spending through 2026, reinforcing ASM’s focus on enabling advanced nodes such as FinFET and GAA, where Epitaxy (Epi) and atomic layer deposition (ALD) are critical. The company’s FY24 revenue profile shows that its top five customers accounted for 51% of sales, while the top ten represented 70%, indicating strong relationships with leading-edge semiconductor manufacturers. These likely include TSMC, Samsung, Intel, SK hynix, and Micron—ASM’s probable top customers given their leading-edge node adoption and high ALD utilisation. Others may include GlobalFoundries, UMC, SMIC, and select IDMs. 

The industry’s shift to gate-all-around (GAA) transistor architectures at 2 nm and beyond is driving increased demand for single-wafer ALD and silicon epitaxy (Si Epi) processes, which are essential for integrating high-k dielectrics, advanced metals, and high aspect ratio features in both logic and memory devices. ASM’s deep engagement with leading-edge customers—particularly in logic/foundry and high-bandwidth memory (HBM) DRAM—has already translated into strong revenue contributions. Additionally, early tool shipments for the 1.4nm node reflect continued confidence from top-tier clients and extend ASM’s growth visibility as chipmakers prepare for more complex architectures requiring precise material deposition.


ASMI presented a robust growth trajectory of the single-wafer Atomic Layer Deposition (ALD) market, projected to reach between US$4.2 billion and US$5.0 billion by 2027, with a compound annual growth rate (CAGR) of 10–14% from 2022.

Summary from ASM International Q1 2025 Earnings Call:

1. ALD Market Outlook:
ALD continues to be a key growth driver for ASM, with equipment sales led by ALD and expectations of a strong increase in GAA (gate-all-around) related demand throughout 2025. ALD intensity is rising as leading-edge nodes (2 nm and 1.4 nm) require more deposition steps for complex 3D structures, high-k dielectrics, and metal gate stacks. ASM confirmed ongoing R&D engagement for 1.4nm and highlighted that ALD demand will further accelerate in next-gen nodes, backside power delivery, and in advanced DRAM (e.g. HBM), which increasingly adopt logic-like ALD layers. ASM remains confident in long-term ALD market growth, forecasting double-digit increases in application layers per node.

2. Trade, Tariffs, and Geopolitical Risk:
ASM addressed potential impacts from new US tariff announcements, noting no immediate effect on equipment, but acknowledging possible indirect macroeconomic consequences. The company has prepared multiple mitigation scenarios, including flexible global manufacturing—already expanding in Korea and establishing capability in Arizona (set to scale in 2H 2026). ASM emphasised its ability to localise production quickly if needed. While there’s been no pull-forward of tool orders due to tariff concerns, the company is monitoring the situation closely and maintaining optionality in its supply chain to navigate shifting trade conditions.

ASM International NV (ASMIY) Q1 2025 Earnings Call Transcript | Seeking Alpha

"ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength"

ASM International (ASMIY) delivered a strong Q1 FY25, exceeding expectations in revenue, margins, and orders, driven by robust AI infrastructure demand, early ramp-up of 2nm nodes, and resilient performance in China. Despite macroeconomic risks and export controls, ASM saw solid contributions from mature logic foundries and high-bandwidth memory (HBM), which relies on advanced techniques like ALD and Epi. The company’s improved operational efficiency, growing AI demand, and clearer long-term growth visibility led the author to upgrade the stock to a “strong buy,” supported by a belief that ASM can reach the high end of its FY27 revenue target with continued margin expansion.

LINK: ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength (OTCMKTS:ASMIY) | Seeking Alpha

Sunday, May 4, 2025

Semiconductor Equipment Stocks: Analysis of Decline and Recovery (Feb–May 2025)

Between February and May 2025, the semiconductor equipment sector experienced significant market volatility, driven by a combination of geopolitical developments, trade policy shifts, and evolving industry dynamics. Notably, U.S. tariff announcements and uncertainty in AI infrastructure investment led to sharp downturns in stock valuations across key players such as ASML, Applied Materials, KLA, Lam Research, and ASM International. Despite the initial decline, the sector showed resilience with signs of recovery emerging in late April. Here is an overview of the key events influencing these market movements, along with insights into the partial rebound observed by early May.



📉 February 24, 2025: Tariff Concerns and AI Sector Weakness

On February 24, 2025, semiconductor equipment stocks experienced a downturn due to escalating concerns over new U.S. tariffs and a slowdown in the AI sector. President Trump's administration announced a series of tariffs that heightened trade tensions, particularly affecting technology companies with significant exposure to international markets. Additionally, the AI sector faced headwinds as companies like Super Micro Computer Inc. issued profit warnings, citing delays in AI infrastructure investments. These factors collectively contributed to a decline in investor confidence, leading to a sell-off in semiconductor-related stocks.

Stocks Get Hit as Economic Jitters Spur Bond Rally: Markets Wrap

Bitcoin Sinks Below $90,000; US to Intensify Chip Controls Over China

📉 March 25, 2025: Temporary Relief Amid Ongoing Uncertainty

On March 25, 2025, there was a brief respite in the downward trend as President Trump announced exemptions for semiconductor equipment and other electronics from the newly imposed tariffs. This announcement provided temporary relief to the market, leading to a modest rebound in semiconductor stocks. However, the relief was short-lived as uncertainties persisted regarding the broader implications of the trade policies and their potential impact on global supply chains.

Stock Market News, March 26, 2025: Nasdaq Falls; Nvidia, Tesla Drop More Than 5%

📉 April 1, 2025: Market Crash Triggered by Sweeping Tariffs

On April 1, 2025, the semiconductor sector was significantly impacted by a broader market crash initiated by the announcement of sweeping tariffs by the U.S. administration. These tariffs affected a wide range of imports, leading to fears of a global trade war and potential recession. The semiconductor industry, being highly globalized and reliant on complex international supply chains, was particularly vulnerable. The market reacted sharply, with semiconductor equipment stocks experiencing substantial declines.

Watch Tariff-Driven Turmoil Drags Stocks to Multiyear Lows | Bloomberg: The Close 04/04/2025 - Bloomberg

Tariffs Won’t Stop Companies Buying ASML’s Machines—Heard on the Street

📈 Partial Recovery: Resilience Amid Challenges

Despite the challenges, semiconductor equipment stocks have shown signs of recovery in the subsequent weeks. Several factors have contributed to this partial rebound:

- Strong Earnings Reports: Companies like Cadence Design Systems reported robust earnings, indicating resilience in certain segments of the semiconductor industry.
- Continued AI Demand: The ongoing demand for AI-related technologies has provided support to the semiconductor sector, with companies like ASM International projecting sales growth driven by AI chip demand.
- Tariff Exemptions: The exemption of semiconductor equipment from certain tariffs has alleviated some immediate pressures on the industry, allowing for cautious optimism among investors.

While uncertainties remain, particularly concerning global trade policies and geopolitical tensions, the semiconductor equipment sector has demonstrated a degree of resilience, adapting to the evolving landscape and capitalizing on areas of sustained demand.

Wednesday, April 16, 2025

ASML Posts Strong Q1 2025 Results Amid AI-Driven Demand and Tariff Uncertainty

ASML kicked off 2025 with solid first-quarter performance, beating expectations on both earnings and revenue as demand for advanced lithography tools—driven by AI and next-generation semiconductor nodes—remained robust. While the company reaffirmed its growth outlook for 2025 and 2026, it also flagged increasing geopolitical uncertainty, particularly around US-China tariffs, as a risk factor for the months ahead.

ASML delivered strong Q1 2025 results, with earnings per share of $6.82 and revenue of $8.80 billion, reflecting a 56% year-over-year increase. The company met or exceeded guidance across major financial metrics, with gross margins at 54%, supported by favorable EUV system configurations and higher average selling prices. Net system sales reached €5.7 billion—€3.2 billion from EUV and €2.5 billion from non-EUV—while Installed Base Management sales added €2 billion. Bookings totaled €3.9 billion, mostly from logic customers. Despite a seasonal dip in free cash flow due to payment timing and capital investments, ASML remains financially strong with €9.1 billion in cash.


CEO Christophe Fouquet and CFO Roger Dassen emphasized the ongoing strength of AI as a demand driver, particularly in advanced logic and memory, while acknowledging growing macroeconomic and geopolitical uncertainties—especially around tariffs. They reiterated revenue expectations for 2025 between €30 billion and €35 billion, with 2026 also anticipated to be a growth year. However, they cautioned that new tariff dynamics introduce significant unknowns for both ASML and its customers, which may affect gross margins and the broader supply chain.


On the technology front, ASML made progress with both its Low NA and High NA EUV systems. The NXE:3800E tool is now shipping at full spec and is seeing strong adoption among logic and memory customers aiming for single-expose EUV. Meanwhile, the High NA NXE:5000 has demonstrated better maturity compared to the Low NA at a similar stage, with customers like Intel and Samsung reporting substantial gains in productivity and process simplification. ASML shipped its fifth NXE:5000 in Q1 and is beginning shipments of the NXE:5200, which will be critical for phase two customer evaluations. Full-scale adoption is expected from 2026–2028, contributing to ASML’s long-term revenue forecast of €44 billion to €60 billion by 2030.

ASML addressed growing concerns over US and China tariffs, highlighting the high level of uncertainty surrounding their scope and impact. The company is actively assessing both direct and indirect consequences, including tariffs on system sales, parts imports, and servicing operations. ASML emphasized that it is working closely with customers and suppliers to mitigate disruptions and ensure that tariff-related costs are fairly distributed across the value chain, rather than being absorbed solely by ASML. While management acknowledged that these discussions are still evolving and outcomes remain unclear, they cautioned that tariffs could introduce volatility in margins, supply chain planning, and customer delivery schedules. Despite this, ASML noted that the current business conversations with customers remain unchanged and the long-term strategic investment momentum—especially in logic and AI-related capacity—appears resilient.

Sources:

ASML Holding N.V. 2025 Q1 - Results - Earnings Call Presentation (NASDAQ:ASML) | Seeking Alpha

ASML Holding N.V. (ASML) Q1 2025 Earnings Call Transcript | Seeking Alpha

Applied Materials Unveils Industry-First Ruthenium-Cobalt Liner and Next-Gen Dielectrics to Enable 2nm Chip Wiring and Boost 3D Stacking for Energy-Efficient AI Computing

Applied Materials has announced new materials engineering breakthroughs aimed at improving energy efficiency in computing by enabling copper wiring to scale down to the 2nm node and beyond. Central to this innovation is the industry’s first high-volume use of ruthenium in a binary metal liner with cobalt (RuCo), which allows for thinner liners, improved copper fill, and up to 25% lower electrical resistance. This innovation, part of the new Endura™ Copper Barrier Seed IMS™ system, combines six process technologies in one high-vacuum system and is already being adopted by major logic chipmakers. These advances address the increasing challenges of interconnect resistance and mechanical weakness as chip feature sizes shrink.


Applied Materials’ new Endura™ Copper Barrier Seed IMS™ with Volta™ Ruthenium CVD combines six different technologies in one high-vacuum system, including an industry-first combination of materials that enables chipmakers to scale copper wiring to the 2nm node and beyond.

Complementing this, Applied also introduced an enhanced version of its long-standing Black Diamond™ low-k dielectric material, designed to reduce capacitance and reinforce chip strength — critical for advanced 3D stacking in logic and memory chips. These solutions help overcome scaling limitations associated with Moore’s Law and are critical for sustaining AI-driven computing advancements. As demand for high-performance, energy-efficient chips grows, Applied’s innovations are expanding its served market for interconnect technologies, which is projected to reach $7 billion per 100K wafer starts per month with the addition of backside power delivery.



With the semiconductor industry’s first use of ruthenium in high-volume production, Applied Materials' new binary metal combination of ruthenium and cobalt (RuCo) enables copper chip wiring to be scaled to the 2nm node and beyond and reduces electrical line resistance by as much as 25 percent.


Applied Materials today introduced an enhanced version of the company’s Producer™ Black Diamond™ PECVD dielectric film. This new material enables chip scaling to 2nm and below, while offering increased mechanical strength to help take 3D logic and memory stacking to new heights.



The new Producer™ Enhanced Black Diamond™ dielectric is a revolutionary product, enabling next-generation chips of the AI era. Enhanced Black Diamond™ addresses two key issues in leading-edge chips. As wires become closer together, parasitic capacitance increases. The phenomenon slows signals down, worsening performance and energy consumption. Additionally, damaging plasma manufacturing processes can cause the thinner insulating dielectric material between wires to fracture or collapse, potentially leading to chip failure (Embedded from Youtube : https://youtu.be/uJju9KNA-yE?si=ae-Eqc0Qaf5J8e0W).

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Photos accompanying this announcement are available at



Thursday, April 10, 2025

AlixLabs to Demonstrate APS™ on 300-millimeter UMC wafers at the 2025 CMC Conference

Atomic Layer Etching Pitch Splitting (APS) proven on more industry-leading wafers, doubling fin density and proving flexibility without EUV.

Austin, TX, USA/Stockholm, Sweden – April 10th, 2025 – AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching (ALE), today demonstrates the latest in its line of groundbreaking development in advanced chip fabrication unveiling additional research into its novel semiconductor manufacturing process known as APS™ (Atomic Layer Etching Pitch Splitting) capable of doubling fin density while introducing the unprecedented flexibility to vary pitch and critical dimensions within the same wafer area.


Proven on 300-millimeter wafers provided by United Microelectronics Corporation (UMC), the APS™ technology successfully halved pitch compared to current industry benchmarks. This significant advancement was achieved entirely without relying on expensive and energy-intensive Extreme Ultraviolet (EUV) lithography.

Instead, APS™ leverages advanced etching techniques that substantially enhance sustainability, drastically reducing energy consumption without compromising throughput. Previous demonstrations of the APS™ process, validated through Intel’s Test Vehicle Program[1], confirmed its potential by achieving metal pitches as small as 25 nanometers.


“Today we are sharing more proof that the APS™ process can be a game changer for leading foundries. Thanks to UMC, we have been able to verify our process on production wafers that are shipped in quantities measured in millions of wafers annually,” said Dr. Robin Athle, Principal Researcher at AlixLabs. “Our mission is to create equipment that allows companies that don’t have access to EUV tools to scale down their production to 5 nanometer and beyond. By eliminating the dependency on EUV lithography, we are offering the industry a path towards more sustainable and economically feasible high-density chip production.”

Detailed results from AlixLabs’ UMC wafer tests and further insights into APS™ technology will be presented at the 2025 CMC Conference, scheduled for April 10th in Austin, Texas. Dr. Athle’s presentation “Atomic Layer Etching Pitch Splitting (APS™): a New Alternative to Multi Patterning” will be held at 4:00 PM at the Bergstrom Ballroom in Hilton Austin Airport Hotel.

Sunday, April 6, 2025

Semiconductor Equipment Not Listed in Tariff Exemptions and EU and Japanese Suppliers Show Market Resilience

As of April 6, 2025, semiconductor equipment is not explicitly included in the list of exempted products under the U.S. tariffs detailed in Annex II of President Donald Trump’s executive order. While semiconductors and electronic components such as integrated circuits and diodes are covered, the exemption does not extend to manufacturing equipment.


Since the April 2, 2025 tariff announcement, ASML’s stock fell about 9.5%, showing more resilience than the Philadelphia Semiconductor Index (SOX), which dropped approximately 16.7% (deepest point).

Semiconductor equipment not listed in tariff exemptions, but EU and Japanese suppliers show market resilience

Despite this, European and Japanese semiconductor equipment companies have shown relative resilience in the wake of the April 2 tariff announcement. ASML, the Netherlands-based manufacturer of advanced lithography tools, saw its stock fall by about 9.5 percent, compared to a sharper 16.7 percent drop at the lowest point for the Philadelphia Semiconductor Index (SOX). This suggests continued investor confidence in ASML’s position and the essential nature of its equipment in semiconductor manufacturing.



Other global equipment firms also experienced moderate declines. ASM International, also from the Netherlands, saw an 8.3 percent drop. Tokyo Electron, Japan’s leading chip tool supplier, declined by 8.1 percent. In contrast, US-based companies faced more significant losses: Applied Materials dropped 14.1 percent, Lam Research fell 19.9 percent, and KLA Corporation declined by 16 percent between April 2 and April 4.

The broader tariff policy applies a 10 percent baseline rate on most imports starting April 5, with higher rates—up to 50 percent—for goods from 83 countries (including EU members) beginning April 9. Annex II outlines exemptions across multiple sectors: critical minerals, pharmaceuticals, energy products, integrated circuits, and fertilizers. However, semiconductor manufacturing equipment is not among the listed exemptions, indicating it remains subject to the new tariffs unless otherwise specified in future regulatory clarifications.

Despite this, the muted market response for EU and Japanese equipment makers highlights their global significance and the likelihood that US firms will continue to source vital tools from these suppliers, tariffs notwithstanding.

Background:

Starting on April 5, a 10% baseline tariff will be applied to nearly all products from all countries, with a few notable exceptions explained later. The executive order’s Annex I lists 57 countries (83 when accounting for all European Union member states) that will face higher tariffs of up to 50%, which go into effect on April 9. The new tariffs will stack on previous product-specific tariff rates. As a reminder, a tariff is a tax paid at the border by an importer seeking to bring products into the United States from a foreign country.

The exempted items in Annex II include, but are not limited to: copper, pharmaceuticals, semiconductors, lumber articles, certain critical minerals, energy/energy products, and products facing section 232 tariffs from the current administration (steel, aluminum, automobiles and any future section 232 investigations). While some of these industries were exempted due to their important roles in the economy (energy and critical minerals), others were excluded as they are a target for future restrictions (copper, lumber, pharmaceuticals and semiconductors).

Annex II lists a range of products exempted from trade actions, categorized across several sectors. It includes critical minerals and ores, such as copper, cobalt, lithium, tungsten, manganese, rare-earth elements, and graphite.

It also covers a wide array of chemicals and industrial compounds, including hydrofluoric acid, titanium dioxide, aluminum oxide, and various oxides, chlorides, and sulfates.

A significant portion of the list includes energy products, such as crude oil, natural gas (liquefied and gaseous), coal, petroleum derivatives, lubricants, and electricity.

The Annex lists several electronic components, including integrated circuits (processors, memory, amplifiers, other ICs), semiconductor devices (diodes, transistors, thyristors, optical isolators), and parts for these devices.
In agriculture, exempted products include fertilizers containing potash and NPK compounds, peat, and veterinary vaccines.

The document also includes many pharmaceuticals and medical products, such as antibiotics, hormones, vitamins, vaccines, and active pharmaceutical ingredients (APIs), along with cell therapy products and clinical trial materials.

There are exemptions for polymers and plastics in primary forms, including polyethylene, polypropylene, PTFE, silicones, and epoxide resins.


Additionally, doped materials for electronics, such as silicon wafers (HTS 38180000), and pigments and colorants like titanium dioxide and copper phthalocyanine, are listed.


Monday, February 10, 2025

AlixLabs Demonstrates 3 nanometers on Intel Silicon – Without EUV

The Swedish semiconductor company has fabricated leading-edge structures without using complex and costly lithography techniques.

The Swedish semiconductor company AlixLabs announces that it has used its technology to etch structures equivalent to commercial 3-nanometer circuits on Intel test silicon. Notably, this has been achieved without the use of extreme ultraviolet lithography (EUV) or advanced multi-patterning techniques such as SADP and SAQP (Self-Aligned Double Patterning and Self-Aligned Quad Patterning, respectively).


AlixLabs, a startup based in Lund, specializes in the development of Atomic Layer Etching (ALE), a type of plasma-based dry etching for cutting-edge structures, and ALE Pitch Splitting (APS), which enables transistor fins to be split using etching. The advantage of this approach is that it significantly reduces costs at the cutting edge, where wafer prices skyrocket with each new generation.

"We are pleased to demonstrate how APS can help the industry reduce its dependence on multi-patterning while lowering costs and environmental impact. Our technology enables the fabrication of sub-10-nanometer structures on silicon, and through Intel’s Test Vehicle Program, we have proven that sub-5-nanometer structures can be achieved using etching alone."
– Dmitry Suyatin, CTO and Co-Founder of AlixLabs

According to Dmitry Suyatin, AlixLabs’ CTO, this demonstration was made possible through Intel’s Test Vehicle Program, which provided test silicon for AlixLabs to process with its APS technology. While ALE has traditionally been limited to structures in the 10-nanometer class, AlixLabs' APS technique has significantly simplified the manufacturing of structures smaller than 5 nanometers.

Etching 3-nanometer-class structures without advanced EUV lithography, using only immersion lithography, is a significant breakthrough—provided the technology can be scaled and applied in practical manufacturing. AlixLabs has previously stated its goal of seeing its technology adopted by TSMC and Samsung for their 2-nanometer processes.


Since the industry moved past the 28-nanometer node, multi-patterning has become increasingly necessary to create smaller structures and transistors. This lithographic technique involves breaking down complex patterns into simpler ones and sequentially patterning them onto the silicon wafer for higher precision and detail. Lithography can perform this in two, three, or four steps (SADP, SAQP), though more steps are theoretically possible, they are considered too complex and costly for practical use at smaller nodes.

"APS technology demonstrates that complex multi-patterning techniques such as SADP and SAQP are not needed to manufacture circuits at 5 nanometers and below. This increases the potential to use immersion lithography for critical mask layers in 3-nanometer processes. These results were achieved with our early Alpha equipment, and Beta equipment will follow later in 2025. We thank Intel for enabling this demonstration and providing high-quality test silicon."
– Jonas Sundqvist, CEO and Co-Founder of AlixLabs

While lithographic multi-patterning is often necessary, it comes with several downsides. Each additional step requires more masks, which must be precisely aligned to form the final, complex pattern. Even a slight misalignment can lower yield and performance, but more importantly, it significantly extends production time. Avoiding multi-patterning whenever possible is therefore always preferable.

It is essential to distinguish between "nanometer-class" structures and actual physical nanometer measurements. What AlixLabs has achieved is a metal pitch (the distance between metal interconnects connecting transistor gates) of 25 nanometers through dry etching. This compares to TSMC’s most advanced 3-nanometer process, which achieves a metal pitch as low as 23 nanometers in certain high-density configurations.

AlixLabs highlights this test silicon as a major milestone towards commercialization and announces that more updates will follow later in 2025. Additional details will be presented by CTO Dmitry Suyatin at SPIE Advanced Lithography + Patterning in San Jose, California, on February 27, from 9:00–9:20 AM (local time).

Sources:

AlixLabs demonsterar 3 nanometer på Intel-kisel – utan EUV – Semi14

AlixLabs to Showcase Latest APS™ Findings at SPIE Advanced Lithography + Patterning – AlixLabs

Browse the 2025 program for SPIE Advanced Lithography + Patterning


Saturday, January 18, 2025

Revolutionizing Silicon Photonics: First Electrically Pumped Group IV Laser Achieved for Seamless Integration on Silicon Chips

Researchers have achieved a groundbreaking milestone in silicon photonics by developing the first electrically pumped Group IV laser, made from silicon-germanium-tin layers directly grown on silicon wafers. This innovation paves the way for cost-effective, energy-efficient photonic integrated circuits in next-gen silicon chips.


The breakthrough in silicon photonics achieved by an international research team marks a transformative step in the materials and manufacturability of photonic devices. By developing the first electrically pumped continuous-wave laser made entirely of Group IV materials—silicon, germanium, and tin—the researchers overcame a long-standing challenge in integrating efficient light sources directly into silicon-based technologies. This laser is built using ultrathin layers of silicon-germanium-tin and germanium-tin, grown directly on silicon wafers. Its compatibility with conventional CMOS processes promises seamless integration into existing silicon manufacturing workflows, reducing costs and enhancing scalability. Unlike traditional lasers based on III-V materials, which are costly and complex to integrate with silicon, this innovation makes use of widely available Group IV elements, providing an energy-efficient and manufacturable solution for on-chip photonics.

This laser not only operates with a low current of 5 milliamperes at 2 volts but also features a sophisticated multi-quantum well structure and ring geometry to minimize power consumption and heat generation. Though the device currently functions at cryogenic temperatures, its development path mirrors earlier advancements in germanium-tin lasers that achieved room-temperature operation within a few years. The laser’s manufacturability is further underscored by its growth on standard silicon wafers, aligning with industry-standard processes. This achievement is poised to catalyze the adoption of low-cost photonic integrated circuits (PICs) in microchips, meeting the growing demand for energy-efficient hardware in AI and IoT applications while paving the way for advances in optical data transmission and next-generation silicon photonics.

Sources:

Silicon Photonics Breakthrough: The “Last Missing Piece” Now a Reality

Wednesday, January 8, 2025

SEMI World Fab Forecast Highlights Strong Fab Investments and New Fabs in 2025

The latest World Fab Forecast by SEMI, published on December 19, 2024, highlights strong growth in global semiconductor manufacturing from 2023 to 2025. Key takeaways from the report include increased investments in fab equipment and capacity expansions across both memory and foundry segments, indicating a resilient and growing industry.


SEMI’s latest World Fab Forecast report reveals that 18 new semiconductor fabs will begin construction in 2025, including three 200mm and fifteen 300mm facilities, primarily in the Americas, Japan, China, and Europe. These projects, set to start operations between 2026 and 2027, reflect the industry's focus on advanced nodes for AI and high-performance computing (HPC). Total semiconductor capacity is expected to grow at a 6.6% annual rate, driven by leading-edge logic technologies, while mainstream and mature nodes continue to support automotive, IoT, and power applications. Foundries remain key drivers of capacity growth, with generative AI demand boosting memory markets, particularly high-bandwidth memory (HBM). [Semiconductor Digest, LINK below]

For 2024, global fab equipment spending is projected to rise by 8% year-over-year to approximately 111 billion dollars, surpassing previous projections. The foundry segment is expected to account for 59 billion dollars of this investment, marking a 2% increase from 2023. The memory segment is set to see the most significant growth, with spending projected to jump by 50% to 34 billion dollars. This surge in memory investments reflects a rebound from the recent downturn and aligns with rising demand for advanced semiconductor technologies.

Looking ahead to 2025, fab equipment spending is expected to grow by an additional 4%, reaching approximately 116 billion dollars. The foundry segment will likely invest around 65 billion dollars, while the memory segment is forecasted to maintain robust spending at 33 billion dollars.

In terms of capacity expansion, the report predicts continued growth in both memory and foundry capacity. Memory capacity is expected to grow by 4% in 2024 and 3% in 2025, while foundry capacity, including pure-play foundries and IDM fabs, is projected to see 12% growth in 2024 and 11% in 2025. This reflects strong demand for advanced logic chips and specialty processes.

On the construction front, investments in new fab construction are expected to dip slightly in 2024, with a 5% decline to 39 billion dollars. However, SEMI anticipates 45 new construction projects for volume fabs, excluding R&D and pilot facilities, between 2025 and 2030. These projects are expected to support long-term demand growth across various segments, including AI chips, automotive semiconductors, and memory.

In 2025, the industry is expected to see the completion of several new fabs that are currently under construction. These new fabs will be crucial for meeting growing demand for advanced semiconductor technologies and are expected to bring significant additional capacity online. Many of these facilities will focus on next-generation nodes, particularly for applications in AI, high-performance computing, and automotive sectors. The report highlights that regions such as Taiwan, South Korea, and the US will see major investments in these new fabs, further strengthening their positions as key players in the global semiconductor supply chain.

Sources:

For more details, visit the official SEMI World Fab Forecast page:

Semiconductor Digest:

Saturday, December 14, 2024

Intel Unveils 6 nm Gate Length Silicon RibbonFET CMOS and Breakthroughs in Semiconductor Scaling at IEDM 2024

Intel Corporation / Intel Foundry has demonstrated and extensively characterized gate-all-around Silicon RibbonFET CMOS transistors with a 6 nm gate length (LG). The study showcases nanoribbon silicon thickness (Tsi) scaling down to 3 nm, enhancing short-channel effects without compromising performance. Effective workfunction engineering mitigates threshold voltage increases caused by quantum confinement at scaled Tsi, enabling reduced threshold voltage at highly scaled gate lengths. Injection velocity of 1.13x10^7 cm/s is maintained at LG=6nm without degradation down to Tsi=3 nm, highlighting advancements crucial for continued gate length scaling and the ongoing realization of Moore's Law.


Intel Foundry made groundbreaking announcements at the IEEE International Electron Devices Meeting (IEDM) 2024, showcasing advancements that propel semiconductor technology into the next decade and beyond. Highlights include innovations in transistor and interconnect scaling, advanced packaging, and emerging materials to support the industry’s roadmap toward achieving 1 trillion transistors on a chip by 2030. Intel demonstrated a 25% capacitance reduction using subtractive ruthenium for interconnections, achieved a 100x throughput improvement in advanced packaging through Selective Layer Transfer (SLT), and advanced gate-all-around (GAA) transistor scaling with Silicon RibbonFET CMOS at a 6 nm gate length. Additionally, Intel unveiled new work on gate oxide modules for scaled 2D FETs, addressing the next phase of GAA scaling.

Among the key technical breakthroughs, subtractive ruthenium stands out as a metallization alternative to copper for interconnects, offering significant capacitance reductions at tight pitches while being cost-effective and scalable for high-volume manufacturing. SLT further revolutionizes advanced packaging with ultra-fast, flexible chip-to-chip assembly, enabling smaller, higher-density chiplets for AI and other demanding applications. For transistor scaling, Intel’s demonstration of Silicon RibbonFET CMOS at 6 nm gate length delivers industry-leading short-channel effects and performance, paving the way for continued scaling under Moore’s Law. Additionally, Intel’s progress with 2D GAA NMOS and PMOS transistors and gate oxide development signals readiness for post-silicon semiconductor technologies.

Intel also highlighted progress in gallium nitride (GaN) technology, demonstrating the first 300 mm GaN-on-TRSOI substrates for high-performance power and RF electronics. These developments, alongside Intel’s continued focus on advanced memory integration, hybrid bonding, and modular system expansion, underscore its commitment to addressing challenges in AI, energy efficiency, and thermal management. With these innovations, Intel Foundry continues to lead the charge in semiconductor advancements, ensuring a robust path forward for the trillion-transistor era.

Source: Intel IEDM 2024 Innovations


Saturday, December 7, 2024

Decoupling from Dependence: The Global Semiconductor Industry Races to Diversify Amid Geopolitical Risks

The semiconductor industry is at a critical juncture, driven by the dual pressures of rising demand for advanced chips in artificial intelligence (AI) and the urgent need to mitigate geopolitical vulnerabilities. With Taiwan’s fabs, particularly TSMC, supplying over 90% of the world’s cutting-edge semiconductors, nations are rapidly investing in new fabs to reduce reliance on both Taiwan and China. While TSMC, Samsung, and Intel lead efforts to expand capacity in regions like the US, Europe, and Japan, these initiatives fall short of replacing Taiwan’s unparalleled output of 2 nm and below chips by 2030. Simultaneously, China’s struggle to compete at leading-edge nodes, compounded by export restrictions on critical tools, further underscores the fragility of the global semiconductor supply chain. These dynamics signal a transformative era as the free world works to establish more resilient and geographically diversified semiconductor ecosystems.

According to a recent article by FT (Source), the primary drivers for 2 nm technology development are the surging demand for custom and specialized chips, particularly in artificial intelligence (AI), and the need to create competitive alternatives to current large-scale semiconductor manufacturers. Rapidus, for instance, is targeting a niche in the AI market by producing bespoke chips that prioritize efficiency and can outperform more generic chips, such as those produced by Nvidia, in specific applications.

The motivation also includes addressing capacity limitations from dominant players like TSMC, which prioritizes large orders. Rapidus sees an opportunity to capture smaller customers who are willing to pay a premium for speed and customization. Additionally, geopolitical factors are influencing the push for advanced technology, with Japan aiming to reduce reliance on Taiwan's semiconductor manufacturing expertise and establish its own ecosystem for leading-edge production. 

This is why the semiconductor industry is advancing rapidly toward 3 nm and 2 nm process nodes, with leading players outlining production timelines and capacity expansions over the next five years. Below is a detailed overview of these developments, including plans from TSMC, Samsung, Intel, and Rapidus.


The forecast predicts a 540% growth in the global AI semiconductor market between 2020 and 2030, driven by increasing adoption across key segments such as servers, networking, edge devices, and PCs/smartphones. Servers are projected to dominate the market, reflecting the growing demand for AI in data centers and cloud computing, while networking and edge computing are expected to see rapid expansion, driven by real-time processing needs in IoT and automotive applications. Moderate growth is anticipated in the PCs/smartphone segment as AI integration in consumer electronics continues. Tokyo’s recent $65 billion investment in AI and semiconductor industries underscores the importance of this market, which is expected to exceed $400 billion by 2030, highlighting the transformative role of semiconductors in powering AI advancements across industries.

TSMC

Taiwan Semiconductor Manufacturing Company (TSMC) is enhancing its semiconductor fabrication capabilities globally, focusing on 3 nm and 2 nm and below nodes.

  • 3 nm Production (Taiwan): TSMC began volume production of its 3 nm process technology in December 2022 at Fab 18, located in the Southern Taiwan Science Park (STSP). Fab 18 consists of eight phases, each featuring a cleanroom area of 58,000 square meters, roughly double the size of a standard logic fab. TSMC has invested over NT$1.86 trillion in Fab 18, creating more than 11,300 high-tech jobs.

  • 2 nm Development (Taiwan): TSMC’s 2 nm process is scheduled for risk production in late 2024 and mass production in 2025. A new facility in Hsinchu Science Park is under construction, with equipment installation set for April 2024.

  • 2 nm (Arizona, USA): TSMC is building a second fab in Arizona to produce 2 nm nodes, with production expected to begin in 2028. A third fab, focused on cutting-edge technologies, is planned for later this decade. This is part of a $40 billion investment, the largest foreign investment in Arizona's history.

Samsung

Samsung Electronics is expanding its semiconductor manufacturing capabilities in South Korea and the United States, focusing on 3 nm and 2 nm nodes.

  • 3 nm Production (South Korea): Samsung began mass production of its first-generation 3 nm chips in the second half of 2022, using its proprietary Multi-Bridge Channel Field-Effect Transistor (MBCFET) technology, a Gate-All-Around (GAA) architecture. Second-generation 3 nm production began in 2023, offering improved energy efficiency and performance.

  • 2 nm Development (South Korea): Samsung plans to start 2 nm production in 2025 for mobile devices, followed by high-performance computing in 2026 and automotive semiconductors by 2027. The 2 nm (SF2) process is expected to deliver a 12% performance increase, 25% power efficiency improvement, and 5% area reduction compared to 3 nm.

  • Taylor Fab (Texas, USA): Samsung is constructing a $17 billion fab in Taylor, Texas. Initially planned for 4 nm production in late 2024, the fab may start directly with 2 nm technology in 2026 to align with Samsung’s broader roadmap.

Intel

Intel Corporation is investing in global semiconductor manufacturing, focusing on advanced nodes like Intel 3, Intel 20A, and Intel 18A.

  • United States: Intel’s Fab 42 in Arizona produces 10 nm chips and is transitioning to Intel 7 and Intel 4 nodes. In Ohio, Intel is building two fabs with a $20 billion investment to produce Intel 18A by the decade's end.

  • Europe: Intel’s Fab 34 in Ireland will produce Intel 4 technology using EUV lithography. In Germany, Intel delayed its is investing €17 billion to construct two fabs in Magdeburg, focusing on advanced nodes.

  • Israel: Intel’s Fab 28 in Kiryat Gat, Israel, is transitioning from 10 nm to Intel 7 and Intel 4 processes. Intel has committed $10 billion to expand this facility.

Rapidus

Rapidus, a Japanese semiconductor start-up, aims to produce 2 nm chips, positioning itself as a significant player in the advanced semiconductor market.

  • 2 nm Development: Rapidus plans to start trial production of 2 nm chips in April 2025, with mass production by 2027. The company is collaborating with IBM to integrate cutting-edge technology, including Extreme Ultraviolet (EUV) lithography.

  • Manufacturing Facilities: Rapidus is building its IIM-1 fab in Chitose City, Hokkaido, Japan. The first EUV machine from ASML is expected to arrive in mid-December 2024.

  • Strategic Approach: Rapidus is rethinking traditional manufacturing models by emphasizing smaller batch production with faster cycle times, aiming for greater efficiency and adaptability.

SMIC

China’s stake in leading-edge semiconductor manufacturing and AI is hindered by significant technological and geopolitical challenges. While domestic efforts, such as those by SMIC, have made strides in producing 7 nm chips, China remains far behind global leaders like TSMC, Samsung, and Intel, who are advancing toward 2 nm production. Critical dependencies on foreign equipment, such as ASML's EUV lithography machines, and U.S.-led export restrictions on advanced semiconductor tools and high-performance GPUs have further constrained its progress. Although China has invested heavily in AI development, its capabilities remain primarily focused on practical applications like surveillance and automation rather than leading innovation in foundational AI technologies. To conclude, China has an uphill battle to compete in the global semiconductor and AI industries.

Is the free world Decoupling from China and future risk of relying on Taiwan Fabs?

The global semiconductor industry is undergoing significant restructuring as it increasingly decouples from China and prepares for potential decoupling from Taiwan’s fabs. Geopolitical tensions, driven by concerns over China's ambitions toward Taiwan and its own restricted access to advanced chip-making technologies, have accelerated efforts by the US, Europe, and their allies to diversify supply chains and reduce dependency on both regions. Export controls targeting China, including restrictions on advanced chips and manufacturing tools, have prompted heavy investments in domestic semiconductor manufacturing in the US, Japan, South Korea, and Europe. Simultaneously, Taiwan’s pivotal role in leading-edge semiconductor production, dominated by TSMC, has highlighted vulnerabilities, spurring new fabs outside the island, such as TSMC’s facilities in Arizona and Samsung’s in Texas. These shifts reflect a broader trend toward creating more resilient, geographically dispersed semiconductor ecosystems that mitigate risks associated with reliance on any single region for critical technologies.

Current global plans for semiconductor manufacturing expansion aim to reduce dependency on Taiwan but fall short of ensuring sufficient non-Taiwan capacity for 2 nm and below nodes in the near term. Taiwan, led by TSMC, still dominates leading-edge semiconductor production, supplying over 90% of the world’s advanced chips. While significant investments are underway—such as TSMC's Arizona fabs, Samsung’s expansions in South Korea and Texas, and Intel's facilities in the US, Europe, and Israel—these efforts are unlikely to match Taiwan’s scale and technological leadership at 2 nm and below by 2027-2030.

For example, TSMC’s planned Arizona fab is projected to produce 2 nm chips by 2028, but its capacity will be a fraction of TSMC's output in Taiwan. Similarly, Samsung and Intel are progressing toward advanced nodes, but both face challenges in matching TSMC’s efficiency and yield at these cutting-edge technologies. Additionally, the complexity of EUV lithography and the industry's high R&D costs further limit the pace at which non-Taiwan fabs can scale to competitive capacities.