Global Semiconductor Sales See Mixed Trends: Monthly Rise Amid Annual Decline

Global semiconductor sales rose 1.9% in September 2023 from August, but fell 4.5% from September 2022. Q3 sales reached $134.7 billion, up 6.3% from Q2 but down 4.5% from Q3 the previous year. Sales reflect positive momentum with a strong long-term demand outlook. Increases were seen in all regions except Japan.

WASHINGTON—Nov. 1, 2023—The Semiconductor Industry Association (SIA) today announced global semiconductor sales for the month of September 2023 increased 1.9% compared to August 2023 and fell 4.5% compared to September 2022. Worldwide sales of semiconductors totaled $134.7 billion during the third quarter of 2023, an increase of 6.3% compared to the second quarter of 2023 and down 4.5% compared to the third quarter of 2022. Monthly sales are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. SIA represents 99% of the U.S. semiconductor industry by revenue and nearly two-thirds of non-U.S. chip firms.

“Global semiconductor sales increased on a month-to-month basis for the seventh consecutive time in September, reinforcing the positive momentum the chip market has experienced during the middle part of this year,” said John Neuffer, SIA president and CEO. “The long-term outlook for semiconductor demand remains strong, with chips enabling countless products the world depends on and giving rise to new, transformative technologies of the future.”

Regionally, month-to-month sales increased in Asia Pacific/All Other (3.4%), Europe (3.0%), the Americas (2.4%), and China (0.5%), but decreased slightly in Japan (-0.2%). Year-to-year sales increased in Europe (6.7%), but decreased in the Americas (-2.0%), Japan (-3.6%), Asia Pacific/All Other (-5.6%) and China (-9.4%).

For comprehensive monthly semiconductor sales data and detailed WSTS forecasts, consider purchasing the WSTS Subscription Package. For detailed historical information about the global semiconductor industry and market, consider ordering the SIA Databook.

Atlas Copco to Bolster Semiconductor Portfolio with Acquisition of South Korean Vacuum Valve Company, Presys Co., Ltd.

• Atlas Copco set to acquire South Korean vacuum valve producer, Presys Co., Ltd.
• Presys reported a revenue of MKRW 35,000 in 2022 and has a workforce of 134.
• The deal, pending regulatory approval, is anticipated to close in Q1 2024.

Swedish firm Atlas Copco has announced its intention to purchase Presys Co., Ltd, a South Korean manufacturer of vacuum valves primarily for the semiconductor sector. Located in Suwon, Presys reported 2022 revenues of MKRW 35,000 (equivalent to SEK 275 million). Geert Follens, the Business Area President of Vacuum Technique at Atlas Copco, highlighted that Presys' offerings will enhance their existing semiconductor product range. Although the transaction amount remains undisclosed, it awaits regulatory nods and is slated for completion by early 2024. Upon finalization, Presys will be integrated into Atlas Copco's Semiconductor Chamber Solutions Division within the Vacuum Technique Business Area.

Presys customers, with focus on Asia.

Sources: 

프리시스(주) (gabia.io)

Atlas Copco to acquire Presys (evertiq.com)

TSMC To Report Breakthrough in NMOS Nanosheets Using Ultra-Thin MoS2 Channels at IEDM 2023

A TSMC-led research team, in collaboration with National Yang Ming Chiao Tung University and National Applied Research Laboratories, has unveiled promising results for using ultra-thin transition metal dichalcogenides (TMDs), specifically MoS2, as the channel material in NMOS nanosheets. Their innovative approach deviates from the conventional method of thinning Si channels. The team's devices exhibited impressive performance metrics: a positive threshold voltage (VTH) of ~1.0 V, a high on-current of ~370 µA/µm at VDS = 1 V, a large on/off ratio of 1E8, and a low contact resistance ranging between 0.37-0.58 kΩ-µm. These outcomes were primarily attributed to the introduction of a novel C-shaped wrap-around contact, which enhances contact area, and an optimized gate stack. While the devices demonstrated satisfactory mechanical stability, a challenge remains in addressing defect creation within the MoS2 channels. This groundbreaking study, titled "Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact" by Y-Y Chung et al., is a pivotal step forward in nanosheet scaling using TMDs.

ALD is a the technique for the precise and uniform synthesis of MoS₂, especially for semiconductor applications on large-scale wafers. The choice of precursors plays a crucial role in achieving optimal deposition characteristics. Mo (CO) 6 and H2S have been identified as the primary precursors for depositing molybdenum and sulfur components, respectively. These precursors have demonstrated the capacity for self-limiting growth behavior within a specific ALD temperature window, leading to uniform MoS₂ layers. Notably, this process has been successfully scaled up to achieve highly uniform film growth on large 300 mm SiO2/Si wafers, marking its potential for industry-level manufacturing. The ability to maintain uniformity and thickness control on such wafers emphasizes the potential of ALD in integrating MoS₂ into next-generation electronic devices and further underscores the significance of selecting appropriate precursors for optimal deposition outcomes. Other precursors have been investigated. MoCl₅ and MoF₆ serve as alternative molybdenum sources. For the sulfur component, H₂S is commonly paired with molybdenum precursors, but (CH₃)₂S has also been explored. The choice of these precursors directly impacts the properties of the resulting MoS₂ film in the ALD process and therefore precursor development for 2D MoS2 is a hot field of ongoing research.

While deposition methods are abundant, etching processes are comparatively scarce. Recent research by Elton Graugnard et al also introduces a thermal Atomic Layer Etching (ALE) technique for MoS2, leveraging MoF6 for fluorination, alternated with H2O exposures, to etch both crystalline and amorphous MoS2 films. This process has been characterized using various analytical techniques like QCM, FTIR, and QMS. The etching is temperature-dependent, with a significant increase in mass change per cycle as temperature rises. The mechanism involves two-stage oxidation of Mo, producing volatile byproducts. The resultant etch rates were established for different films, and post-etch annealing rendered crystalline MoS2 films. The thermal MoS2 ALE introduces a promising low-temperature method for embedding MoS2 films in large-scale device manufacturing.

Chem. Mater. 2023, 35, 3, 927-936

Sources:

 https://www.ieee-iedm.org/press-kit

https://pubs.acs.org/doi/10.1021/acs.chemmater.2c02549

Hamas' Brutal Attacks on Israel Could Disrupt Global Tech Supply Chain and Intel's Expansion Plans

The escalating Israel-Hamas war, after Hamas brutal attack on Israel and innocent civilians, is affecting the global tech sector. Many professionals, including top executives, are now serving as reservists in the Israel Defense Forces, as highlighted by EPSNews. Intel, a major private employer in Israel, along with other tech giants like Nvidia, Apple, Amazon, and Microsoft, faces potential disruptions, especially with facilities near conflict zones. The blockade in Gaza and transportation interruptions further strain the supply chain, emphasizing the tech industry's vulnerability to geopolitical challenges.

Intel factory in Kiryat Gat, employing about 5000 workers, which manufactures computer chips (wWikipedia), Location of Intel Fabs in Israel (Google)

Kiryat Gat, situated in Israel's Southern District, is known for Intel's semiconductor fabrication plants, including Fab 28 and the upcoming Fab 38. Founded in 1954, the city has grown significantly due to Jewish immigration over the decades and it remains an educational hub with 25 schools serving over 10,000 students.

The Israel-Hamas conflict has intensified concerns over the global semiconductor supply chain, as CNBC reports. With Israel being a key player in chip production, the geopolitical unrest poses risks to the semiconductor industry. The recent kidnapping of an Nvidia engineer further accentuates these threats, prompting tech firms to prioritize their employees' safety in the region.

Bloomberg reported this summer of Intel Corp.'s initiative to set up a new manufacturing facility in Israel. This move is part of Intel's strategy to diversify its production sources. While details remain undisclosed, the facility will focus on wafer fabrication. Intel's CEO, Pat Gelsinger, intends to expand manufacturing bases outside Asia. The plant, expected to operate from 2027, will be located in Kiryat Gat and is seen as a significant foreign investment in Israel. This development aligns with the global shift in chip manufacturing, as seen with Intel's investment in Poland and Micron Technology's potential investment in India.

Sources: 

War in Israel to Impact Electronics Supply Chain - EPS News

Intel to Build in Israel as Chipmakers Move Beyond East Asia - Bloomberg

Israel Is an Important Link in the Global Chip Supply Chain - Bloomberg

Kiryat Gat - Wikipedia

New US Roadmap Identifies Critical Semiconductor Research Priorities

Advancing semiconductor research is essential to continued innovation in the chip industry and throughout our economy. As ever-shrinking semiconductor components face fundamental physical limits, next-gen breakthroughs are unachievable without major advancements. To help address this challenge, Semiconductor Research Corporation (SRC) today unveiled the Microelectronics and Advanced Packaging (MAPT) Roadmap, which defines critical chip research priorities and technology challenges that must be addressed to support the “seismic shifts” outlined in the Decadal Plan for Semiconductors released by SRC and SIA in January 2021.

The Decadal Plan identified five seismic shifts in the industry related to smart sensing, memory and storage, communication, security, and energy efficient computing. The MAPT Roadmap continues the spirit of the Decadal Plan and discusses how to achieve its system-level goals, outlining the implementation plan for the semiconductor industry. The fundamental research that will transform these obstacles is focused on advanced packaging, 3D integration, electronic design automation, nanoscale manufacturing, new materials, and energy-efficient computing. The MAPT Roadmap is framed around fundamental and practical limits of information and communications technology sustainability: energy sustainability, environmental sustainability, and workforce sustainability.

Federal government and private sector investments in semiconductor R&D have propelled the rapid pace of innovation in the U.S. semiconductor industry, spurring tremendous growth throughout the U.S. and global economies. Using the MAPT Roadmap as a guide, we must sustain and expand public and private investments in chip research to help unlock the transformative technologies of the future.

Source: SIA, Erik Hadland, Director of Technology Policy New Roadmap Identifies Critical Semiconductor Research Priorities - Semiconductor Industry Association (semiconductors.org)

The Semiconductor Showdown: TSMC's GAA FETs vs. Intel's RibbonFET

The semiconductor industry is witnessing a fierce competition between TSMC and Intel, as they advance transistor designs with TSMC's Gate-All-Around (GAA) FETs and Intel's RibbonFET. Atomic Layer Deposition (ALD) plays an instrumental role in crafting these intricate designs. As the race to dominate the microelectronics realm heats up, the innovations from these giants foretell a transformative phase for technology between 2024 and 2026. This article dives into their respective technologies, comparing their strategies and highlighting the future implications for the semiconductor industry.

Both TSMC and Intel are pushing the boundaries of semiconductor innovation with advanced transistor designs. TSMC's GAA (Gate-All-Around) FET (Field-Effect Transistor) technology and Intel's RibbonFET are prime examples of this evolution. ALD is crucial for GAA FET production, ensuring precision and atomically thin, conformal or on purpose non-conformal or selectively deposited films. As transistors miniaturized, ALD replaced traditional silicon dioxide gate dielectrics with high-k materials, reducing gate leakage and offering enhanced uniformity. One of the challenges in GAA FETs is accurately aligning the gate material around the channel; ALD facilitates this through self-aligned processes. Additionally, in configurations with multiple gates or nanosheets, ALD accurately deposits spacer materials, preserving the necessary separation between nanosheets. ALD also offers precise doping for GAA FETs, including NMOS and PMOS. With atomic-level control, ALD introduces dopants like phosphorus for NMOS and boron for PMOS. Given the shrinking device dimensions, ALD's precision becomes vital, especially when considering techniques like solid-state doping to achieve ultra-shallow profiles.

TSMC's Gate-All-Around (GAA) FET technology represents a significant shift from the traditional FinFET transistor design. In a GAA FET, the gate material wraps entirely around the channel, unlike the FinFET where the gate is only on three sides of a vertical fin. This complete encirclement provides enhanced control over the current flow through the channel, reducing leakage current and allowing for lower voltage operation. The result is improved energy efficiency and performance.

TSMC's roadmap to N2. (Image: TSMC)

On the other hand, Intel's RibbonFET introduces a similar gate-all-around design but with a unique twist. Instead of a traditional vertical fin, RibbonFET uses nanosheet technology, where multiple flat nano-sheets are stacked to form the channel. This design offers even better control of the current flow, leading to significant gains in performance and efficiency. RibbonFET is one of Intel's flagship innovations for its advanced nodes, emphasizing the company's commitment to reclaiming technology leadership in the semiconductor space.

Intel 20A Ribbon FET (intel.com)

In a recent article Tom´s Hardware (Anton Shilow, link below) compares the advanced semiconductor technology nodes from industry TSMC and Intel, focusing on TSMC's N3P and N2 nodes against Intel's 20A and 18A nodes. Forecasted for release between 2024 and 2026, these nodes represent the forefront of semiconductor innovation. TSMC's N3P, a 3nm-class node, is set to be available by 2025 and offers performance comparable to Intel's 18A. Interestingly, TSMC's 2nm-class N2, expected in the second half of 2025, is anticipated to outpace Intel's 18A in terms of power, performance, and area advantages. Intel's 20A, arriving in 2024, promises significant advancements by introducing RibbonFET gate-all-around transistors and a backside power delivery network. The subsequent 18A will further refine these innovations. While TSMC leans on its proven FinFET technology for the N3P, it plans to introduce nanosheet GAA transistors in the N2. 

As the semiconductor race intensifies, both companies are heavily invested in outpacing each other, with TSMC focusing on technology maturity and cost-effectiveness, and Intel aiming to regain its technology leadership. The dynamics between these tech giants will shape the semiconductor industry's future.

Comparison of Advanced Semiconductor Technology Nodes: TSMC N3P & N2 vs. Intel 20A & 18A, highlighting the competitive landscape of the semiconductor industry for the years 2024-2026 based on Toms Hardware article below.

Sources: 

TSMC: Our 3nm Node Comparable to Intel's 1.8nm Tech | Tom's Hardware (tomshardware.com)

Intel and TSMC company web pages

Semiconductor Supply Chain Problems Running Rampant?

Solutions to mitigate future materials supply vulnerabilities

By Lita Shon-Roy, MS/MBA, and Sachi Brown, TECHCET CA

Over the past 2 to 3 years, the semiconductor industry has faced extreme pressure to meet growing consumer demand for an abundance of everyday electronic products like cars, smartphones, and computers. This pressure has only been amplified by various supply chain issues stemming from the raw material sources that are essential to building semiconductors. These material dependencies are easy to overlook since they reside in the sub-tier of the semiconductor market, hidden from direct view of what is sold to chip fabricators and consumers. TECHCET, a leading materials supply chain analysis firm, has consistently worked to uncover many of these dependencies, such as for fluorspar, neon, and helium. These materials play an essential role in the supply chain lifeline to the semiconductor industry and require expertise to identify, qualify, and track for the efficient forward movement of the market.

With recent chip shortages, various producers around the world have announced plans to invest in chip expansions that total more than US$500B over the next five years. For the US alone, this equates to an increase of >45% in semiconductor wafer starts by 2026. While this sounds hopeful for resolving chip deficiencies, it still does not address one key weakness: material shortages. As the industry expands, the risk of complications to the semiconductor supply chain grows, elevating the importance for material supply chain tracking and analysis.

Sulfuric acid is one example of an essential material that would put the semiconductor supply chain at risk if its supply is not properly managed. Fortunately, TECHCET has identified a >50% increase in demand for US sulfuric acid by 2026 to help key chip fabs prepare for expansions. TECHCET consistently provides key metrics related to supply and demand to the Critical Materials Council (CMC), a consortium formed in the mid-1990’s made up of chip fabricators and material suppliers. The Council also provides feedback to TECHCET to direct their ongoing supply chain analysis work. Identifying materials-related disruptions, dependencies, and weaknesses within the supply-chain, are all key elements of TECHCET’s focus and benefits to the CMC subscriber members.

In recent years, material shortages from the Russia-Ukraine conflict and COVID-19 have proven to be high stress points for chip fabricators and material suppliers. For example, neon gas faced shortages at the onset of the Russia-Ukraine war, threatening the stability of semiconductor production and causing high anxiety among chip fabs. At the time, it was unknown how much the US and Asia relied on Ukraine for neon supply. TECHCET managed to uncover various dependencies on Ukrainian neon from different regions around the world, helping major chip companies re-evaluate and better stabilize their supply chains. During the COVID pandemic, sporadic and extreme ocean freight roadblocks also contributed to slowdowns in chip manufacturing. In response to these disruptions, CMC subscriber companies met with logistics and shipping port officials to improve mitigation strategies for further supply interruptions.

CMC member subscribers also gain insight into supply chain challenges from the CMC Seminar. The next one will be hosted in Taiwan (October 25) and will focus on current problems in the materials supply chain and future quality requirements. This event is one of several that brings conversation on supply issues to the forefront. These events connect the entire semiconductor ecosystem by providing essential information on critical materials needed by decision makers at chip fabricators, suppliers, and government. The current CMC chip fab subscribers include more than a dozen of the world’s largest chip makers. (Reference: https://cmcfabs.org)

Given the massive impact semiconductors have in our digital global society, there is a growing and persistent need to manage the coming supply-chain issues, especially with expectations for chip volume to sharply ramp come 2025-2026. Looking into the future, TECHCET and the CMC will continue to facilitate coordination among key players in the materials and chip industry to navigate what lies ahead.

For more information on TECHCET: https://techcet.com or https://cmcfabs.org/2023-cmc-seminar/.

Lita Shon-Roy is President/CEO of TECHCET CA LLC, an advisory services firm expert in market analysis and business development of electronic markets and supply-chains for the semiconductor, display, solar/PV, and LED industries.

Sachi Brown is the Marketing Specialist of TECHCET CA LLC, in charge of marketing communications.

Tokyo Electron Integrated Report/Annual Report 2023 available for download

Tokyo Electron (TEL) issues an integrated report for the purpose of reporting our medium- to long-term profit expansion and continuous corporate value enhancement to their stakeholders.

As they celebrate their 60th anniversary this year, the 2023 report looks back at the history of our business expansion. It also details our efforts to continuously create value by the value chain of their business activities anchored around material issues, in conjunction with their sustainability initiatives.

For anyone involved in the semiconductor industry or those eager to gain fresh perspectives in this dynamic field, this report is a must-read. It not only showcases TEL's history and strategies but also sheds light on industry trends, sustainability practices, and the exciting developments shaping the future of semiconductor technology. Dive into this comprehensive report and unlock valuable knowledge about TEL's journey and the semiconductor industry at large.

Integrated Report/Annual Report | Investor Relations | Tokyo Electron Ltd. (tel.com)

TEL also have great training material and a Nanotech Museum:

Learn about semiconductors | Tokyo Electron Ltd. (tel.com)

nanotec museum (tel.com)

Global Fab Equipment Spending to Rebound in 2024 After 2023 Slowdown, Predicts SEMI Report

Global fab equipment spending is anticipated to decline by 15% in 2023, dropping to $84 billion from the record high of $99.5 billion in 2022. However, a recovery of 15% to $97 billion is expected in 2024, driven by the end of a semiconductor inventory correction in 2023 and increased demand in high-performance computing (HPC) and memory segments. The foundry segment will lead the industry's expansion in 2023 with $49 billion in investments, while memory spending is set to make a strong comeback in 2024 with a 65% increase to $27 billion. 

Taiwan will remain the top region for fab equipment spending in 2024, with $23 billion, followed by Korea with $22 billion, and China in third place at $20 billion. The Americas and Europe/Mideast regions are also expected to see increased investments, while capacity growth in the global semiconductor industry is forecasted to continue, rising by 6% in 2024.

Source: 2024 Global Fab Equipment Spending Recovery Expected After 2023 Slowdown, SEMI Reports | SEMI

Exploring SMIC's 7nm Semiconductor Advancements: Technology, Dimensions, and Future Prospects

The recent introduction of Huawei's Mate 60 Pro smartphone, featuring a 7 nm chip from Semiconductor Manufacturing International Corp. (SMIC), has raised questions about the authenticity of SMIC's technological strides and their implications. This summary dives into the heart of SMIC's 7 nm technology, shedding light on its dimensions, technological intricacies, challenges, and the outlook for the future.

However, it has been known for some time that SMIC has been developing at putting out 7 nm chips, and an early 2022 assessment published at Seeking Alpha can be found here: Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha

The SMIC 7 nm Technology Debate

Central to the debate surrounding SMIC's technology is the classification of whether it genuinely qualifies as 7 nm. Parameters such as Fin Pitch (FP), Contacted Poly Pitch (CPP), and Metal 2 Pitch (M2P) are scrutinized. While SMIC's FP pitches are larger than TSMC's 10 nm, its CPP and M2P dimensions match TSMC's 10 nm, creating a complex classification.

SMIC appears to have a serviceable first generation 7nm process now with a reasonable prospect to get to second generation 7nm/6nm in the near futures. 5nm and 3nm while theoretically possible would be highly constrained and expensive process versions if pursued due to the lack of EUV. - Scotten Jones, SemiWiki (LINK)

Design Technology Co-Optimization (DTCO) Features

SMIC's 7 nm process introduces Design Technology Co-Optimization (DTCO) features uncommon in traditional 10 nm processes. Notably, SMIC's track height is smaller than TSMC and Samsung's 10 nm processes, approaching 7 nm-class characteristics. These features add to the nuanced evaluation of SMIC's technological position.

Cell Density and Cut Masks

SMIC's high-density logic cell boasts an impressive 89 million transistors per millimeter squared, akin to Samsung and TSMC's first-generation 7 nm processes. This suggests that SMIC's technology aligns with the 7 nm category, though the debate on its dimensions continues. Notably, SMIC's process introduces larger Contacted Poly Pitch (CPP) dimensions, hinting at potential performance challenges that necessitated this adjustment.

The EUV Challenge and Future Prospects and Alternative Technologies

SMIC's journey toward further technological advancements faces significant hurdles due to the unavailability of extreme ultraviolet lithography (EUV) systems in China. EUV technology plays a pivotal role in pushing semiconductor boundaries. However, ongoing US restrictions on EUV system shipments to China constrain SMIC's options for achieving cutting-edge technology.

Self aligned multi patterning (SAMP) in Advanced Logic Semiconductor Manufacturing

In advanced logic semiconductor manufacturing, addressing the challenges posed by sub-5 nm nodes and dense metal layers is essential. SMIC can consider alternative technologies like Atomic Layer Deposition (ALD) and Directed Self-Assembly (DSA) to overcome these hurdles.

ALD stands out for its precision in depositing thin films, allowing for the creation of ultra-thin etch masks, spacers, and precise control over critical dimensions. On the other hand, DSA leverages materials' self-assembly properties to form predefined patterns, effectively dividing pitch sizes and simplifying lithography masks.

Incorporating ALD and DSA into semiconductor manufacturing processes has the potential to enhance the capabilities of immersion lithography, enabling smaller nodes without the need for EUV lithography. While these technologies require further research and development, they offer promise in helping semiconductor manufacturers advance their technology and remain competitive, particularly in the absence of EUV lithography equipment.

Together with self-aligned multi-patterning (SAMP) techniques like self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and self-aligned litho-etch-litho-etch (SALELE), these alternative approaches provide SMIC with a range of options to navigate the complexities of advanced semiconductor manufacturing, ultimately shaping the future of Chinese advanced chip fabrication.

The Future of Nanoimprint Lithography: High-Volume Production Possibilities

Nanoimprint lithography (NIL) offers potential for high-volume production with sub-10 nm resolution, revolutionizing semiconductor manufacturing. TEL and Canon have showcased NIL's sub-10 nm capabilities, making it suitable for multiple memory generations using a single mask. Challenges like edge placement errors (EPE) are addressed through precision techniques like Quasi-Atomic Layer Etch (Quasi-ALE). To achieve aggressive scaling targets, overlay accuracy and critical dimension uniformity (CDU) management are vital. NIL's simplicity and cost-effectiveness make it a promising contender, with ongoing development poised to refine its integration into semiconductor fabrication.

Future Outlook for SMIC and China

SMIC's path forward may involve alternative fabrication technologies such as ALD, DSA, and NIL. that offers the potential for high-volume production with sub-10 nm resolution.

By mastering and integrating these advanced technologies into semiconductor manufacturing could potentially expand immersion lithography's capabilities, accommodating smaller nodes without depending on EUV lithography. While further research and development are essential, these technologies offer potential pathways for SMIC to advance its fabrication processes and sustain competitiveness, particularly in the absence of EUV lithography equipment. These strategies, alongside self-aligned multi-patterning techniques, stand to influence the future of advanced chip fabrication in China beyond 7 nm. 

The answer is as always - it depends. For how long will China have access to also Immersion Lithography? Will top tier OEMs be allowed to continue to export ALD and other process technology needed to China? What will be the cost using higher complexity and additional masks needed for SAQP (cut masks)? Is Huawei's limited chip demand, as compared to Apple & Co, enough to pay for the R&D needed? Will Chinese state support cover the development and fab expansion cost? 

Sources:

193i Lithography Takes Center Stage...Again (semiengineering.com)

Does SMIC have 7nm and if so, what does it mean - SemiWiki

Look Inside Huawei Mate 60 Pro Phone Powered by Made-in-China Chip - Bloomberg

BALD Engineering - Born in Finland, Born to ALD: The Future of Nanoimprint Lithography: Exploring Possibilities and Challenges for High-Volume Production

BALD Engineering - Born in Finland, Born to ALD: Comparison confirms that SMIC reaches 7nm without access to western equipment & technologies

Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha

Metal Plating Chemicals Revenues to Boost into 2024

Growth driven by developments in leading-edge logic and memory

San Diego, CA, August 31, 2023: TECHCET—the electronic materials advisory firm providing business and technology information— reports that revenues for the Semiconductor Metal Plating Chemicals market will rise to USD $1,047M in 2024, a 5.6% increase from the forecasted USD $992M for 2023. The largest revenues for 2024 are forecasted for copper plating chemicals used for device-level interconnect and advanced packaging wiring, as explained in TECHCET’s newly released Metal Chemicals Critical Materials Report. The 5-year CAGR’s for 2022-2027 are expected to remain on an upward track, with 3.5% growth for advanced packaging and 3% for copper device interconnects.

“Increased usage of advanced packaging, redistribution layers, and copper pillar structures are all factors contributing to the growth of the metal chemicals market segment,” states Dr. Karey Holland, Chief Strategist at TECHCET.

A potential risk factor for the metal chemicals market is increased lead times and price increases for electronic chemicals. Fabs and plating chemical suppliers are not reporting any difficulty obtaining metals for semiconductor plating in 2023, however, shortages may occur in the future. Geopolitical tensions with China, for instance, may hinder the availability of tin that is mined there. Similarly, nickel imported from Russia and Ukraine may face supply constraints.

To read the full article, go to: https://lnkd.in/gqdUHRuM

For more details on the Semiconductor Metal Plating Chemicals market & supply chains, go to: https://lnkd.in/gFQNSEpa

To discuss more on the supply-chains for metal chemicals and other semiconductor materials, come talk to TECHCET at the CMC Seminar in Taichung, Taiwan on October 25th. For more information and to register, go to: https://lnkd.in/gZN2gjWT.

The Industiral Ecosystem of Si Chips and Atomic Layer Deposition - Webinar

American Chemical Society

@AmerChemSociety

·

23h

Register now for a FREE #ACSScienceTalks #VirtualEvent with

@ChemMater

 Assoc Editor

@HanBoRam_Lee

discussing "The Industrial Ecosystem of Si Chips & Atomic Layer Deposition as a Key Nanofabrication Technology." https://brnw.ch/21wC0I4

Global Semiconductor Industry Poised for 2024 Recovery Amidst Near-Term Challenges, SEMI Reports

In a recent report by SEMI, in collaboration with TechInsights, the global semiconductor industry shows signs of emerging from its downcycle, with a projected recovery expected in 2024. The report highlights that the third quarter of 2023 is anticipated to witness a healthy 10% quarter-on-quarter growth in electronics sales, while memory IC sales are set to achieve double-digit growth for the first time since the downturn began in 2022. Although headwinds persist in the semiconductor manufacturing sector during the latter half of 2023, a rebound is on the horizon.

Inventory drawdowns at integrated device manufacturer (IDM) and fabless companies are forecasted to keep fab utilization rates lower than those seen in the first half of 2023. Despite this, positive trends are noted in capital equipment billings and silicon shipments, stemming from government incentives and robust equipment sales backlogs.

Market indicators suggest the semiconductor industry reached its nadir by mid-2023, commencing a path to recovery, setting the stage for growth in 2024. All segments are predicted to witness year-over-year increases in 2024, with electronics sales projected to surpass their 2022 peak.

Clark Tseng, Senior Director of Market Intelligence at SEMI, pointed out that the gradual demand recovery might extend the timeline for inventory normalization until the end of 2023, leading to temporary reductions in fab utilization rates. Nevertheless, semiconductor manufacturing is expected to hit its bottom in Q1 2024.

Boris Metodiev, Director of Market Analysis at TechInsights, highlighted the resilience of equipment sales and fab construction despite the broader downturn. He attributed this trend to government incentives driving new fab projects and strong backlogs supporting equipment sales.

Original Source: SEMI https://www.semi.org/en/news-resources/press-releases/2023/08/global-semiconductor-industry-on-track-for-2024-recovery-but-near-term-headwinds-remain-semi-reports

AI Chip Market Poised to Soar: Gartner Predicts Revenue to Reach $53 Billion in 2023, Double by 2027

Gartner forecasts that worldwide AI chips revenue will reach $53.4 billion in 2023, an increase of 20.9% from 2022. The growth is driven by the developments in generative AI and the increasing use of a wide range of AI-based applications, such as natural language processing, computer vision, speech recognition and machine learning.

The AI semiconductor industry is on the brink of a remarkable surge, as outlined by Gartner's latest forecast. Predicting an impressive revenue increase of 20.9%, the industry is set to reach a staggering $53.4 billion in 2023. This upward trajectory shows no signs of slowing down, with anticipated growth rates of 25.6% in 2024, culminating in an AI chips revenue forecast of $67.1 billion. However, the real eye-opener lies in Gartner's projection for 2027, where the AI chips market is poised to more than double, reaching an astonishing $119.4 billion. 

This meteoric rise is attributed to the expanding landscape of AI-based applications in data centers, edge devices, and more, necessitating the deployment of high-performance graphics processing units (GPUs) and tailored semiconductor devices. Notably, custom-designed AI chips are expected to become a staple, replacing prevalent architectures and accommodating the growing demand for optimized AI workloads. The consumer electronics sector is also embracing this transformation, with the value of AI-enabled application processors predicted to surpass $1.2 billion by the close of 2023. The future shines brightly for AI chips, as generative AI techniques and hyperscalers' interests drive innovation and efficiency in deploying AI applications. Gartner's insights underscore the imminent revolution in the semiconductor industry, ushering in an era of unprecedented growth and potential.

Gartner clients can read more in “Forecast: AI Semiconductors, Worldwide, 2021-2027, 2Q23 Update.”

TSMC Marks Major Milestone: First EUV Machine Installed in Arizona Fab, Job Opportunities Open

Taiwan Semiconductor Manufacturing Co. (TSMC) has achieved a significant milestone in its Arizona manufacturing venture by installing its inaugural extreme ultraviolet lithography (EUV) machine. This advanced machine, procured from Dutch semiconductor equipment leader ASML Holding NV, is a pivotal asset for TSMC's future high-end chip production endeavors.

EUV technology is a critical aspect of semiconductor fabrication, facilitating the printing of intricate designs on microchips significantly smaller than a human hair. TSMC's achievement underscores its commitment to innovation and technological leadership.

While the installation of the EUV machine marks a remarkable accomplishment, TSMC acknowledges that the setup of the new fab in Arizona involves numerous additional tasks. The company emphasized the need for approximately 2,000 skilled workers to handle the installation of various equipment pieces and services in the complex. This requirement stems from TSMC's unique tool configurations and specifications.

TSMC, recognized as the world's largest contract chip manufacturer, is channeling substantial investments amounting to $40 billion into constructing two wafer fabs in Phoenix. The first facility will employ the advanced 4-nanometer process, while the second, already under construction, will utilize the more sophisticated 3-nanometer process. This latter technology has already entered mass production in Taiwan.

The presence of skilled workers has been a contentious topic linked to the Arizona project. TSMC Chairman Mark Liu explained that a deficiency in experts capable of properly installing equipment at the Arizona site has led to a delay in mass production, now projected for 2025 rather than late 2024.

However, TSMC's approach to addressing this shortfall has sparked debates. The company's bid to bring in around 500 Taiwanese workers on temporary E-2 visas has faced resistance from local unions, who assert that prioritizing American jobs is paramount, especially considering the significant subsidies TSMC seeks under the CHIPS and Science Act. This legislation, signed by President Joe Biden, encourages semiconductor investments in the United States.

US Senator Mark Kelly of Arizona emphasized that the visa applications will be evaluated in accordance with established laws and procedures. As TSMC navigates these challenges, its progress in Arizona remains a focal point in the semiconductor industry's dynamic landscape.

TSMC installs first EUV machine in U.S.; job opening ads posted - Focus Taiwan

An Update on Directed Self-Assembly (DSA) for Advancing Micro and Nano Fabrication

Revolutionizing fabrication, Directed Self-Assembly (DSA) innovates micro to nano devices and materials. It leverages block co-polymer morphology for precise patterns and guides micro/nano particles, enhancing manufacturing. In semiconductors, DSA addresses lithography challenges, while Imec's research showcases DSA-EUV synergy for defect-free outcomes. Complex rectification processes, illustrated by Imec, spotlight improved Critical Dimension Uniformity and Pattern Placement Error control. As DSA advances, its collaboration with EUV promises precision, efficiency, and innovation across industries.

DSA has emerged as a groundbreaking technique for mass-producing micro to nano devices and materials with precision and efficiency. This method harnesses the inherent properties of materials to assemble them into intricate structures, revolutionizing manufacturing processes across various industries.

DSA leverages block co-polymer morphology to create patterns, enhancing feature control and shape accuracy. This involves guiding the assembly of micro and nano particles to achieve desired structures, made possible by the precise control of surface interactions and polymer thermodynamics. The key advantage of DSA is its ability to create structures at remarkably small scales, enabling advancements in diverse fields.

In the semiconductor industry, DSA offers a new perspective on lithography challenges. Despite initial setbacks, DSA is being revisited to address critical issues such as stochastic defects in extreme ultraviolet (EUV) lithography. These defects, which can contribute significantly to patterning errors, have led semiconductor manufacturers to explore DSA as a solution to rectify these problems. Notably, DSA is not replacing traditional methods but rather enhancing them. It is being integrated with existing manufacturing processes to enable increased resolution and precision, all while reducing costs.

However, challenges persist in integrating DSA into high-volume manufacturing. Defect control remains a primary concern, as the technology strives to meet industry standards of minimal defectivity. Common defects include line bridging, collapse, bubbles, and dislocations. Efforts are ongoing to optimize annealing temperature, etching methods, and film thickness to reduce these defects. Another challenge is the complexity of pattern inspection, which demands accurate metrology methods. Researchers are exploring machine learning-based approaches to automate the inspection process and achieve higher throughput.

Despite these challenges, DSA is being applied to various applications beyond semiconductors. Tissue engineering benefits from the precision of directed assembly, enabling the controlled organization of cells into desired micro-structures. In nanotechnology, DSA facilitates the creation of precise nanostructures, leading to advancements in areas such as graphene nanoribbon arrays and thin-film quantum materials.

Revolutionizing EUV Lithography with Directed Self-Assembly (DSA)

EUV lithography has revolutionized semiconductor manufacturing but comes with its share of challenges, particularly in addressing line roughness and stochastic defects. DSA has now gained attention as a potential game-changer to tackle these issues in EUV lithography.

Recent research from Imec sheds light on the promising synergy between EUV and DSA in overcoming lithography challenges. In the study titled "EUV Lithography Line Space Pattern Rectification Using Block Copolymer Directed Self-Assembly: A Roughness and Defectivity Study," led by Julie Van Bel and team, the researchers explored the combination of DSA with EUV. Their findings indicate that this integration surpasses DSA processes based on Immersion lithography, offering lower line width roughness and freedom from dislocation defects.

Another study, "Mitigating Stochastics in EUV Lithography by Directed Self-Assembly," led by Lander Verstraete and collaborators, delved into the application of DSA to mitigate stochastic defects in EUV processing.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in Figures below. In the top Figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using DSA. Meanwhile, the lower Figure details the rectification process for defects in EUV Contact Patterns.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in the figures below. In the top figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using Directed Self-Assembly (DSA). Meanwhile, the lower figure details the rectification process for defects in EUV Contact Patterns. These illustrations highlight the potential of DSA in enhancing lithographic precision, addressing challenges related to line roughness and stochastic defects, and achieving improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error control in semiconductor manufacturing.

The results are particularly promising for line/spaces at a 28nm pitch, primarily addressing bridge defects. However, at a 24nm pitch, further improvement is necessary due to an excess of bridge defects. Notably, the type and frequency of defects correlate with the formulation of the block copolymer and the duration of the annealing process.

For contact arrays, the combination of EUV and DSA demonstrates improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error. This advancement also enables the use of a lower dose, contributing to enhanced precision and efficiency in semiconductor manufacturing.

Imec's research underscores the potential of DSA to revolutionize EUV lithography by addressing line roughness and stochastic defects. The successful integration of EUV and DSA holds the promise of enhancing semiconductor manufacturing processes, achieving higher precision, and enabling the production of advanced devices with improved quality. As researchers continue to refine these methods, the collaboration between EUV and DSA is set to shape the future of lithography and microfabrication.

In conclusion, DSA is revitalizing micro and nano fabrication by offering accurate and efficient methods for mass production. While challenges like defect control and metrology persist, DSA's potential to shape the future of industries such as semiconductors, biomedicine, and nanotechnology is undeniable. As research continues to refine DSA processes and overcome hurdles, its role in advancing technology and innovation is set to expand further.

Directed Self-Assembly Finds Its Footing (semiengineering.com)

SPIE 2023 – imec Preparing for High-NA EUV - SemiWiki

Directed assembly of micro- and nano-structures - Wikipedia