Tokyo Electron Delivers Record FY2025 Results Amid AI Boom, Eyes Growth Through CVD Innovation and Geopolitical Resilience

Tokyo Electron (TEL) achieved a record-breaking financial year in FY2025, with strong top- and bottom-line growth driven by robust global demand for advanced semiconductor equipment. Net sales rose by 32.8% year-on-year to approximately ¥2.43 trillion (around $15.7 billion USD), marking the highest in the company's history. Operating profit surged to ¥697.3 billion (about $4.5 billion USD), supported by an improved operating margin of 28.7%. Growth was underpinned by increased investment in leading-edge logic and memory, particularly High Bandwidth Memory (HBM) and advanced DRAM nodes, where TEL maintained or expanded market share through key Process of Record (POR) wins in etch and wafer bonding technologies. Revenue contributions diversified geographically, with notable gains in South Korea and Taiwan, even as China remained a key market. TEL also demonstrated strong cash flow, increased its R&D and capital investments, and returned significant value to shareholders through dividends and buybacks. Looking ahead, TEL forecasts continued growth in FY2026, positioning itself to capitalise on accelerating AI, 2nm logic, and heterogeneous integration trends.

Tokyo Electron TEL has demonstrated strong financial performance and strategic market expansion through FY2025, according to their investor presentation dated April 30, 2025. Their net sales, gross profit, operating profit, and net income have all reached record highs, signaling both operational efficiency and favorable market conditions.

LINK: Tokyo Electron Limited 2025 Q4 - Results - Earnings Call Presentation (OTCMKTS:TOELY) | Seeking Alpha

Tokyo Electron's Q4 FY2025 earnings call highlighted strong financial performance and an optimistic forward outlook amid geopolitical uncertainties. Despite global concerns around US tariffs and export controls—particularly in China, which saw its WFE market share fall to 35%—TEL stated that it has not observed any significant changes in customer investment sentiment or competitive dynamics. The company reaffirmed its strategy of focusing on long-term innovation rather than short-term regulatory shifts, underscoring its commitment to developing higher-productivity tools to offset potential external headwinds. Looking ahead, TEL forecasts continued double-digit WFE market growth into calendar 2026, driven by AI infrastructure demand, 2nm logic, and HBM scaling. The company plans record-high investments of ¥300 billion in R&D and ¥240 billion in CapEx for FY2026, reflecting confidence in sustained momentum across DRAM, advanced logic, and packaging technologies. TEL aims to expand global market share and reach ambitious mid-term goals, including over ¥1 trillion in operating profit and 35%+ OPM, by capitalising on technology transitions such as GAA, backside PDN, and heterogeneous integration.

LINK: Tokyo Electron Limited (TOELY) Q4 2025 Earnings Call Transcript | Seeking Alpha

Revenue and Profitability Growth:

Net sales increased significantly from ¥1,399.1 billion in FY2021 to ¥2,431.5 billion in FY2025, a 74% increase over four years. The gross profit also rose steadily, reaching ¥1,146.2 billion in FY2025, up from ¥564.9 billion in FY2021. Operating profit followed suit, more than doubling from ¥320.6 billion to ¥697.3 billion. These trends underscore TEL’s ability to scale profitably, with operating margins rising from 22.9% in FY2021 to 28.7% in FY2025. Return on equity (ROE) also remained strong, peaking at 37.2% in FY2022 and settling at 30.3% in FY2025, a testament to effective capital management.

Regional Sales Composition:

The revenue breakdown by region from Q1 FY2024 to Q4 FY2025 shows growing diversification. Notably, China has remained the single largest market, although its share declined from 47.4% in Q4 FY2024 to 34.3% in Q4 FY2025, reflecting a strategic balancing across geographies. South Korea, Taiwan, and North America significantly increased their contributions, with South Korea reaching ¥147.0 billion and Taiwan ¥135.8 billion in Q4 FY2025. This reflects growing demand from advanced logic and memory fabrication customers in these regions.

In FY2025, Tokyo Electron’s semiconductor production equipment (SPE) sales reached ¥1.86 trillion, driven by a sharp rise in DRAM-related investments, particularly for high-bandwidth memory (HBM), which accounted for 31% of total sales. Non-volatile memory (NAND) remained stable at 7%, while non-memory segments, including logic and foundry, continued to dominate with 62%, reflecting robust demand from both advanced and mature nodes. The overall recovery and expansion of customer investments across segments underpinned this strong performance.

Market Segment Performance

Tokyo Electron’s global market share in CY2024 demonstrates its leadership across multiple core segments of the semiconductor production equipment market. The company holds a commanding 92% share in coater/developer systems, underlining its unparalleled position in photoresist processing for advanced lithography applications. It also leads the wafer prober segment with a 38% share and maintains robust positions in key deposition categories, including 38% in CVD and 37% in oxidation/diffusion systems. In contrast, TEL’s market share in ALD stands at 16%, notably behind ASM International, highlighting an opportunity for expansion in this strategically important technology as the industry moves towards GAA and other 3D device structures. Performance in dry etch (27%), cleaning systems (21%), and wafer bonding (32%) rounds out a broadly competitive portfolio that positions TEL to effectively support ongoing advancements in scaling, heterogeneous integration, and high-performance packaging across logic, memory, and AI-related applications.

To further expand our future profit, we made steady progress in penetrating into new technology domains. Specifically, we released multiple new outstanding products contributing to the semiconductor technology innovation. For example, penetration to untapped segments such as single-wafer plasma CVD and PVD, gas cluster beam system which improves efficiency of leading-edge lithography, and laser-lift-off system to drastically decrease environmental footprint of processing. In fiscal 2025, we conducted share repurchase of about ¥150 billion in total.

- Toshiki Kawai - Representative Director, President and CEO

 

New product 2025 Episode™ single-wafer CVD platform

Episode™ 1 is Tokyo Electron's latest single-wafer CVD platform, launched in 2024 to address the challenges of advanced device scaling in logic, DRAM, and future AI processors. It supports up to eight process modules, enabling complex, uninterrupted multi-step processing. The system integrates the OPTCURE™ module for native oxide removal and ORTAS™ for titanium CVD, allowing immediate Ti deposition to minimise contact resistance in advanced interconnects. Episode™ 1 replaces traditional PVD with CVD to achieve uniform, low-resistivity films in high aspect ratio structures such as deep contact holes. With a 45% smaller footprint than its predecessor and advanced edge computing, data analytics, and environmental tracking capabilities, the system enhances fab productivity, engineer efficiency, and readiness for new materials in next-generation device manufacturing.

The TEL Episode™ 1 system shown in the image seems to feature twin or dual single-wafer process chambers, which is typical in modular CVD tools designed for high throughput. Each visible module (with two load ports per unit) likely contains two process chambers within the same footprint to maximise wafer handling efficiency and enable parallel processing—common in tools aimed at advanced logic and memory manufacturing.

Episode™ 1 offers a reduced footprint. Compared with the Triase+™ series, twice as many smaller modules can be installed in a system. With the same number of modules installed, Episode™ 1 takes up about 45% less fab space than its predecessor

LINK: Episode™ 1 Single-Wafer Deposition System for Semiconductors: Driving the Evolution of AI Semiconductors to Transform Everyday Life | Blog | Tokyo Electron Ltd.

Neumonda and Ferroelectric Memory Company Collaborate in the Commercialization of Non-Volatile DRAM

Neumonda and Ferroelectric Memory (FMC) are working together to design, provide test solutions, and market FMC’s nonvolatile DRAM+. This collaboration aims nothing less than to bring semiconductor DRAM memory design and manufacturing back to Germany.

Marco Mezger, COO of Neumonda, Thomas Rueckes, CEO of FMC, and Peter Poechmueller, CEO of Neumonda (from left to right), celebrate the collaboration of the two German memory powerhouses

Two German memory innovators join forces to bring semiconductor memory back to Germany

Bad Homburg / Dresden, April 3, 2024 – Neumonda and Ferroelectric Memory (FMC) are working together in the design, provision of test solutions, and marketing of FMC’s nonvolatile DRAM+. This collaboration aims nothing less than to bring semiconductor DRAM memory design and manufacturing back to Germany.

FMC commercializes a disruptive technology that combines non-volatile properties of ferroelectric hafnium oxide (HfO2) with RAM to create a non-volatile DRAM memory for AI, medical, industrial, automotive, and consumer applications. As part of the agreement, Neumonda which holds several patents in the design and testing of DRAM memory, will support FMC with memory consulting services and with its Rhinoe, Octopus, and Raptor test platforms for FMC’s nonvolatile DRAM+ products.

“FMC was founded to exploit the disruptive invention of the ferroelectric effect of HfO2 for semiconductor memories. Applied to a DRAM, it turns the DRAM capacitor into a low power, nonvolatile storage device while maintaining the high DRAM performance to produce a disruptive nonvolatile DRAM memory ideal for AI compute,” explained Thomas Rueckes, CEO of FMC. “Since our technology is unique in the market, cost-effective testing of our memory products is of great importance for our product offerings. With Neumonda and its radically new approach to testing, we have found a partner that can help us speed up the development of our products. We also are excited to work with Neumonda as we share the common vision to bring Memory back to Europe”

Neumonda combines unmatched expertise in memory and, with its Neumonda Technology division, revolutionizes memory testing. Its testers are lightweight, low-cost, and energy-efficient and enable Neumonda to conduct manufacturer-independent tests at a level and detail that has not been possible before—all this at a fraction of the costs of traditional testers.

“As our test platforms are maturing, FMC’s products are an ideal test ground to prove the capabilities of our Rhinoe, Octopus, and Raptor testers, as well as the high-quality yield they enable,” explained Peter Poechmueller, CEO of Neumonda. “One of my personal goals behind founding Neumonda was to bring semiconductor memory back to Europe. With this collaboration, we take a big step closer to establishing a new German memory manufacturer.

About FMC

FMC was founded in 2016 as a spin-off from NaMLab GmbH, a TU Dresden company, to commercialize ferroelectric hafnium oxide technology originally invented by Qimonda, the former German DRAM manufacturer. FMC is a full stack fabless semiconductor company with operations in Dresden (Germany), Milan (Italy) and North America. FMC product offerings include high density, low power, nonvolatile DRAM and Cache chiplets for disruptive performance and power efficiency improvements in edge and cloud AI systems. Since its foundation, FMC has been working closely with Saxonian, Federal German and European funding providers and is very thankful for this continuous support. For more information visit: www.ferrolectric-memory.com

About Neumonda

NEUMONDA combines extensive memory experience with the “DNA” of former memory manufacturer Qimonda, with the aim to offer the most extensive portfolio of specialized memory solutions and competence in the market. It governs MEMPHIS Electronic, a distributor of memory ICs and modules of different suppliers; Intelligent Memory, the manufacturer of DRAM and NAND-based memory solutions; and NEUMONDA Technology which designs and holds IP for application test systems for memory applications. Combining these different areas of expertise, NEUMONDA is able to offer unique global memory competency that can help companies in any industry to meet their current and future memory requirements. www.neumonda.com

Lam Research’s Dry Resist: A Breakthrough in EUV Lithography for Next-Generation Logic and Memory Manufacturing

Lam Research’s dry resist technology represents a major shift in EUV lithography and semiconductor patterning, addressing critical challenges such as stochastic defectivity, resolution limitations, and cost-efficiency. With recent qualifications for advanced DRAM and 2nm logic manufacturing, along with a growing ecosystem for high-volume production, dry resist is positioned to disrupt traditional chemically amplified resists (CARs) and enable future High-NA EUV adoption.

One of the most significant recent developments is Lam’s qualification of dry resist for 28nm pitch BEOL logic at 2nm and below in collaboration with imec. This qualification confirms that dry resist can eliminate multi-patterning steps, reducing complexity and improving EUV throughput. The process is designed to work with both low-NA and high-NA EUV scanners, ensuring its relevance for sub-2nm logic scaling. This represents a key milestone in extending direct EUV printing to future logic nodes, an approach that could significantly lower lithography costs while improving pattern fidelity.

In addition, a leading DRAM manufacturer has selected Lam’s Aether dry resist technology as its production tool of record for advanced DRAM nodes. This decision highlights dry resist’s low-defect, high-fidelity patterning capabilities, which are essential for scaling memory architectures. The technology enables lower exposure doses while reducing stochastic defects, which are a major concern in EUV-based DRAM production. Given that Samsung, SK Hynix, and Micron are all increasing their reliance on EUV for next-generation DRAM, Lam’s dry resist is well-positioned for widespread adoption in the memory sector.

To ensure a stable supply chain for dry resist materials, Lam Research has partnered with Entegris and Gelest, a Mitsubishi Chemical Group company. This collaboration ensures reliable dual-source precursor production, providing chipmakers with long-term process stability. The partnership also focuses on the development of next-generation high-NA EUV precursors, further strengthening dry resist’s role in future sub-2nm manufacturing.

SEM images of 28 nm pitch line/space patterns imaged with 0.33NA EUV in dry resist from Entegris precursor.

A critical enabler of dry resist technology is its atomic layer deposition (ALD) process, which replaces traditional spin-coating used in CARs. ALD-based vapor-phase deposition offers higher uniformity, eliminating polymer chain variations found in conventional resists. It also allows precise thickness control, which is essential for optimizing EUV photon absorption and etch selectivity. Unlike CARs, which rely on a complex mixture of polymers, dry resist materials are based on single-component metal-organic precursors such as organo-tin oxides. These materials provide higher EUV photon absorption, improving sensitivity and pattern resolution.

Another key advantage of dry resist is its anisotropic dry development process, which replaces wet solvent-based development. Traditional CAR-based EUV resists require organic solvents or aqueous bases, leading to stochastic defects, material loss, and waste. Dry resist, by contrast, is developed entirely in the gas phase, selectively removing unexposed regions and forming a negative-tone image. This eliminates line collapse and delamination issues, improving yield stability. Additionally, the elimination of wet chemistries significantly reduces chemical waste, making dry resist a more sustainable solution with five to ten times lower material consumption compared to traditional resists.

Lam’s dry resist technology is poised to disrupt traditional CAR-based EUV lithography, particularly as the industry moves toward High-NA EUV adoption. By reducing multi-patterning dependency, the technology enhances cost-effective EUV scaling, making it an attractive solution for both logic and memory manufacturers. This positions Lam as a key leader in next-generation EUV resist solutions, challenging conventional resist suppliers like JSR, TOK, and Inpria.

From a sustainability perspective, dry resist significantly lowers EUV exposure dose requirements, leading to higher scanner throughput and lower energy consumption. Its reduced defectivity translates to higher yield per wafer, further enhancing cost-efficiency. The collaboration with Entegris and Gelest ensures supply-chain stability, making dry resist a viable and scalable technology for sub-2nm nodes.

The patent US20220020584A1 mentions several Lam Research tools that play a role in the dry resist deposition, patterning, and development process for EUV lithography. The Altus system is referenced for deposition, likely for metal or dielectric films in the dry resist stack, while the Striker plasma-enhanced atomic layer deposition (PEALD) system may be used for precise resist or underlayer deposition. The Versys platform, known for plasma processing, is relevant to the dry development process, and the Syndion system, typically used for deep silicon etching, may have applications in pattern transfer. Additionally, the Reliant tool is designed for volume manufacturing, possibly adapted for integrating dry resist technology, and the Kiyo plasma etch system is likely involved in etching after the dry resist development stage. These tools collectively enable Lam’s dry resist process to achieve improved resolution, defect reduction, and cost efficiency in advanced EUV lithography.

The patent US20220020584A1, filed by Lam Research Corporation, describes an innovative dry development process for EUV photoresists, which eliminates the need for traditional wet chemical development methods. The patent details a dry resist system deposited via vapor-phase precursors, forming a highly uniform, single-component material that enhances EUV photon absorption and sensitivity. The dry development process selectively removes unexposed resist regions using plasma-based or plasma-free chemical methods, significantly reducing line collapse and defectivity while improving resolution at sub-2nm nodes. By integrating dry resist deposition, EUV exposure, and dry development into a single cluster tool, the patented technology enables scalable, high-volume EUV manufacturing with lower chemical consumption and improved process sustainability, positioning it as a key enabler for High-NA EUV lithography.

Lam Research’s dry resist technology represents a significant development in EUV lithography by addressing key challenges in stochastic defectivity, process cost, and sustainability. Its qualification for 2nm logic and advanced DRAM manufacturing confirms its readiness for high-volume production. By utilizing ALD for precise resist deposition and securing a stable precursor supply through partnerships with Entegris and Gelest, Lam has established a strong foundation for scaling the technology. 

Sources:

Lam Research Press Release on DRAM Adoption (Jan 2025): Lam Research

imec Qualification of Dry Resist for 2nm Logic (Jan 2025): imec

Entegris and Gelest Collaboration Announcement (July 2022): Entegris

Overview of Dry Resist ALD and Precursor Chemistry: SemiAnalysis

ASML High-NA EUV Roadmap and Implications for Dry Resist: ASML

Lam Reserach patent application US20220020584A1: US20220020584A1.pdf

4F² DRAM developed by a Kioxia using ALD IGZO

The new 4F² DRAM developed by a Kioxia-led team combines gate-all-around (GAA) IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) with a unique design that places transistors above high-aspect-ratio capacitors to reduce thermal stress and suppress electrical interference like "row hammer." This structure increases memory density and efficiency, providing a high on/off current ratio essential for low-power operation. The team demonstrated a 275Mbit array with this technology, indicating its potential to enable high-density, low-power DRAM for advanced computing applications.

Kioxia is traditionally known for its expertise in NAND flash memory rather than DRAM. They are one of the leading companies in the NAND space, focusing primarily on storage solutions. However, this new venture into DRAM with innovative 4F² cell structures signals an expansion of their research and development scope, possibly to leverage their materials and process expertise in a closely related area. It suggests Kioxia may be exploring ways to diversify its technology portfolio, potentially addressing high-density memory needs beyond traditional NAND storage

ALD offers atomic-level precision and is beneficial for creating uniform, conformal layers of IGZO in complex, high-aspect-ratio surfaces demonstrated here, which is particularly advantageous in advanced semiconductor applications. ALD works by exposing the substrate to alternating pulses of indium, gallium, and zinc precursors, separated by purges to prevent unwanted reactions. This controlled process achieves a smooth and consistent IGZO layer with excellent thickness control, crucial for sensitive electronic applications like DRAM devices.

New Type of 4F² DRAM: DRAM is the workhorse memory of electronic systems, but patterning the extremely small features of conventional silicon 6F² DRAM memory cells and suppressing “row hammer” electrical interference from nearby cells are major challenges. To overcome them, the industry has been actively developing denser 4F² DRAM designs made with different materials. A Kioxia-led team will describe a new type of 4F² DRAM, comprising GAA IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) and a new integration scheme, where the heat-sensitive transistors are placed on the top of high aspect-ratio capacitors instead of on the bottom, to reduce the thermal impact from BEOL processing below. The vertical architecture also fully suppresses row hammer interference, because the active region isn’t shared with adjacent cells. The InGaZnO VCT achieved more than 15µA/cell ON current and 1aA/cell OFF current. The researchers demonstrated the technology by successfully building a 275Mbit array with it, demonstrating its potential for future high-density, low-power DRAM technologies.

 

Above:

(a)   is a schematic of the oxide-semiconductor channel transistor DRAM. The InGaZnO VCT was integrated on a capacitor array, a different architectural scheme from silicon-based 4F2 DRAM devices.

(b)   is a cross-sectional TEM image of the InGaZnO VCT test structure, with the key technologies needed for DRAM applications described on the right nearby. The gate oxide and InGaZnO were formed in a 26nm-diameter vertical hole.

(c)   is a cross-sectional TEM showing the InGaZnO VCTs on high-aspect-ratio capacitors.

 Source:

IEDM2024 Paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F² Architecture,” S. Fujii et al, Kioxia Corp./Nanya Technology Corp. https://www.ieee-iedm.org/press-kit

A New Zr Precursor Enhances Wafer-Scale Zirconium Dioxide Films

A new class of Zirconium (Zr) precursor, featuring boratabenzene ligand, has been developed by a team led by Mohd Zahid Ansari at Yeungnam University, enabling the production of highly conformal ZrO2 thin films via Atomic Layer Deposition (ALD). This innovation, detailed in a recent study published in Science Advances, uses tris(dimethylamido)dimethylamidoboratabenzene zirconium and oxygen as reactants to achieve amorphous ZrO2 films at temperatures ranging from 150–350 °C on SiO2/Si substrates.

The new approach decouples the conventional ALD process, enhancing the deposition temperature window and achieving a growth per cycle of 0.87 Å, which surpasses previous methods using different Zr precursors. The films exhibit extreme conformality with complete step coverage, even on substrates with complex topographies, marking a significant advancement in semiconductor fabrication.

This development not only streamlines the manufacturing process by using O2 as a mild oxidant but also promotes safer and more efficient production methods. The films transition into nanocrystalline cubic ZrO2 upon annealing at 850 °C, enhancing their properties for potential use in high-temperature applications and as coatings for optical filters. The research team's breakthrough paves the way for next-generation semiconductor devices with improved performance and reliability.

The use of ZrO2 in DRAM helps in addressing several challenges associated with the miniaturization of memory devices. As device dimensions continue to shrink, traditional silicon dioxide (SiO2) used in older generations of DRAM becomes less effective due to increased leakage currents and decreased reliability. ZrO2, with its higher dielectric constant, allows for greater data storage capacity and improved efficiency without compromising the device's size or power requirements.

Source: New class of Zr precursor containing boratabenzene ligand enabling highly conformal wafer-scale zirconium dioxide thin films through atomic layer deposition - ScienceDirect

SK hynix to Lead in Advanced DRAM Production, Overtaking Samsung with Earlier Start

Korean SK hynix is set to initiate mass production of its advanced 6th generation 10nm class DRAM (node 1c) in the third quarter of this year, ahead of its competitor Samsung Electronics. The move positions SK hynix to potentially lead in the DDR5 server memory market, which is needed for data centers operated by major tech companies. SK hynix has outlined a strategic internal roadmap that includes achieving necessary customer certifications in anticipation of a surge in demand, especially following compatibility approval with Intel's server platforms. This certification is crucial as Intel holds a dominant share in the global server CPU market. 

The DDR5 DRAM from SK hynix is designed to be compatible with Intel CPUs, a significant advantage given Intel’s extensive market presence. Meanwhile, Samsung plans to start its mass production of similar DRAM by the end of the year, having shared its development roadmap at the recent MemCon 2024 conference. Both companies are using leading-edge Extreme Ultraviolet (EUV) lithography in their processes, which enhances chip yield and power efficiency over previous generations.

SK hynix's new M16 DRAM plant in Icheon, Gyeonggi Province / Courtesy of SK hynix

Source: SK hynix Leads with ‘6th Generation 10 nm’ DRAM Production Ahead of Samsung - Businesskorea

Hanwha to supply ALD Equipment for Molybdenum Deposition for Memory Applications

According to Korean media, Hanwha Precision Machinery is developing a new type of thermal atomic layer deposition (ALD) equipment for depositing molybdenum, which is emerging as a superior material for metal gates in next-generation semiconductors due to its lower resistivity and lack of fluoride residue. The new technology, still in the prototype stage and expected to take three years to commercialize, uses molybdenum dichloride dioxide (MoO2Cl2) as a precursor. This initiative marks Hanwha's expansion into the semiconductor fabrication equipment market, collaborating with industry giants like SK Hynix on future projects, including the development of hybrid bonding equipment for high bandwidth memory production.

At two recent conferences, EFDS ALD For Industry and CMC 2024 this week in Phoenix, Air Liquide presented HVM ready solution for MoO2Cl2 sub fab delivery. They also confirmed that it is already in HVM. Other sources claim that Mo is also in HVM for DRAM. However, no reverse engineering is publicly available as of to day.

Air Liquide presenting HVM ready sub fab solution for MoO2Cl2 precursor delivery at EFDS ALD for Industry in Dresden, Germany.

Hanwha developing thermal ALD equipment for deposition of molybdenum - THE ELEC, Korea Electronics Industry Media (thelec.net)

Applied Materials Pioneer® CVD film for EUV Sculpta and DRAM Sym3 Etch applications

Applied Materials continues to lead in semiconductor technology with its introduction of the Producer® XP Pioneer® CVD patterning film at the SPIE Advanced Lithography + Patterning conference. This latest innovation is critical for DRAM scaling and EUV lithography, offering improved etch selectivity and pattern fidelity due to enhanced film density and stiffness. Optimized for use with the Sculpta® pattern-shaping system, Pioneer allows for advanced patterning capabilities, crucial for maintaining precise feature dimensions. With its adoption by leading foundry-logic and memory manufacturers, the Pioneer system is set to significantly enhance Applied Materials' portfolio and revenue, affirming its leadership in CVD technologies.

Applied Materials' Draco™ hard mask and Sym3® Y HT etch system have revolutionized DRAM production by enabling the etching of perfectly cylindrical capacitor holes, significantly enhancing etch selectivity and improving critical dimension uniformity, which contributes to a notable increase in the company's market share in DRAM.

Demand for DRAM innovation continues to grow to feed the insatiable need for memory bandwidth in the AI era. The recently launched Pioneer CVD patterning film has already been adopted by leading memory manufacturers for DRAM patterning. Pioneer is a completely new CVD architecture based on a unique high-density carbon formula that is more resilient to etch chemistries used in the most advanced process nodes, permitting thinner film stacks with superior sidewall feature uniformity.

A thinner hard mask means less vertical distance is required for etch, resulting in a lower aspect ratio. This allows use of lower-power plasma and offers better control of the ratio of ions to radicals. A higher concentration of ions produces more efficient etches with better control, allowing desired patterns to be transferred to the wafer with exceptional fidelity. Pioneer is also being co-optimized with Applied’s new Sym3® Y Magnum® etch system to provide better control over conventional carbon films for critical etch applications in memory processing.

For EUV Lithography the Pioneer CVD patterning film developed by Applied Materials addresses the stringent demands of EUV lithography by increasing film density and stiffness, which enhances etch selectivity and allows for finer pattern control, vital for the ultra-fine dimensions required in advanced chip manufacturing.

Source: Building on an Unmatched Foundation of CVD Innovation (appliedmaterials.com)

Surge in HBM Demand Marks Memory Market Recovery and Anticipated Growth in 2024 for Samsung

The global memory market, after experiencing a period of stagnation, has witnessed a resurgence in the third quarter, driven primarily by increased demand for high-density DRAM and NAND products in the PC and mobile sectors.

Samsung Electronics' financial results for 3Q23 highlighted a 12% QoQ revenue increase to 67.40 trillion Korean won, although there was a 12% YoY decrease. Notably, the company reported its highest quarterly profit for the year. Despite potential economic uncertainties in 2024, Samsung is optimistic about the recovery of the memory market and the rebound in smartphone demand. 

The memory sector saw a recovery compared to the previous quarter, especially in PC and mobile due to the rise in adoption of high-density DRAM and NAND products. The completion of customer inventory adjustments also played a role. Server demand was subdued for traditional servers due to macroeconomic uncertainties. However, strong demand persisted for AI-oriented high-density products. Samsung emphasized its focus on expanding sales of advanced node products like HBM DDR5, LPDDR5, and UFS 4.0. They also intend to manage high inventory products through production adjustments. The company expects the recovery trend in the memory market to accelerate further in the fourth quarter. Additionally, there has been a notable surge in HBM demand and the company is actively advancing its HBM businesses and plans to augment its HBM supply capacity by 2.5 times next year.

Trendforce on X (LINK)

The foundry division secured a record number of new orders, particularly in the HPC domain, despite a slow recovery in the mobile market. The new Taylor factory in Texas is set to begin production using the second-gen 3nm GAA process. The advanced packaging business has also been flourishing with orders from both domestic and international HPC clients.

Profits in the mobile panel business surged due to new flagship models from major clients. In contrast, the large panel business faced tepid demand. Samsung aims to cater to the growing mobile panel demand and increase profitability in the large panel sector by introducing new products and enhancing yield rates.

With the global economy expected to bounce back in 2024, the smartphone market's demand is anticipated to surge. High-end market growth is likely to continue, driven by the global recovery of the smartphone market.

Looking ahead to 2024, Samsung anticipates increased PC and mobile demand due to product replacement cycles initiated during the pandemic's early phase. High-density trends in both DRAM and NAND are expected to persist, propelled by on-device AI advancements. The company plans to focus on advanced node products, including 1B nanometer DDR5, LPDR5X, PCI Gen 5, and UFS 4.0, to bolster product competitiveness and profitability. Emphasizing the growing demand for generative AI, Samsung aims to strengthen its market position with high-density, low-power, and high-performance products for on-device AI, which has recently gained significant attention.

Sources;

TrendForce on X: "Samsung Electronics has released its financial results for 3Q23, reporting a quarterly revenue of 67.40 trillion Korean won—a 12% QoQ increase but 12% YoY decrease. The company achieved its highest quarterly profit of the year and anticipates that, despite ongoing global economic… https://t.co/RDKVjimgzN" / X (twitter.com)

Samsung Electronics Co Ltd (SSNLF) Q3 2023 Earnings Conference Call Transcript | Seeking Alpha

Micron's Distinct Approach to DRAM and Apple Design Wins

The tech landscape has seen consistent advancements, especially with the D1β (D1b) DRAM generation. Micron's D1β LPDDR5 16 Gb DRAM chips, integrated into the Apple iPhone 15 Pro, represent a significant step forward. Codenamed Y52P die, this chip offers an improved form factor and density, especially when contrasted with its LPDDR5/5X D1α 16 Gb predecessor. The integration of these chips into Apple's flagship device marks a significant design win for Micron, emphasizing the trust and partnership between the two tech giants.

In a recent teardown of the Apple iPhone 15 Pro, TechInsights has discovered a remarkable find - Micron's cutting-edge D1β LPDDR5 DRAM chips. These chips mark the industry's first foray into the D1β generation, and they are nothing short of impressive. (LINK)

Micron's technological direction is unique, especially with their decision to forego the Extreme Ultraviolet Lithography (EUVL) process, common in sub-15nm DRAM scaling. This stands in contrast to industry giants like Samsung and SK Hynix, who employ EUVL in their DRAM fabrication. Despite this, Micron has successfully launched the D1z, D1α, and D1β DRAM chips without EUVL, illustrating an alternative yet effective DRAM scaling approach.

In wrapping up, while Samsung and SK Hynix utilize EUVL in their DRAM processes, Micron has carved a different path, further solidified by their design wins with Apple. This partnership not only underscores Micron's technological prowess but also indicates the potential of varied methodologies in shaping the future of DRAM technology.

Source: Micron's D1β LPDDR5 Chip: Great Advancements in Memory Technology | Semiconductor Materials and Equipment (abachy.com)

Micron Unveils Breakthrough NVDRAM: A Dual-Layer 32Gbit Non-Volatile Ferroelectric Memory with Near-DRAM Performance

At the upcoming International Electron Devices Meeting (IEDM), Micron is set to present a paper on a novel 32Gbit non-volatile ferroelectric memory, termed NVDRAM. Authored by Nirmal Ramaswamy, the vice president of advanced DRAM and emerging memory at Micron, the paper is titled "NVDRAm: A 32Gbit Dual Layer 3D Stacked Non-Volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI Workloads". It introduces the world’s first dual-layer, high-performance, 32Gbit stackable ferroelectric memory technology. This technology, branded as non-volatile dynamic random access memory (NVDRAM), promises faster data movement and better energy efficiency than traditional DRAM, making it ideal for larger neural network models.

NVDRAM merges the benefits of ferroelectric memory cells – non-volatility and high endurance – with performance surpassing NAND flash memory retention and offering DRAM-like read/write speeds. The memory's architecture uses a 5.7nm ferroelectric capacitor for charge retention in a 1T1C DRAM structure, while dual-gated polycrystalline silicon transistors control access. The stacked double memory layer resides above a CMOS access circuit layer on a 48nm pitch. Despite the technological advancements, commercialization discussions remain speculative, potentially awaiting feedback from the IEDM presentation.

The images above show the final die layout (left) and SEM cross-section (center) of a 32Gb NVDRAM with 1T1C memory layers, fabricated over a CMOS array. On the right is a schematic diagram of NVDRAM memory arrays, showing polysilicon access device with orthogonal wordline (WL) and digitline (DL), and ferroelectric memory cells.

Abstract: Non-Volatile Ferroelectric w/DRAM-Like Performance, for AI & Machine Learning: Rapid growth in the size of the data models used in artificial intelligence (AI) and machine-learning (ML) applications is creating an urgent need for higher-bandwidth memory solutions. While new compute paradigms like near-memory-compute and processing-in-memory are being investigated, the best near-term opportunity is to outfit existing, traditional compute architectures with more efficient memory for faster data movement and to accommodate larger models. In this year’s Generative AI Focus Session, Micron researchers will unveil a memory technology for these uses which they call NVDRAM. It is the world’s first dual-layer, high-performance, high-density (32Gb), stackable and nonvolatile ferroelectric memory technology. It combines the non-volatile, high-endurance nature of ferroelectric memory cells with DRAM-like read/write speeds and endurance, and also surpasses the retention performance of NAND memory. NVDRAM uses an ultra-scaled (5.7nm) ferroelectric capacitor as the memory cell, and a dual-gated, stackable, polycrystalline silicon transistor as the access device. To achieve high memory density, two memory layers are fabricated above CMOS circuitry in a 48nm pitch, 4F2 architecture. Full package yield is demonstrated from -40°C to 95°C, along with reliability of 10 years (for both endurance and retention).

Sources:

eeNews: IEDM: Micron to present DRAM-like non-volatile memory for AI ... (eenewseurope.com)

IEDM Paper: 15.7_Non-Volatile Ferroelectric with DRAM-Like Performance, for AI & Machine Learning_Micron.docx (egnyte.com)

TechInsights Discovers Micron's Cutting-Edge D1β LPDDR5 16 Gb DRAM Chips in Apple iPhone 15 Pro: Setting a New Standard in Memory Technology

TechInsights has confirmed Micron's cutting-edge D1β LPDDR5 16 Gb DRAM chips in the Apple iPhone 15 Pro, marking the industry's first venture into the D1β generation. These chips are smaller and denser than their predecessors, showcasing significant advancements in DRAM technology. Notably, Micron has achieved this without utilizing Extreme Ultraviolet Lithography (EUVL), a technique employed by competitors like Samsung and SK Hynix for their DRAM processes. This achievement highlights Micron's dedication to pushing the boundaries of DRAM technology, emphasizing innovation and efficiency in the tech landscape. Micron's groundbreaking D1β LPDDR5 16 Gb DRAM chip promises to reshape the future of memory technology, setting a new standard for the industry.

(Source Micron.com)

1-BETA includes cool stuff

High-k/Metal Gate

Micron's 1β fabrication process uses the company's 2nd generation high-K metal gate (HKMG) and is said to increase bit density of a 16Gb memory die by 35% as well as to improve power efficiency by 15% when compared to a similar DRAM device made on the company's 1α node

Pitch multiplication without the need for EUV Lithography

Micron's use of proprietary multi-patterning lithography involves advanced techniques for defining circuit patterns on semiconductor wafers with the highest precision. This approach allows Micron to create intricate patterns on the chips, achieving higher memory capacity in a smaller footprint. It enables the company to fit billions of memory cells on a chip that's roughly the size of a fingernail. 

While the semiconductor industry has been transitioning to extreme ultraviolet lithography (EUVL) to overcome technical challenges in patterning, Micron has opted for its multi-patterning lithography approach. This choice showcases Micron's expertise and innovation in lithography techniques, enabling them to continue shrinking circuit features and achieving greater memory capacity without relying on EUVL, which is still considered an emergent technology. 

By using proprietary multi-patterning lithography, Micron not only reduces the cost per bit of data but also enables devices with small form factors, such as smartphones and IoT devices, to incorporate more memory into compact spaces. This approach underscores Micron's commitment to staying at the forefront of memory technology innovation.

"While the industry has begun to shift to a new tool that uses extreme ultraviolet light to overcome these technical challenges, Micron has tapped into its proven leading-edge nano-manufacturing and lithography prowess to bypass this still emergent technology. Doing so involves applying the company’s proprietary, advanced multi-patterning techniques and immersion capabilities to pattern these minuscule features with the highest precision," Micron explains. Thy Tran, VP Process Integration, Micron

On the heels of the news that Micron has begun shipping QS-sample LPDDR5X components developed on the new 1-beta DRAM process node to its smartphone customers, host Jim Greene welcomes Thy Tran, Vice President of DRAM Process Integration, to the Chips Out Loud Podcast to discuss the emergent technology.

Sources:

Micron LPDDR5 16 Gb Non-EUVL Chip Found in Apple iPhone 15 Pro | TechInsights

LPDRAM | LPDDR | Micron Technology

Micron Ships World’s Most Advanced DRAM Technology With 1-Beta Node | Micron Technology

(Source: TechInsights.com)

NEO Semiconductor Unveils Revolutionary 3D NAND and DRAM Innovations at Flash Memory Summit 2023

NEO Semiconductor, known for its expertise in 3D NAND flash and DRAM technologies, presented groundbreaking innovations at Flash Memory Summit 2023 in August. The full presentation can be seen on Youtube (below). CEO Andy Hsu's keynote introduced their latest creation, 3D X-DRAM™, designed to overcome DRAM's capacity limitations and replace 2D DRAM. This technology utilizes the existing 3D NAND flash process with minor modifications, streamlining development and reducing costs. Hsu also unveiled a new AI application, "Local Computing," promising a substantial enhancement in AI chip performance.

X-DRAM™ significantly reduces data latency and provides ultra-high data throughput to unleash the full potential of High-Bandwidth Memory (HBM). HBM uses many Through Silicon Via (TSV) to increase I/O bandwidth. However, the HBM data latency remains almost the same when using conventional DRAM because bit line lengths remain the same.

Furthermore, NEO Semiconductor showcased various novel memory structures derived from 3D X-DRAM™, tailored for applications like 3D NOR flash memory, 3D Ferroelectric RAM (FFRAM), 3D Resistive RAM (RRAM), 3D Magnetoresistive RAM (MRAM), and 3D Phase Change Memory (PCM). These innovations enable the transition from 2D to 3D memory cells.

Hsu underscored the significance of these technologies for the semiconductor industry, cloud providers, and enterprises, highlighting that 3D X-DRAM™ offers a high-speed, high-density, cost-effective, and high-yield solution.

The presentation addressed the challenges faced by DRAM and NAND flash memory in the context of AI applications and introduced two innovative solutions – 3D X-DRAM™ and 3D X-NAND™.

Being part of the prestigious Flash Memory Summit, NEO Semiconductor showcased its technologies at booth number 215, and interested parties had the opportunity to schedule meetings with the company at the event.

In summary, NEO Semiconductor unveiled groundbreaking advancements in 3D NAND flash and DRAM technologies at Flash Memory Summit 2023, offering solutions to critical challenges in memory performance and capacity.

Source: NEO Semiconductor to Present Its Ground-Breaking 3D NAND and 3D DRAM Architectures in Keynote Address at Flash Memory Summit 2023 - Neo Semiconductor | X-Nand

"Micron to Produce Advanced Memory Chips in Taiwan Using EUV Lithography by 2025, Reinforces Commitment to Island's Semiconductor Industry"

Micron Technology is set to begin producing memory chips in Taiwan using advanced EUV lithography technology by 2025, ahead of its other production sites. The company's local division head, Donghui Lu, confirmed this move and emphasized that Taiwan remains a top investment destination for Micron. The collaboration with Japanese and Taiwanese companies facilitated the development of this technology. 

Micron's decision to produce HBM type memory in Taiwan highlights the island's significance in its operations, accounting for up to 65% of production volumes. The advantageous Taiwanese infrastructure and the company's commitment to geographic diversification contribute to its expanding and modernizing operations. This move underscores Micron's dedication to innovation and maintaining a competitive edge in the semiconductor industry.

Source: Aroged: Micron will begin producing memory in Taiwan using EUV lithography by 2025 - Aroged

SK Hynix Leads DRAM Industry's Rebound in Q2 with Revenue Surge, Reclaims No. 2 Position

South Korea's SK Hynix Inc. has orchestrated a substantial resurgence in the DRAM chip sector during Q2, propelling itself back to the second-largest global position and surging ahead of Micron Technology Inc., which now stands third. The chipmaker achieved a nearly 50% surge in DRAM shipments, propelling its revenue to $3.44 billion in the April-June period. Notably, SK Hynix excelled in DDR5 and HBM chip shipments, products with higher average selling prices (ASPs) than standard commodity DRAM items, thus enhancing its ASP growth by 7-9% compared to the previous quarter. In contrast, market leader Samsung Electronics experienced a 7-9% ASP drop while retaining its top position, and third-place Micron sustained relatively stable ASP with DDR5 shipments. The overall DRAM industry marked a 20.4% QoQ revenue increase in Q2, signaling a potential turnaround in the sector.

SK Hynix leads DRAM industry’s Q2 revenue rebound, retakes No. 2 spot - KED Global

TechInsights found Samsung DRAM chips in Samsung Galaxy S23 with Five EUV mask layers

TechInsights found Samsung DRAM chips in Samsung Galaxy S23 with Five EUV mask layers. These are from DRAM wafers produced in the so-called D1a node (or D1α, α as in alpha)

👉https://t.co/oSv4yiHJiB
Get your products to market faster: @TechInsightsinc found next-gen #DRAM found in the #GalaxyS23. @Samsung is the first company to apply five #EUV lithography masks on DRAM D1a, the first node to fully adopt EUVL for #DRAM. Learn more. #semiconductor pic.twitter.com/2Pqg7gKuE9

— TechInsights (@techinsightsinc) May 1, 2023

This is in line with a previous press release from Samsung (2020) so no real surprise here: Samsung Announces Industry’s First EUV DRAM with Shipment of First Million Modules – Samsung Global Newsroom

"EUV to be fully deployed from 4th-gen 10nm-class DRAM (D1a) next year"

EUV will be fully deployed in Samsung’s future generations of DRAM, starting with its fourth-generation 10nm-class (D1a) or the highly-advanced 14nm-class, DRAM. Samsung expects to begin volume production of D1a-based DDR5 and LPDDR5 next year, which would double manufacturing productivity of the 12-inch D1x wafers.

 

Samsung Electronics Is Pushing Hard to Bring Monolithic 3D DRAM to HVM by 2025

Samsung Electronics has been enjoying its DRAM market leader position for about 30 years now. To retain the position further, it has intensified its R&D of monolithic 3D DRAMs to bring them to HVM by 2025.

DRAM’s performance boost based on scaling the cell size or pitch is approaching a physical limit for cramming more cells in a limited space. Additionally, the ultra-high aspect ratio capacitors may collapse leading to compromised device reliability. Therefore, switching from current 2D DRAMs to next-generation monolithic 3D DRAMs seems inevitable.

Samsung has reportedly intensified its R&D on stacking DRAM cells on top of each other in a monolithic fashion, unlike in the case of high-bandwidth memory (HBM), wherein multiple dies are stacked atop each other.

Besides High-k/Metal Gate transistor technology, Samsung is also considering adopting FinFET or gate-all-around (GAA) technology for the DRAM cell transistor to attain better electrostatic control of the charge flow within the channel with the gate electrode.

Micron Technology and SK Hynix are also reportedly developing monolithic 3D DRAMs. Micron recently filed a patent for a monolithic 3D DRAM that is different from that of Samsung. Micron’s approach is to change the shapes of the transistor and capacitor without laying down a cell. Major equipment manufacturers such as Applied Materials and Lam Research are also developing solutions for the monolithic 3D DRAMs.

By Abhishek Kumar Thakur & Jonas Sundqvist

Source: Samsung Electronics Gearing up to Develop World’s First 3D DRAM - Businesskorea

Applied Materials MEMORY MASTER CLASS 2021 - slide deck

I missed this opportunity, however, I am grateful for Lita Shon-Roy just sending me the link to the slide deck - Tack så mycket. 

Slide deck for the Memory Class LINK

Next class up is Logic June 16, 2021 followed by more interesting topics in 2nd half 2021:

• Specialty semiconductors
• Heterogeneous design and advanced packaging
• Inspection and process control

Teaser slide (Credit Dr. Sony Varghese, Director of Strategic Marketing at at Applied Materials)

You are welcome to contact us at TECHCET (jsundqvist@techcet.com) to dig further into the future surge of materials to realize the data-driven economy:

• ALD/CVD precursors
• Metals/PVD Targets
• Photoresist
• Wet chemicals
• CMP pads & slurries
• Bulk, Rare and Speciality gases
• Wafers

Applied Materials Introduces Materials Engineering Solutions for DRAM Scaling

• New Draco™ hard mask material co-optimized with Sym3® Y etcher to accelerate DRAM capacitor scaling
• DRAM makers adopting Black Diamond®, the low-k dielectric material pioneered by Applied Materials to overcome interconnect scaling challenges in logic
• High-k metal gate transistors now being introduced in advanced DRAM designs to boost performance and reduce power while shrinking the periphery logic to improve area and cost

SANTA CLARA, Calif., May 05, 2021 (GLOBE NEWSWIRE) -- Applied Materials, Inc. today announced materials engineering solutions that give its memory customers three new ways to further scale DRAM and accelerate improvements in chip performance, power, area, cost and time to market (PPACt).

The Draco hard mask resolves this issue with a new material whose selectivity is more than 30 percent higher than conventional DRAM capacitor hard masks. It enables the deposition of a 30 percent thinner hard mask, thus decreasing the capacitor’s aspect ratio and easing the difficulty of the etch process.

The digital transformation of the global economy is generating record demand for DRAM. The Internet of Things is creating hundreds of billions of new computing devices at the edge which are driving an exponential increase in data transmitted to the cloud for processing. The industry urgently needs breakthroughs that can allow DRAM to scale to reduce area and cost while also operating at higher speeds and using less power.

Applied Materials is working with DRAM customers to commercialize three materials engineering solutions that create new ways to shrink as well as improve performance and power. The solutions target three areas of DRAM chips: storage capacitors, interconnect wiring and logic transistors. They are now ramping into high volume and are expected to significantly increase Applied’s DRAM revenue over the next several years.

Introducing Draco™ Hard Mask for Capacitor Scaling

Since over 55 percent of a DRAM chip’s die area is occupied by the memory arrays, increasing the density of these cells is the biggest lever for reducing cost per bit. Data is stored as charges in cylindrical, vertically arranged capacitors that need as much surface area as possible to hold adequate numbers of electrons. As DRAM makers narrow the capacitors, they also elongate them to maximize surface area. A new technology challenge to DRAM scaling has emerged: the etching of the deep capacitor holes threatens to exceed the limits of the “hard mask” material that acts as a stencil to determine where each cylinder is placed. If the hard mask is etched through, the pattern is ruined. Taller hard masks are not viable because as the combined depth of the hard masks and capacitor holes exceeds certain limits, etch byproducts remain and cause bending, twisting and uneven depths.

Applied Producer® XP Precision® Draco™ CVD

The solution is Draco™, a new hard mask material that has been co-optimized to work with Applied’s Sym3® Y etch system in a process monitored by Applied’s PROVision® eBeam metrology and inspection system that can take nearly half a million measurements per hour. The Draco hard mask increases etch selectivity by more than 30 percent which enables a shorter mask. Draco hard mask and Sym3 Y co-optimization includes advanced RF pulsing which synchronizes etching with byproduct removal to enable patterning holes that are perfectly cylindrical, straight and uniform. The PROVision eBeam system gives customers massive, immediate actionable data on hard mask critical dimension uniformity which is the key to capacitor uniformity. Applied’s solution provides customers with a 50-percent improvement in local critical dimension uniformity and reduces bridge defects by 100X, thus increasing yields.

Implementation of Draco for DRAM capacitors. (Applied Materials Master Memory Class May the 5th 2021 LINK)

“The best way to quickly solve materials engineering challenges with our customers is to co-optimize adjacent steps and use massive measurements and AI to optimize process variables,” said Dr. Raman Achutharaman, group vice president, Semiconductor Products Group at Applied Materials.

Bringing Black Diamond® Low-k Dielectric to the DRAM Market

A second key lever of DRAM scaling is reducing the die area needed by the interconnect wiring that routes signals to and from the memory arrays. Each of the metal lines is surrounded by an insulating dielectric material to prevent interference between data signals. For the past 25 years, DRAM makers have used one of two silicon oxides – silane and tetraethoxysilane (TEOS) – as the dielectric material. Continual thinning of the dielectric layers has reduced DRAM die sizes but created a new technology challenge: the dielectrics are now too thin to prevent capacitive coupling in the metal lines whereby signals interfere with one another causing higher power consumption, slower performance, increased heat and reliability risks.

The solution is Black Diamond®, a low-k dielectric material first used in advanced logic. With DRAM designs now experiencing similar scaling challenges, Applied is adapting Black Diamond to the DRAM market and making it available on the highly productive Producer® GT platform. Black Diamond for DRAM enables smaller, more compact interconnect wires that can move signals through the chips at multi-gigahertz speeds without interference and at lower power consumption.

High-k Metal Gate Transistors Bring PPAC Improvements to DRAM

A third key lever of DRAM scaling is improving the performance, power, area and cost of the transistors used in the periphery logic of the chip to help drive the input-output (I/O) operations needed in high-performance DRAM like those based on the new DDR5 specification.

Until today, DRAM used transistors based on polysilicon-oxide which were phased out in foundry-logic by the 28-nanometer node because extreme thinning of the gate dielectric allowed electrons to leak, thereby wasting power and limiting performance. Logic makers adopted high-k metal gate (HKMG) transistors, replacing the polysilicon with a metal gate and the dielectric with hafnium oxide, a material that improves gate capacitance, leakage and performance. Now memory makers are designing HKMG transistors into advanced DRAM designs to improve performance, power, area and cost. In DRAM as in logic, HKMG will increasingly replace polysilicon transistors over time.

This technology inflection in DRAM creates growth opportunities for Applied Materials. The more complex and delicate HKMG materials stack is challenging to manufacture, and in-vacuum processing of adjacent steps using Applied’s Endura® Avenir™ RFPVD system has become the industry’s preferred solution. HKMG transistors also benefit from Applied’s epitaxial deposition technologies such as Centura® RP Epi along with film treatments including RadOx™ RTP, Radiance® RTP and DPN which are used to fine-tune the transistor characteristics for optimum performance.

“Draco hard mask and Black Diamond low-k dielectric are being adopted by leading DRAM customers, and the first HKMG DRAMs are now being introduced,” added Dr. Achutharaman. “Applied Materials projects billions of dollars in revenue growth as these DRAM inflections play out over the next several years.”

Additional information about the growth outlook for these technologies is being provided at Applied’s 2021 Memory Master Class being held later today. For more information, please visit the investor page of our website at https://ir.appliedmaterials.com.