Thursday, July 29, 2021

Picosun delivers ALD Morpher 200 mm Batch Cluster tool to ams OSRAM

ESPOO, Finland, 28th of July 2021 – Picosun Group delivers cutting-edge Atomic Layer Deposition (ALD) technology to ams OSRAM for volume manufacturing of optical semiconductor devices.

ams OSRAM has invested in a fully automated PICOSUN® Morpher production cluster, which can deposit multiple materials on a batch of wafers even during the same process run. The flexibility and process variety of the PICOSUN® Morpher system is a key advantage, which enables volume production as well as the testing of new processes for R&D of future products.


Picosun Group and ams OSRAM have collaborated in a public funded project FLINGO (m-era.net project) to develop new ALD materials and processes to improve the characteristics of LEDs, such as efficiency and durability. The collaboration between the parties will continue after the ALD system delivery with activities to further expand the use of ALD in optoelectronic semiconductor processing.

“We have been working with Picosun since 2010 and now with this investment we can bring our collaboration to the next level. We are very excited to have the PICOSUN™ Morpher F cluster platform installed in our cleanroom”, states Dr. Sebastian Taeger, at ams OSRAM.

“The optical semiconductor market is one focus area of Picosun today. It is a fast-growing market where we have a strong presence with our tailored solutions for compound semiconductor-based devices. We have had excellent collaboration with the ams OSRAM technical team during project FLINGO and during the system specification stage. The expertise from both companies has resulted in optimized ALD solutions to boost the performance of the customer’s products.”, continues Dr. Christoph Hossbach, General Manager of Picosun Europe GmbH.

Friday, July 23, 2021

PlasticARM - A natively flexible 32-bit Arm microprocessor using ALD

Woah - PlasticARM 32-bit microprocessor using ALD and other thin film deposition techniques on a flexible substrate.

A natively flexible 32-bit Arm microprocessor using ALD

John Biggs, James Myers, Jedrzej Kufel, Emre Ozer, Simon Craske, Antony Sou, Catherine Ramsdale,
Ken Williamson, Richard Price & Scott White
Nature volume 595, pages532–536 (2021)

Abstract: Nearly 50 years ago, Intel created the world’s first commercially produced microprocessor—the 4004, a modest 4-bit CPU (central processing unit) with 2,300 transistors fabricated using 10 μm process technology in silicon and capable only of simple arithmetic calculations. Since this ground-breaking achievement, there has been continuous technological development with increasing sophistication to the stage where state-of-the-art silicon 64-bit microprocessors now have 30 billion transistors (for example, the AWS Graviton2 microprocessor, fabricated using 7 nm process technology). The microprocessor is now so embedded within our culture that it has become a meta-invention—that is, it is a tool that allows other inventions to be realized, most recently enabling the big data analysis needed for a COVID-19 vaccine to be developed in record time. Here we report a 32-bit Arm (a reduced instruction set computing (RISC) architecture) microprocessor developed with metal-oxide thin-film transistor technology on a flexible substrate (which we call the PlasticARM). Separate from the mainstream semiconductor industry, flexible electronics operate within a domain that seamlessly integrates with everyday objects through a combination of ultrathin form factor, conformability, extreme low cost and potential for mass-scale production. PlasticARM pioneers the embedding of billions of low-cost, ultrathin microprocessors into everyday objects.


a, The SoC architecture, showing the internal structure, the processor and system peripherals. The processor contains a 32-bit Arm Cortex-M CPU and a Nested Vector Interrupt Controller (NVIC), and is connected to its memory through the interconnect fabric (AHB-LITE). Finally, the external bus interface provides a General-Purpose Input-Output (GPIO) interface to communicate off-chip with the test framework. b, Features of the CPU used in PlasticARM compared to those of the Arm Cortex-M0+ CPU. Both CPUs fully support Armv6-M architecture with 32-bit address and data capabilities and a total of 86 instructions from the entire 16-bit Thumb and a subset of 32-bit Thumb instruction set architecture. The CPU microarchitecture has a two-stage pipeline. The registers are in the CPU of the Cortex-M0+, but in the PlasticARM the registers are moved to the latch-based RAM in the SoC to save the CPU area of the Cortex-M. Finally, both CPUs are binary compatible with each other and to other CPUs in the same architecture family. c, The die layout of PlasticARM, denoting the key blocks in white boxes such as the Cortex-M processor, ROM and RAM. d, The die micrograph of PlasticARM, showing the dimensions of the die and core areas. From: A natively flexible 32-bit Arm microprocessor

Green CVD—Toward a sustainable philosophy for thin film deposition by chemical vapor deposition

Thin films of materials are critical components for most areas of sustainable technologies, making thin film techniques, such as chemical vapor deposition (CVD), instrumental for a sustainable future. It is, therefore, of great importance to critically consider the sustainability aspects of CVD processes themselves used to make thin films for sustainable technologies. Here, we point to several common practices in CVD that are not sustainable. From these, we offer a perspective on several principles for a sustainable, “Green CVD” philosophy, which we hope will spur research on how to make CVD more sustainable without affecting the properties of the deposited film. We hope that these principles can be developed by the research community over time and be used to establish research on how to make CVD more sustainable and that a Green CVD philosophy can develop new research directions for both precursor and reactor design to reduce the precursor and energy consumption in CVD processes.




Electrical energy consumption and greenhouse gas emission in 300 mm logic wafer production for relevant technology nodes in production in 2021 and to be ramped up in the next five years.

We foresee a new research field focused on developing more sustainable CVD processes without impacting the performance of the deposited film negatively. To develop this, we suggest an adaption of a philosophy similar to Green Chemistry,8 a philosophy for all areas of chemistry and chemical engineering to make more sustainable processes and products. Green chemistry focuses on reducing the amount of hazardous materials used and generated, the amount of energy consumed, and designing less harmful molecules. Here, we outline suggestions for such a Green CVD philosophy

A Green CVD philosophy needs to focus on reducing the total energy consumption, reducing molecular consumption by increasing the efficiency in atom usage, and reducing the use of and formation of hazardous molecules. This should be done for the whole process chain of a CVD process—from precursor synthesis to waste gas abatement. A sustainable CVD process must also take an active stand against human rights abuse throughout the whole materials chain, use renewable energy for CVD equipment, and make use of the excess heat produced by CVD equipment. 

Summary of a suggested Green CVD philosophy

From this breakdown of the CVD process, we suggest the following principles to summarize a sustainable Green CVD philosophy:
(1) Use precursors that can be supplied to the process in close to the stoichiometric ratios in the target film to reduce molecular waste.
(2) Use precursors that undergo reactions with lower activation energies to reduce energy consumption and molecular waste.
(3) Use less hazardous precursor molecules to make the CVD process safer.
(4) Use precursors that produce less harmful by-products that are easier to handle.
(5) Minimize waste and energy consumption in the precursor supply chain.
(6) Minimize the thermal budget and vacuum volume of the CVD reactors.
(7) Use the most energy-efficient way to activate the deposition chemistry, including plasma methods.
(8) Recycle unconsumed CVD gases and precursors.
(9) Identify, prevent, address, and account for human rights abuses in the CVD supply chain.
(10) Use renewable energy for the CVD process and harvest excess heat.

Finally, we appreciate that industry is reluctant to change precursors and CVD processes that have been successfully brought into high volume production. As we have already pointed out, the research area of Green CVD should strive to make a given CVD process more sustainable without causing negative effects on the performance of the deposited film. Ideally, Green CVD should not affect the price of the CVD processing step either. It is very reasonable to expect that the demands for more sustainable production will increase and with that a need for more sustainable CVD. As in other research, a strong collaboration between industry and academia will strengthen the Green CVD development effort.
Full article in JVSTA: 

Green CVD—Toward a sustainable philosophy for thin film deposition by chemical vapor deposition
Journal of Vacuum Science & Technology A 39, 051001, (2021); https://doi.org/10.1116/6.0001125  Henrik Pedersen, Seán T. Barry, and Jonas Sundqvist


 

Thursday, July 22, 2021

Wafer-level uniformity of atomic-layer-deposited niobium nitride thin films for quantum devices

Research showing the potential for Plasma Enhanced ALD to scale up superconducting Quantum circuits from Jena and Karlsruhe, Germany using Oxford Instruments Plasma ALD.

Abstract: Superconducting niobium nitride thin films are used for a variety of photon detectors, quantum devices, and superconducting electronics. Most of these applications require highly uniform films, for instance, when moving from single-pixel detectors to arrays with a large active area. Plasma-enhanced atomic layer deposition (ALD) of superconducting niobium nitride is a feasible option to produce high-quality, conformal thin films and has been demonstrated as a film deposition method to fabricate superconducting nanowire single-photon detectors before. Here, we explore the property spread of ALD-NbN across a 6-in. wafer area. Over the equivalent area of a 2-in. wafer, we measure a maximum deviation of 1% in critical temperature and 12% in switching current. Toward larger areas, structural characterizations indicate that changes in the crystal structure seem to be the limiting factor rather than film composition or impurities. The results show that ALD is suited to fabricate NbN thin films as a material for large-area detector arrays and for new detector designs and devices requiring uniform superconducting thin films with precise thickness control.



Wafer-level uniformity of atomic-layer-deposited niobium nitride thin films for quantum devices
Journal of Vacuum Science & Technology A 39, 052401 (2021); https://doi.org/10.1116/6.0001126

Wednesday, July 7, 2021

Friday, July 2, 2021

Future foldable and flexible Display with NCD’s ALD encapsulation technology

In the global market of smart phones, competition on mobile’s form factors has been an important issue since foldable smart phones had launched following cured ones. Samsung electronics applied in-folding form factor to Galaxy Fold and Galaxy Z Flip, and Huawei used out-folding form factor to Mate X. New two or three folding form factor has been unveiling to the public beyond in-folding and out folding displays.

Flexible displays consist of Thin Film Transistor (TFT), Organic Light Emission Diode (OLED) and multi encapsulation layers. Generally organic and inorganic laminated layers is used for foldable displays and PECVD has applied to deposit inorganic materials.

Basically, Inorganic layers is lack of brittleness then their encapsulation property is degraded with continuous mechanical stress. ALD method for TFE was considered instead of PECVD due to their excellent encapsulation characteristics with thicknesses of few tens of nanometers. The reliability of the tool blocked applying to production at that time.

But because of the superior encapsulation property using ALD, many universities, institutes as well as display companies have been developing ALD inorganic layers for flexible displays and evaluating hundreds of thousand times folding test considering actual use recently.

LucidaTM GD Series ALD


The customer which has NCD’s Lucida GD Series ALD, measured folding test on flexible displays with inorganic layers using ALD instead of using PECVD and showed great performance under actual display operation. The 5.85 inch AMOLED display panels for in-folding and out-folding consisted of encapsulation structure of 30nm Al2O3 ALD/ 8㎛-Polymer/ 30nm Al2O3 and was tested in-folding and out-folding evaluation of 200,000 times with bending radius of 2R under light status after the 1st reliability test of RA 60℃/90% for 500hr. There were no dark spots on the panels after finishing the folding measurement. The 2nd reliability test of RA 60℃/90% for 48hr followed folding evaluation and then the TFE status was examined without any cracks.


Using NCD’s large area batch ALD system for foldable phones could obtain superior encapsulation property and flexibility with very thin inorganic layers to current ones using PECVD as well as provide great productivity because the batch tool can process lots of panels at one time.

Then NCD really looks forward to applying its large area batch ALD technology to encapsulation of future flexible display with in/out-folding and very small bending radius because of having solved the previous issues without both reliability and productivity that the reason is why ALD equipment didn’t apply for mass production of flexible display.

Thursday, July 1, 2021

Picosun’s PicoArmour(TM) reduces semiconductor manufacturing costs

ESPOO, Finland, 2nd of June 2021 – Picosun Group has pending patent rights for an ALD enabled corrosion protection solution against plasma etch that will bring benefits in semiconductor fabrication processes in terms of throughput, film uniformity and conformality. With PicoArmourTM the corrosion protection can be achieved more efficiently compared with the industry solutions commonly used today.

Wafer fabrication process flows include several steps where plasma etching is necessary. An inevitable consequence of using etching chemicals is that the tool itself will be etched. A common industrial solution for reducing the tool damage is applying a corrosion-resistant coating to the etch tool using for example PVD or spray coating​ with Y2O3. Compared to only using Y2O3, PicoArmour(TM) enables an up to five times faster and a more cost-effective way of producing the coating. Compared to Al2O3, the coating can be five times more durable.* Also, the maintenance interval of etch tools can be increased which also translates to significant reduction of manufacturing costs.


“Picosun’s approach with PicoArmour(TM) is to combine the highly-etch-resistant Y2O3 ALD process with more robust ALD processes. A high performance ALD corrosion barrier combining the speed and convenience of Al2O3 process with the durability of Y2O3 can be achieved by carefully controlling the film composition. With ALD, the protective effect can be achieved with thinner films, which in turn leads to material savings and a more environmentally friendly process”, states Juhana Kostamo, VP, Industrial Business Area of Picosun Group.

To learn more about PicoArmour(TM) and a study Picosun has done related to protective coatings against plasma damage, join Picosun talk at the virtual ALD 2021 conference on June 29 at 10:25 am EDT.

Tier 1 semiconductor automotive supplier selects Oxford Instruments Plasma Technology’s ALE technology for it’s GaN power electronic program

Oxford Instruments Plasma Technology announced May 25, 2021, (LINK) that a leading German semiconductor manufacturer to the automotive industry has selected its PlasmaPro®100 Cobra® system for the development of next generation GaN power electronic devices.

The PlasmaPro®100 Cobra® system is designed for superior uniformity, high- precision and low-damage process solutions. The production-proven system allows for rapid change between wafer sizes up to 200 mm and the cost of ownership is one of the lowest in the market.

The PlasmaPro®100 Cobra® system will be incorporated into the R&D section and will be used for development of GaN power devices. GaN power devices are gaining market share in fast charger applications and offer benefits in Electric Vehicle power management systems.

We continue to see very encouraging signals in the form of increasingly proactive customer engagement and clear market preparation and positioning activities from significant industry players for the emerging Wide Band Gap power electronic market.

"Our Atomic Scale Processing etch solution being selected by this world leading manufacturer for their GaN power electronics programme is an important strategic win for Oxford Instruments Plasma Technology" comments Klaas Wisniewski, Plasma Technology’s Strategic Business Development Director, who also added: "The GaN based power electronic market is very dynamic with improvements to both performance and cost expected at each design iteration.. This reiterates the importance of our strategy to focus on atomic scale processing solutions such as atomic layer deposition (ALD) and atomic layer etching (ALE). We are pleased that such a leading automotive semiconductor company recognizes the benefits our solutions deliver.





The PlasmaPro 100 ALE delivers precise process control of etching for next-generation semiconductor devices. Specially designed for processes such as recess etching for GaN HEMT applications and nanoscale layer etching, the system's digital/cyclical etch process offers low damage, smooth surfaces.

  • Digital/Cyclical etch process – etching equivalent of ALD
  • Low damage
  • Smooth etch surface
  • Superb etch depth control
  • Ideal for nanoscale layer etching (e.g. 2D Materials)
  • Wide range of processes and applications

Wednesday, June 30, 2021

Congratulations to 2021 ALD Innovator Awardee Stacey Bent (Stanford University, USA)!

The ALD conferences for the next coming years were just announced!

The AVS ALD and ALE conferences for the next coming years were just announced!

2022 - Ghent, Belgium
2023 - Bellevue, Washington, USA
2024 - Helsinki, Finland

2024 is the year when ALD celebrates 50 years since Dr Suntolas famous patent and also celebrates all great ALD persons that turn fifty that year. 




Thursday, June 24, 2021

Picosun strengthens its presence in Southeast Asia

ESPOO, Finland, 24th June 2021 – Picosun Group extends its global sales and service partner network further by signing a partner agreement with Hermes-Epitek Corporation Pte. Ltd. Hermes-Epitek Corporation, headquartered in Taiwan, is one of the world’s largest high-tech equipment distributors. The company provides equipment for semiconductor and optoelectronic manufacturing, as well as tech services and parts sales.


“We look forward to cooperate as Picosun’s sales representative and external field service provider targeting both 8-inch and 12-inch ALD markets in all Southeast Asia countries”, states Teo Kim Leong, Director, Hermes-Epitek Corporation.

“Southeast Asia is one of Picosun’s important market areas, where the demand for industrial ALD solutions is constantly increasing. For almost ten years now, Picosun has successfully provided world leading ALD solutions to numerous customers and partners in both academies and industries in Southeast Asia. I’m happy that with the partnership with Hermes-Epitek Corporation we are able to serve our customers in the region even better”, says Edwin Wu, CEO, Picosun Asia Pte. Ltd.

Picosun provides the most advanced AGILE ALD® (Atomic Layer Deposition) thin film coating solutions for global industries. Picosun’s ALD solutions enable technological leap into the future, with turn-key production processes and unmatched, pioneering expertise in the field – dating back to the invention of the technology itself. Today, PICOSUN® ALD equipment are in daily manufacturing use in numerous leading industries around the world. Picosun is based in Finland, with subsidiaries in Germany, USA, Singapore, Japan, South Korea, China mainland and Taiwan, offices in India and France, and a world-wide sales and support network. Visit www.picosun.com.

More information:
Edwin Wu
CEO
Picosun Asia Pte. Ltd.
Tel. +358 40 480 3449

Thursday, June 17, 2021

Picosun is part of world's first wooden satellite coated by ALD

Picosun is part of world's first wooden satellite, Wisa Woodsat, launched to space during this year. The wood used in the satellite is ALD coated with Picosun tools to make the wood impermeable and meet the requirements of the most demanding environment.

WISA WOODSAT is a nanosatellite based on the popular CubeSat standard. The satellite measures roughly 10 x 10 x 10 cm, which is equivalent of 1U CubeSat. The satellite is designed and built in Finland and it will be launched to space during the fall of 2021 with a Rocket Lab Electron rocket from the Mahia Peninsula launch complex in New Zealand.

The mission of the satellite is to test the applicability of wooden materials, especially WISA-Birch plywood in spacecraft structures and expose it to extreme space conditions, such as heat, cold, vacuum and radiation, for an extended period of time.

Source: WISA WOODSAT (LINK)






Saturday, June 12, 2021

Vinova fund Swedish AlixLabs Breakthrough green technology in Nanostructures Miniaturization for Electronic Chips

Vinnova has decided to grant AlixLabs application to Innovative Startups step 2 "Breakthrough green technology in Nanostructures Miniaturization for Electronic Chips" in the spring of 2021. 140 applications were received for the call, of which 35 were given grants. The assessment is based on a weighting of the six main criteria Relevance, Potential, Team, Implementation, Sustainability, and Gender Equality. The applications have been assessed in competition with each other. AlixLabs application was judged to meet the criteria to a great extent. 

AlixLabs aim to validate our breakthrough green technology for nanofabrication of nanostructures for applications in electronic chips. It is to demonstrate that Alixlabs' method is technically viable for the production of low dimensional transistors down to 2 nm node size, in line with the newly designed European Flagship "A European Initiative on Processors and semiconductor technologies" (LINK) to develop next-generation chips and 2 nm technology with €146.5 B, supported by 22 EU members. This demonstration will minimize the risks for AlixLabs entering the semiconductor industry market and ecosystem.



Miniaturization of electronic components, known as Moore's law, is fundamental to the entire IT explosion leading to the fast processing of data. Production of sub 10 nm chips requires advanced equipment such as extreme UV lithography (EUVL) tools, costing over €100 million, not affordable to all manufacturing companies or adding extreme investment cost for those companies still in the scaling race. Our innovative patented technology (WO2017157902A1) enables miniaturization without requiring or reducing the number of process steps using costly EUVL. This way, less financially powerful manufacturers (fabs) can get back to semiconductor production chains on level terms with large competitors from the USA and Asia. Our technology uses Atomic Layer Etching (ALE) for pitch splitting of nanostructures, which allows for efficient and high-volume nanopatterning and offers to reduce operating cost up to 35 - 50% and energy use and greenhouse emissions by 25 - 50% per Lithography mask layer requiring advanced Immersion base multiple patterning technology or EUVL single and double exposure.

BREAKTHROUGH DEVELOPMENTS

We envision two breakthrough developments in this project:

(1) Application of ALE pitch splitting nanofabrication for electronic chip manufacturing down to 2 nm Foundry node size
(2) Demonstration of first transistors produced by ALE pitch splitting

Vinnova is the Swedish government agency that administers state funding for research and development. The agency's mission as defined by the government is to promote the development of efficient and innovative Swedish systems within the areas of technology, transportation, communication and labour.

About AlixLabs AB:

AlixLabs (www.alixlabs.com) is an innovative startup enabling the semiconductor industry to scale down Logic and Memory components in a cost-effective manner by the use of ALE Pitch Splitting (APS).

Background Information:





Applied Materials to present New Innovations Needed to Continue Scaling Advanced Logic (June 16)

Applied Materials (Santa Clara, USA): The semiconductor industry is at a crossroads. Demand for chips has never been greater as we enter the early stages of a new wave of growth fueled by the Internet of Things, Big Data and AI. At the same time, it’s become apparent that conventional Moore’s Law 2D scaling techniques are no longer able to deliver the consistent improvements in power, performance, area-cost and time to market (PPACt) that chipmakers have long relied on. This is particularly the case for logic chips, which serve as the main processing engine in nearly every electronic product and where power efficiency and performance are critical.

To shed light on this issue, Applied Materials is hosting an online Logic Master Class on Wednesday, June 16. I will be joined by other experts from Applied and the industry to discuss the logic scaling roadmap, including challenges and solutions for delivering continued improvements in PPACt. We will be exploring several different areas, including transistor and interconnect scaling, patterning and design technology co-optimization (DTCO). The common denominator underlying all of these areas is the need to supplement classic 2D scaling with a combination of approaches that includes new chip architectures, new 3D structures, novel materials, new ways to shrink features and new ways to connect chips with advanced packaging.

Source: Applied Materials Blog (LINK)


Primary modules of a FinFET are channel and shallow trench isolation (1), high-k metal gate (2) and transistor source/drain resistance (3). (Credit: Applied Materials)

Wednesday, June 2, 2021

Picosun’s PicoArmour(TM) reduces semiconductor manufacturing costs

ESPOO, Finland, 2nd of June 2021 – Picosun Group has pending patent rights for an ALD enabled corrosion protection solution against plasma etch that will bring benefits in semiconductor fabrication processes in terms of throughput, film uniformity and conformality. With PicoArmourTM the corrosion protection can be achieved more efficiently compared with the industry solutions commonly used today.
Wafer fabrication process flows include several steps where plasma etching is necessary. An inevitable consequence of using etching chemicals is that the tool itself will be etched. A common industrial solution for reducing the tool damage is applying a corrosion-resistant coating to the etch tool using for example PVD or spray coating​ with Y2O3. Compared to only using Y2O3, PicoArmourTM enables an up to five times faster and a more cost-effective way of producing the coating. Compared to Al2O3, the coating can be five times more durable.* Also, the maintenance interval of etch tools can be increased which also translates to significant reduction of manufacturing costs.

“Picosun’s approach with PicoArmourTM is to combine the highly-etch-resistant Y2O3 ALD process with more robust ALD processes. A high performance ALD corrosion barrier combining the speed and convenience of Al2O3 process with the durability of Y2O3 can be achieved by carefully controlling the film composition. With ALD, the protective effect can be achieved with thinner films, which in turn leads to material savings and a more environmentally friendly process”, states Juhana Kostamo, VP, Industrial Business Area of Picosun Group.

To learn more about PicoArmourTM and a study Picosun has done related to protective coatings against plasma damage, join Picosun talk at the virtual ALD 2021 conference on June 29 at 10:25 am EDT.
Register here.

Tuesday, June 1, 2021

South Korean equipment makers recorded mixed results in the first quarter of 2021

출처 : THE ELEC, Korea Electronics Industry Media(http://thelec.net) - South Korean equipment makers recorded mixed results in the first quarter of 2021.

  • Fab equipment vendors posted high growth, while display equipment firms underperformed.
  • Fab equipment makers benefited from aggressive spending by semiconductor companies.
  • CVD/ALD equipment companies showed good growth, see below (Jusung, Wonik IPD, Eugene Technologies

Semes, Samsung Electronics’ fab equipment subsidiary, recorded 870.6 billion won in sales, an increase of 62.3% from a year prior. It recorded 112.8 billion won in operating income, an increase of 40.5% over the same time period. The growth likely stems from Samsung starting to put in equipment to its P2 chip line at its Pyeontaek plant during the quarter. Overheat transport accounted for 60% of the sales recorded by Semes during the quarter.

SFA recorded 355.6 billion won in sales and 42.3 billion won in operating income, a drop of 3.3% and 1.6%, respectively, a year prior. Non-display business accounted for 65.1% of its sales. SFA, which previously focused on display kits, managed to record level earnings to a year prior thanks to other business areas.


Wonik IPS recorded 254.5 billion won in revenue and 24.2 billion won in operating income, a surge of 39.9% and 68.1%, respectively, from a year prior. The firm previously focused on fab equipment for use in memory chip production. But it has begun supplying kits for foundry beginning last year, which helped growth.

Eugene Technology recorded 100.7 billion won in revenue and 30.7 billion won in operating income. The company recorded an operating margin rate of 30.5%. Its LPCVD equipment supplied to SK Hynix for the latter’s M16 DRAM fab led the growth.

Jusung Engineering posted 75.3 billion won in sales in the quarter, double that of the year prior. It turned a profit from a year prior and posted 16 billion won in operating income. The company won the order for atomic layer deposition kits from SK Hynix for use in next-generation DRAMs. Jusung is the sole supplier of the kits.

Hanmi Semiconductor recorded 70.9 billion won in sales, a jump of 79% from a year prior. Its operating income increased 160% year-on-year to 19.3 billion won. It won 22 orders during the quarter. It has signed supply deals with SK Hynix, Amkor Technology Korea, ASE, NXP, Nanya, SPIL and others for a combined worth of 87 billion won.

YIK recorded 67.5 billion won in sales and 9.7 billion won in operating income, a jump of 99.7% and 177.1%, respectively, from a year prior. The firm mainly provides electrical die sorting equipment. The firm is seeing more orders from Samsung, having signed a 155.3 billion won deal with the tech giant in the first quarter alone.

South Korean fab equipment makers are expected to post solid growth throughout 2021 from increased spending this year by Samsung and SK Hynix. SK Hynix had said in the conference call for the first quarter that it plans to execute some of its spending it planned for 2022 earlier to this year.

SEMI is expecting global fab equipment spending to increase 15.5% this year to US$70 billion. Meanwhile, South Korean display equipment makers underperformed during the first quarter.

Samsung Display and LG Display have been conservative with their spending due to uncertainties surrounding the display market. But increased spending in OLED from Chinese panel makers such as BOE and Tianma staved off a huge dip in profitability.

Only few companies recorded growth, such as AP Systems, which saw sales drop 6.9% year-on-year but operating income surge 53.2% over the same time period. The company benefited from laser annealing equipment supplied to BOE for the B12 line.

Youngwoo DSP saw a surge in its operating income from supplies to its Chinese customers. KC Tech saw sales jump 21.1% but operating income remained flat. Top Engineering saw 9.6 billion won in operating loss from the 6.1 billion won operating loss posted by subsidiary Powerlogics. Dong A Eltek recorded 2.3 billion won in operating loss, though sales doubled. The firm said increased cost from the pandemic stunted growth.

Charm Engineering continued to record loss. HB Technology, Toptec and Philoptics all turned to the red. 

Local display equipment makers are expected to see a turnaround starting in the fourth quarter when Samsung Display and LG Display decide on new spending plans around the same time.


Thursday, May 27, 2021

Atomic billiards helps to understand Atomic Layer Deposition

In the beautiful German city of Münster, scientists are playing games on an atomic scale to help ALD developers understand what is going on in their process. Critical ALD parameters, such as the evolution of film closure and thickness with increasing cycle number are determined with a game of billiards at the atomic level. This game is called LEIS (Low Energy Ion Scattering), the most surface specific chemical analysis technique available to the surface scientist.

The fundamental principles behind LEIS are surprisingly simple: In an ultrahigh vacuum chamber, light charged particles (ions) are aimed at the sample where they collide with the atoms in and on the sample. These collisions obey the same laws of physics as collisions between large objects, such as balls. This means that the ions are bouncing (or scattering) back with high speed (or energy) when they collide with a heavy atom and with low energy after a collision with a light atom. The energy of the scattered ions is measured to determine the mass of the surface atoms.

Figure 1: The principle of LEIS: When ions collide with surface atoms, their energy after the collision depends on the mass of the atoms that they collided with. A LEIS spectrum shows the number of returned ions as a function of their energy. This represents the surface concentrations of different elements, sorted after their mass.

LEIS helps to develop and optimize ALD processes


We show an example of a co-operation between scientists at Tascon in Münster and the ALD experts from ASM Microchemistry Oy in Helsinki, Finland where the initial formation of a GaSb film on SiOx was investigated.

Figure 2 shows a set of LEIS spectra for the increasing number of ALD cycles recorded with Neon ions. There are two peaks due to collisions with Gallium (Ga) and Antimony (Sb) atoms in the outermost atomic layer of these samples. Antimony atoms are heavier than Gallium atoms and therefore the peak from collisions with Antimony lies at higher energy than the Gallium peak.


Figure 2: 5 keV 20Ne+ LEIS spectra of increasing cycle numbers of GaSb deposited on SiOx
As one would expect, the amount of Gallium in the outermost atomic layer is increasing continuously with increasing cycle number (from red to purple) showing how the fraction of Gallium increases in the outermost atomic layer. The Antimony behaves differently, though. After increasing initially, its signal goes through a maximum (the green spectrum), and with increasing cycle number the amount of Antimony at the surface decreases. With this valuable information, the ALD expert can optimize the deposition process.

LEIS separately analyzes the outermost atomic layer and the layers below it

As we have seen, LEIS is sensitive to the outermost atomic layer of a sample. The used noble gas ions (Helium or Neon) lose their charge as soon as they enter the material. Since the instrument can only detect ions, the neutral Helium or Neon atoms that collided in deeper layers are not detected. Therefore, the peaks in the spectrum from figure 2 represent Gallium and Antimony at the surface.

Particularly when Helium ions are used, there is a second effect. A Helium atom, that collided in deeper layers, may lose an electron as it leaves the surface. The probability for this re-ionization is small enough to recognize the peaks in the spectra, but large enough to cause an additional signal in the spectrum, as shown in figure 3, a set of spectra recorded with Helium ions from the same GaSb deposition study.

Figure 3: 7 keV 4He+ LEIS spectra of increasing cycle numbers of GaSb deposited on SiOx.
Again, we see the Gallium peak increasing and the Antimony peak going through a maximum. This time, we also see the Silicon (Si) peak decreasing with increasing cycle number, confirming that the substrate is getting covered. But we also see that with increasing cycle number shoulders appear on the left side of the Gallium and Antimony peaks (indicated by the dashed arrows).

These shoulders are caused by collisions from Gallium and Antimony atoms below the surface. The Helium atoms have slowed down while traveling through the sample on their way to and from the colliding atom. The more the shoulder extends to lower energy, the more the atoms have slowed down and the deeper the colliding atom was in the sample. The fact that the shoulders are extending more and more to the left with increasing cycle number shows that the film is getting thicker.

Since LEIS is a quantitative analysis technique, the surface fractions can be determined from the spectra. Figure 4 shows a ternary diagram for the composition of the sample surface with increasing cycle number. It clearly shows that initially Gallium and Antimony are deposited together. But as the film is almost closed, the Gallium deposition starts to dominate.


Figure 4: Ternary diagram showing the surface composition of the samples with increasing cycle number. The colors of the data points correspond to the colors of the spectra.
This example shows the value of LEIS in the study of ALD. Because of its surface specificity and the need for ever thinner films, the role of LEIS in ALD is expected to increase in the coming years.

Acknowledgement

The GaSb films in this study were kindly provided by ASM Microchemistry Oy, Helsinki, Finland.

Guest blog by Rik ter Veen and Karsten Lamann, Tascon GmbH, Münster, Germany

About the authors:

Rik ter Veen and Karsten Lamann are scientists at Tascon GmbH, a service provider and consulting company for the analysis of surfaces, films and interface for over 20 years with two locations in Germany and one in the USA. In addition to LEIS, the subject of this blog, Tascon offers surface and materials analysis with techniques such as ToF-SIMS, XPS and SEM-EDX. If you are interested in their services or have questions about LEIS, or other techniques, the authors can be contacted through their website.

Wednesday, May 26, 2021

Vaccines perfected from the atoms up - Forge Nano technology enables next-gen vaccine formulation platform using ALD

Vaccines perfected from the atoms up - Forge Nano technology enables next-gen vaccine formulation platform using Atomic Layer Deposition.


The vaccine of the future is here. Designed from the atoms up, this disruptive technology platform enables; thermally stable, combined-dose, time released, single injection vaccines!

Forge Nano platform technology is being used to develop innovative vaccines that can withstand higher temperatures, combine multiple doses, and release over time, all in one injection. Using Atomic Layer Deposition, these vaccine formulations can be controlled at the atomic level.

VitriVax, Inc. a Colorado based formulation technology company, utilizes Forge Nano’s Atomic Layer Deposition platform technology to engineer thermostable, single-shot vaccines across a broad range of indications. Using the cGMP certified PANDORA ALD tool, developed and manufactured by Forge Nano, VitriVax uses its proprietary Atomic Layering Thermostable Antigen and Adjuvant (ALTA™) technology platform to enable thermostable, single-shot vaccines, that can be applied to a wide variety of antigens and adjuvants to project against thermal and chemical degradation, and enable controlled release, incorporating prime doses + additional booster doses in a single-shot administration.

VitriVax’s vaccine formulation platform addresses both of these challenges by enabling vaccines to be made thermostable up to 70°C (158°F), and the combination of prime and boost doses into a single injection with timed release, eliminating the need for a follow up injection. The platform uses a technology called atomic layer deposition (ALD) to coat the active ingredient in the vaccine with a protective layer of adjuvant (commonly used in vaccines to stimulate immune response). That coating then slowly dissolves to release the dose inside. The current generation of ALD system in use by VitriVax operates at the scale of around 1000 doses per run. (LINK)


“In light of the current global pandemic, vaccine storage, distribution, and efficacy has never been more important. We are proud to see our platform being used to make vaccines that can be more easily transported, with more efficient and precisely controlled doses. Future technologies are being enabled by controlling things at the atomic level. Our platform is being used every day to enable precision and control at the atomic scale.” Dr. Paul Lichty- CEO Forge Nano.

Forge Nano specializes in optimizing the way surfaces interact at the atomic level. Using proprietary technology, Forge Nano can apply nano coatings onto the surface of virtually anything. Forge Nano’s platform technology unlocks a level of precision and control that is unrivaled by other surface engineering technologies.

About VitriVax, Inc:

Based in Boulder, CO, VitriVax’s mission is to eliminate barriers to global vaccination. Through its ALTA formulation platform, and driven by a world-class team of scientists, engineers and entrepreneurs with expertise in vaccine development, virology and chemical engineering, VitriVax is dedicated to significantly increasing the availability of human and animal vaccines around the world.

Thursday, May 20, 2021

Plasway, Fraunhofer IKTS and BALD Engineering to present fast SiO2 PEALD at ALD2021

Get ready for ALD/ALE 2021 and don´t miss new record-breaking fast ALD using 3D printed ceramic de Laval Rocket nozzle technology by Plasway, Fraunhofer IKTS and BALD Engineering.

♦ Realization and Dual Angle In-situ OES Characterization of Saturated 10-100 ms Precursor Pulses in a 300 mm CCP Chamber Employing de Laval Nozzle Ring Injector for Fast ALD

♦ we use two fast scanning, with ≤10 ms acquisition time per spectrum ranging from 200 nm to 800 nm, Optical Emission Spectrometers with a resolution in the range of 0.7 nm.

♦ We present the results for PEALD of SiO2 exhibiting substrate surface saturation for 30 ms of BDEAS pulse and 50 ms of O2

Realization and Dual Angle, In-situ OES Characterization of Saturated 10-100 ms Precursor Pulses in a 300 mm CCP Chamber Employing de Laval Nozzle Ring Injector for Fast ALD

Abhishekkumar Thakur1, Stephan Wege1, Sebastian Bürzele1, Elias Ricken1, Jonas Sundqvist2, Mario Krug3

1Plasway Technologies GmbH, 2BALD Engineering AB, 3Fraunhofer IKTS

ALD-based spacer-defined multiple patterning schemes have been the key processes to continued chip scaling, and they require PEALD or catalytic ALD for low temperature and conformal deposition of spacers (typically SiO2) on photoresist features for the subsequent etch-based pitch splitting. Other SiO2 applications in the logic and the memory segments include gap fill, hard masks, mold oxides, low-k oxides, hermetic encapsulation, gate dielectric, inter-poly dielectric ONO stack, sacrificial oxide, optical films, and many more. ALD is limited by low throughput that can be improved by raising the growth per cycle (GPC), using new ALD precursors, performing batch ALD or fast Spatial ALD, shrinking the ALD cycle length, or omitting purge steps to attain the shortest possible ALD cycle. Today’s latest and highly productive platforms facilitate very fast wafer transport in and out of the ALD chambers. Current 300 mm ALD chambers for high volume manufacturing are mainly top-down or cross-flow single wafer chambers, vertical batch furnaces, or spatial ALD chambers.

We have developed a Fast PEALD technology [1], realizing individual precursor pulses saturating in the sub-100 ms range. The key feature of the technology is the highly uniform, radial injection of the precursors into the process chamber through several de Laval nozzles [2]. To in-situ study (concomitantly from the top and the side of the wafer surface) individual ALD pulses in the 10-100 ms range, we use two fast scanning (≤10 ms acquisition time per spectrum ranging from 200 nm to 800 nm) Optical Emission Spectrometers with a resolution in the range of 0.7 nm.


Saturation curves for SiO2 Fast PEALD

We present the results for PEALD of SiO2 exhibiting substrate surface saturation for 30 ms of BDEAS pulse (Fig. 1) and 50 ms of O2 plasma pulse (Fig. 2). All the processes were carried out in a 300 mm, dual-frequency (2 MHz and 60 MHz) CCP reactor in the temperature range of 20 °C to 120 °C and at ~1 Torr max. pulse pressure. The in-situ, time-resolved OES study of O2 plasma pulse, indicating saturation of  O* (3p5Pà3s5S) emission peak already at 50 ms pulse duration (Fig. 3, 4) and associated extinction of reactive O* within 161 ms (Fig. 5), suggest room for yet faster process. The mean GPC diminishes with the electrostatic chuck temp (Fig. 6).

We will present a more optimized PEALD SiO2 process and stacking of Fast PEALD SiO2 on top of Fast PEALD Al2O3 in the same chamber without breaking the vacuum. The results will comprise XPS, TEM, film growth uniformity across 300 mm wafer, and residual stress investigation for the film stack.    

References:

[1] AVS ALD2020, Abstract Number: 2415, Oral Presentation: AM-TuA14

[2] Patent US20200185198A1


ALD/ALE 2021 Technical Program June 27-30, 2021

Virtual Meeting Overview & Highlights

The AVS 21st International Conference on Atomic Layer Deposition (ALD 2021) featuring the 8th International Atomic Layer Etching Workshop (ALE 2021) will be adapted into a Virtual Meeting comprised of Live and On Demand Sessions. The event will feature:

AVS ALD/ALE 2021 Conference Page 

Live Tutorial Session with live Q&A Chat Opportunities
(Sunday, June 27, 2021)

  • Parag Banerjee (University of Central Florida, USA), “Seeing Is Believing: In situ Techniques for Atomic Layer Deposition (ALD) Process Development and Diagnostics”
  • Arrelaine Dameron (Forge Nano, USA), “ALD Powder Manufacturing”
  • Henrik Pedersen (Linkoping University, Sweden), “Let’s Talk Dirty – Battling Impurities in ALD Films”
  • Riikka Puurunen (Aalto University, Finland), “Fundamentals of Atomic Layer Deposition: An Introduction (“ALD 101”)”
  • Fred Roozeboom (Eindhoven University of Technology, The Netherlands), “ALE and ALD: Two Biotopes of a Kind in Atomic-Scale Processing”

Live Plenary, Awards, and Student Finalists with live Q&A Chat Opportunities (Monday, June 28, 2021)

  • Plenary Speaker: Steven George (University of Colorado Boulder, USA), “Mechanisms of Thermal Atomic Layer Etching”
  • Plenary Speaker: Todd Younkin (Semiconductor Research Corporation, USA), “Materials & Innovation – Essential Elements that Underpin the Next Industrial Revolution
  • Live Parallel Technical Sessions with live Q&A Chat Opportunities (Tuesday-Wednesday, June 29-30, 2021)

  • On Demand Oral Sessions (Starting Monday, June 28, 2021)

  • On Demand Poster Sessions with a Mix of Pre-recorded (Video or Audio) Talks and/or PDF files

Note: Live and On Demand Sessions available on Mobile App/Online Scheduler through July 31, 2021 and then to AVS members in the AVS Technical Library. Live Sessions will also be recorded and added to the On Demand Sessions.

Thursday, May 13, 2021

Schweden wollen mit Ätz-Spalttechnik Chipproduktion in Sachsen umkrempeln

Alix Labs aus Lund testet Verfahren nun im Silicon Saxony, berichtet Heiko Weckbrodt bei Oiger.de


Lund/Bannewitz, 13. Mai 2021. Ingenieure aus Schweden und Sachsen wollen gemeinsam die Mikroelektronik-Produktion umkrempeln. Dafür hat das schwedische Technologie-Unternehmen „Alix Labs“ ein Verfahren entwickelt, das die Produktion neuester Computerchips mit Strukturgrößen unterhalb von zehn Nanometern (Millionstel Millimeter) stark vereinfachen und verbilligen soll. Dabei geht es auch darum, den Einsatz teurer Belichtungsanlagen mit „Extremer Ultraviolett-Strahlung“ (EUV) zu vermeiden, die etwa 120 Millionen Euro pro Maschine kosten und für die es weltweit nur eine Quelle gibt: ASML aus den Niederlanden. Um auf alternativen Wegen feinste Chipstrukturen zu erzeugen, setzen die Schweden auf eine „Pitch-Splitting-Methode“ (APS) mittels Atomlagen-Ätzen (Atomic Layer Etching, abgekürzt ALE). „Plasway Technologies“ aus Bannewitz in Dresden transferiert dieses Verfahren nun in einen industrienahen Maßstab auf 300 Millimeter großen Siliziumscheiben (Wafer).
Weiterlesen: LINK


„In Schweden haben wir keine 300-Millimeter-Infrastruktur“, erklärt „Alix Labs“-Chef Jonas Sundqvist die Kooperation mit den Sachsen. „Unsere Technologie kann in bestehende Prozessabläufe der Halbleiterherstellung integriert werden. Theoretisch könnten Chipfabriken wie die Globalfoundries-Fab 1 in Dresden unsere Methode einführen und dann 10- oder 7-Nanometer-Chips herstellen ohne teure EUV-Anlagen.“ Als Kunden sieht er aber auch Branchenriesen wie Intel, TSMC und Samsung.

Wednesday, May 12, 2021

A Molecular Drone for Atomic‐Scale Fabrication Working under Ambient Conditions

Pretty cool stuff going on, please check the interview of the scientist here (LINK). Thanks for sharing this one Henrik Pedersen.

A Molecular Drone for Atomic‐Scale Fabrication Working under Ambient Conditions

Matteo Baldoni Francesco Mercuri Massimiliano Cavallini
Advanced Materials Communications, First published: 12 April 2021 https://doi.org/10.1002/adma.202007150

The direct manipulation of individual atoms has led to the advancement of exciting cutting‐edge technologies in sub‐nanometric fabrication, information storage and to the exploration of quantum technologies. Atom manipulation is currently performed by scanning probe microscopy (SPM), which enables an extraordinary spatial control, but provides a low throughput, requiring complex critical experimental conditions and advanced instrumentation. Here, a new paradigm is demonstrated for surface atom manipulation that overcomes the limitations of SPM techniques by replacing the SPM probe with a coordination compound that exploits surface atom complexation as a tool for atomic‐scale fabrication. The coordination compound works as a “molecular drone”: it lands onto a substrate, bonds to a specific atom on the surface, picks it up, and then leaves the surface along with the extracted atom, thus creating an atomic vacancy in a specific position on the surface. Remarkably, the feasibility of the process is demonstrated under electrochemical control and the stability of the fabricated pattern at room temperature, under ambient conditions.

Phthalocyanine molecule can act as a ‘molecular drone’ from Chemistry World on Vimeo.

Saturday, May 8, 2021

Worldwide silicon wafer area shipments increased 4% to 3,337 million square inches in the first quarter of 2021

MILPITAS, Calif. — May 3, 2021 — Worldwide silicon wafer area shipments increased 4% to 3,337 million square inches in the first quarter of 2021 compared to the fourth quarter of 2020, topping the previous historical high set in the third quarter of 2018, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. First-quarter 2021 silicon wafer shipments saw 14% growth from the 2,920 million square inches logged during the same quarter last year.
From Semi data

“Logic and foundry continue to drive strong demand for silicon wafers,” said Neil Weaver, chairman SEMI SMG and Vice President, Product Development and Applications Engineering at Shin Etsu Handotai America. “The memory market recovery further bolstered shipment growth in the first quarter of 2021.”

Data cited in this release includes polished silicon wafers such as virgin test and epitaxial silicon wafers, as well as non-polished silicon wafers shipped to end users.

Silicon wafers are the fundamental building material for the majority of semiconductors, which, in turn, are vital components of all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin disks are produced in diameters of up to 12 inches and serve as the substrate material on which most semiconductor devices, or chips, are fabricated.

The SMG is a sub-committee of the SEMI Electronic Materials Group (EMG) and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi). The purpose of the SMG is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics on the silicon industry and the semiconductor market.

For more information, please visit SEMI Worldwide Silicon Wafer Shipment Statistics.

Webinar - Decadal Plan for Semiconductors: New Compute Trajectories for Energy Efficiency

SIA/SRC [LINK]: Computing and, more generally, Information and Communication Technologies (ICT) is the social-economic growth engine of the modern world. Rapid advances in computing have provided increased performance and enhanced features in each new generation of products in nearly every market segment, whether it be servers, PCs, communications, mobile, automotive, or entertainment, among others.

The use of information and communication technologies continues to grow without bounds dominated by the exponential creation of data that must be moved, stored, computed, communicated, secured and converted to end user information. Ever-rising energy demands for computing versus global energy production are creating new risk, therefore new computing paradigms need to be discovered that would result in dramatically improved energy efficiency of computing.

This webinar intends to identify a compelling research agenda based on the Decadal Plan for Semiconductors, led by SRC to discover new approaches to computing with a focus on changing the current mainstream compute trajectory. The underlying technical challenge is bit-utilization efficiency in computation.



Friday, May 7, 2021

BALD Engineering & Friends Virtual ALD Fest June 27-30 (tbd), 2021 with Free Beer

BALD Engineering Virtual ALD Fest June 27-30 (tbd), 2021 with Free Beer. A splendid event for everyone attending AVS ALD 2021 or ALE 2021 virtually. The Fest will be streaming live from Dresden Germany and a number of additional locations worldwide - To be announced

Agenda
1. Beer opening ceremony & Tutorial How to open a beer bottle the German way and how to pour a Hefe Weizen
2. ALD Market Briefing with beer
3. Beer drinking competition with several entries (to be announced)



Please vote on Twitter:


Applied Materials MEMORY MASTER CLASS 2021 - slide deck

I missed this opportunity, however, I am grateful for Lita Shon-Roy just sending me the link to the slide deck - Tack så mycket. 

Slide deck for the Memory Class LINK

Next class up is Logic June 16, 2021 followed by more interesting topics in 2nd half 2021:

  • Specialty semiconductors
  • Heterogeneous design and advanced packaging
  • Inspection and process control

Teaser slide (Credit Dr. Sony Varghese, Director of Strategic Marketing at at Applied Materials)

You are welcome to contact us at TECHCET (jsundqvist@techcet.com) to dig further into the future surge of materials to realize the data-driven economy:

  • ALD/CVD precursors
  • Metals/PVD Targets
  • Photoresist
  • Wet chemicals
  • CMP pads & slurries
  • Bulk, Rare and Speciality gases
  • Wafers

Applied Materials Introduces Materials Engineering Solutions for DRAM Scaling

  • New Draco™ hard mask material co-optimized with Sym3® Y etcher to accelerate DRAM capacitor scaling
  • DRAM makers adopting Black Diamond®, the low-k dielectric material pioneered by Applied Materials to overcome interconnect scaling challenges in logic
  • High-k metal gate transistors now being introduced in advanced DRAM designs to boost performance and reduce power while shrinking the periphery logic to improve area and cost
SANTA CLARA, Calif., May 05, 2021 (GLOBE NEWSWIRE) -- Applied Materials, Inc. today announced materials engineering solutions that give its memory customers three new ways to further scale DRAM and accelerate improvements in chip performance, power, area, cost and time to market (PPACt).
The Draco hard mask resolves this issue with a new material whose selectivity is more than 30 percent higher than conventional DRAM capacitor hard masks. It enables the deposition of a 30 percent thinner hard mask, thus decreasing the capacitor’s aspect ratio and easing the difficulty of the etch process.

The digital transformation of the global economy is generating record demand for DRAM. The Internet of Things is creating hundreds of billions of new computing devices at the edge which are driving an exponential increase in data transmitted to the cloud for processing. The industry urgently needs breakthroughs that can allow DRAM to scale to reduce area and cost while also operating at higher speeds and using less power.
Applied Materials is working with DRAM customers to commercialize three materials engineering solutions that create new ways to shrink as well as improve performance and power. The solutions target three areas of DRAM chips: storage capacitors, interconnect wiring and logic transistors. They are now ramping into high volume and are expected to significantly increase Applied’s DRAM revenue over the next several years.

Introducing Draco™ Hard Mask for Capacitor Scaling

Since over 55 percent of a DRAM chip’s die area is occupied by the memory arrays, increasing the density of these cells is the biggest lever for reducing cost per bit. Data is stored as charges in cylindrical, vertically arranged capacitors that need as much surface area as possible to hold adequate numbers of electrons. As DRAM makers narrow the capacitors, they also elongate them to maximize surface area. A new technology challenge to DRAM scaling has emerged: the etching of the deep capacitor holes threatens to exceed the limits of the “hard mask” material that acts as a stencil to determine where each cylinder is placed. If the hard mask is etched through, the pattern is ruined. Taller hard masks are not viable because as the combined depth of the hard masks and capacitor holes exceeds certain limits, etch byproducts remain and cause bending, twisting and uneven depths.


Applied Producer® XP Precision® Draco™ CVD

The solution is Draco™, a new hard mask material that has been co-optimized to work with Applied’s Sym3® Y etch system in a process monitored by Applied’s PROVision® eBeam metrology and inspection system that can take nearly half a million measurements per hour. The Draco hard mask increases etch selectivity by more than 30 percent which enables a shorter mask. Draco hard mask and Sym3 Y co-optimization includes advanced RF pulsing which synchronizes etching with byproduct removal to enable patterning holes that are perfectly cylindrical, straight and uniform. The PROVision eBeam system gives customers massive, immediate actionable data on hard mask critical dimension uniformity which is the key to capacitor uniformity. Applied’s solution provides customers with a 50-percent improvement in local critical dimension uniformity and reduces bridge defects by 100X, thus increasing yields.


Implementation of Draco for DRAM capacitors. (Applied Materials Master Memory Class May the 5th 2021 LINK)

“The best way to quickly solve materials engineering challenges with our customers is to co-optimize adjacent steps and use massive measurements and AI to optimize process variables,” said Dr. Raman Achutharaman, group vice president, Semiconductor Products Group at Applied Materials.



Bringing Black Diamond® Low-k Dielectric to the DRAM Market

A second key lever of DRAM scaling is reducing the die area needed by the interconnect wiring that routes signals to and from the memory arrays. Each of the metal lines is surrounded by an insulating dielectric material to prevent interference between data signals. For the past 25 years, DRAM makers have used one of two silicon oxides – silane and tetraethoxysilane (TEOS) – as the dielectric material. Continual thinning of the dielectric layers has reduced DRAM die sizes but created a new technology challenge: the dielectrics are now too thin to prevent capacitive coupling in the metal lines whereby signals interfere with one another causing higher power consumption, slower performance, increased heat and reliability risks.

The solution is Black Diamond®, a low-k dielectric material first used in advanced logic. With DRAM designs now experiencing similar scaling challenges, Applied is adapting Black Diamond to the DRAM market and making it available on the highly productive Producer® GT platform. Black Diamond for DRAM enables smaller, more compact interconnect wires that can move signals through the chips at multi-gigahertz speeds without interference and at lower power consumption.

High-k Metal Gate Transistors Bring PPAC Improvements to DRAM

A third key lever of DRAM scaling is improving the performance, power, area and cost of the transistors used in the periphery logic of the chip to help drive the input-output (I/O) operations needed in high-performance DRAM like those based on the new DDR5 specification.

Until today, DRAM used transistors based on polysilicon-oxide which were phased out in foundry-logic by the 28-nanometer node because extreme thinning of the gate dielectric allowed electrons to leak, thereby wasting power and limiting performance. Logic makers adopted high-k metal gate (HKMG) transistors, replacing the polysilicon with a metal gate and the dielectric with hafnium oxide, a material that improves gate capacitance, leakage and performance. Now memory makers are designing HKMG transistors into advanced DRAM designs to improve performance, power, area and cost. In DRAM as in logic, HKMG will increasingly replace polysilicon transistors over time.

This technology inflection in DRAM creates growth opportunities for Applied Materials. The more complex and delicate HKMG materials stack is challenging to manufacture, and in-vacuum processing of adjacent steps using Applied’s Endura® Avenir™ RFPVD system has become the industry’s preferred solution. HKMG transistors also benefit from Applied’s epitaxial deposition technologies such as Centura® RP Epi along with film treatments including RadOx™ RTP, Radiance® RTP and DPN which are used to fine-tune the transistor characteristics for optimum performance.

“Draco hard mask and Black Diamond low-k dielectric are being adopted by leading DRAM customers, and the first HKMG DRAMs are now being introduced,” added Dr. Achutharaman. “Applied Materials projects billions of dollars in revenue growth as these DRAM inflections play out over the next several years.”

Additional information about the growth outlook for these technologies is being provided at Applied’s 2021 Memory Master Class being held later today. For more information, please visit the investor page of our website at https://ir.appliedmaterials.com.