Chipmetrics Launches New Test Chips for Advanced Atomic Layer Processes

Finnish 3D thin film semiconductor metrology specialist launches new PillarHall LHAR5 test chip with 100 nanometer gap height, complements its metrology solution with new ASD-1 chip for Area Selective Deposition.

Joensuu, Finland – July 15th, 2024 – Chipmetrics Oy, an innovative metrology solutions provider to the semiconductor industry, announces the launch of two new test chips, the PillarHall LHAR5 and the ASD-1. The PillarHall LHAR5 silicon test chip builds on the success of its predecessor PillarHall LHAR4, with the new LHAR5 test chips being better suited for the most advanced 3D semiconductor device high aspect ratio structures with a gap height as low as 100 nm. Fitting seamlessly into Chipmetrics’ pocket wafer concept, it also allows for fast and accurate process control with full 300-millimeter compatibility.

The PillarHall LHAR5 test chip comes in two variations, with a 100-nanometer and a 500-nanometer gap height. The new 100-nanometer gap height allows engineers to research and compare possible dimensional effects in film penetration depth in line with 500-nanometer gap chips. This allows for new insights into film conformality control and a deeper understanding of 3D NAND, DRAM and other nanoelectronics containing high aspect ratio structures.

“With the launch of PillarHall LHAR5, ASD-1 and the 300-millimeter pocket wafer concept our product line is compatible with the most advanced and challenging semiconductor deposition and etch technologies like ALD, ALE and ASD. The Chipmetrics test chips with our pocket wafer concept is directly compatible with and ready to be used in all existing deposition tools,” says Mikko Utriainen, CEO of Chipmetrics.

The Chipmetrics ASD-1: Prototyping and Process Control for Area Selective Deposition workflows

Launched concurrently with the PillarHall LHAR5 is the Chipmetrics ASD-1 test chip, for prototyping and process control of Area Selective Deposition (ASD) workflows. As the name implies, ASD allows for selective growth of thin films on specific substrate areas, while avoiding it on others, with the ASD-1 test chip aiming to give customers easy access to high-quality data for process control and R&D.

The ASD-1 test chip features a high surface planarity, low line edge roughness, and small line widths which are crucial for ASD applications in advanced semiconductor manufacturing. The ASD-1 test chip features arrays of sub-100 nanometer narrow line structures with alternating materials aligned on the planar silicon substrate for accurately characterizing self-aligned area selective depositions through either Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD) and related processes. The Chipmetrics ASD-1 helps engineers to accelerate ASD process development to meet challenges in miniaturizing and scaling, as well as in reducing defects and improving yield.

Both the PillarHall LHAR5 and ASD-1 test chips are available immediately. For more information on the products, please visit Chipmetrics.com.

About Chipmetrics

Chipmetrics Oy develops and delivers metrology solutions for manufacturing processes for the semiconductor industry, focusing on innovative metrology chips and ALD measurement services. Its main product is the PillarHall® metrology chip for near-instantaneous thin film process conformality measurement. Founded in 2019, its head office is in Joensuu, Finland, with employees and sales partners in Japan, South Korea, USA, and Germany.

For more information, visit www.chipmetrics.com.

Press contact:

Jonas Klar

Chipmetrics Oy

jonas.klar@chipmetrics.com

pr@chipmetrics.com

Editor’s note on ALD:

Atomic Layer Deposition (ALD) is a precision thin-film deposition technique crucial for semiconductor manufacturing, enabling the production of uniform and conformal layers essential for microelectronic devices. Through alternating exposure to precursor gases that react with the substrate in a self-limiting manner, ALD achieves atomic-level control over film thickness and composition. This method ensures exceptional uniformity across complex geometries, vital for the miniaturized, multi-layered structures such as the future’s 3D chips in advanced semiconductor devices, keeping Moore’s Law alive.

Finland plays a key role in the ALD landscape, having pioneered the process in the 1970s. Finland’s contribution to ALD includes significant advancements in materials science, equipment design, and the exploration of new applications ranging from electronics to renewable energy sectors. The country’s strong emphasis on research and development in nanotechnology has positioned it as a hub for ALD innovation, fostering collaborations between academia, industry, and research organizations worldwide.

Tokyo Electron Introduces Acrevia Tool to Enhance EUV Lithography

Tokyo Electron has introduced Acrevia, a state-of-the-art gas cluster beam (GCB) system aimed at refining patterns created by EUV lithography. This advanced tool is set to reduce the necessity for EUV double patterning, thereby improving chipmaking yields and lowering production costs. Acrevia addresses critical challenges such as line edge roughness (LER), a common issue in lithography that affects the precision of pattern edges and overall chip performance. By optimizing pattern sidewalls through precise etching, Acrevia promises to significantly enhance within-wafer uniformity and mitigate LER, contributing to higher yield and better chip reliability. While not replacing High-NA EUV lithography, Acrevia marks a substantial leap forward in semiconductor manufacturing innovation.

Sources:

Tokyo Electron's new tool can reduce the necessity for EUV double patterning and improve yield | Tom's Hardware (tomshardware.com)

Tokyo Electron Launches Acrevia™, a Gas Cluster Beam System for Ultra-Fine Patterning in EUV Lithography | News Room | Tokyo Electron Ltd. (tel.com)

Chipmetrics' Metrology Workshop

This exclusive workshop provides opportunity to learn about Angstrom scale metrology of ALD thin films in ultra High Aspect Ratio structures. In addition, it gives insights of most advanced rapid analytical methods of ALD conformality.

This unique educational opportunity is being held in the fascinating venue in the lake district of Finland.

Workshop flyer and program can be downloaded from here:

https://chipmetrics.com/wp-content/uploads/2024/05/Chipmetrics%20Metrology%20Workshop-08-08-2024-flyer%20v2.pdf?_t=1716811317

Registration Fee: €650

Date: Thursday, 8th August 2024

Location: Vainoniemi villa, Joensuu, Finland

Contact us at +358 41 740 1098 or zahra.ghaderi@chipmetrics.com

Boosting the Future: Increased ALD Use Paves the Way for Advanced GAAFET Technology

The Biden administration is considering a complete ban on the export of chips utilizing Gate All-Around Field Effect Transistor (GAAFET) technology to China, Bloomberg reports (LINK). The rationale behind this potential ban is the concern that such advanced transistors could be leveraged for military applications and artificial intelligence (AI) advancements by China. This move follows previous restrictions from 2022, when the U.S. barred its Electronic Design and Automation (EDA) companies from selling tools necessary for GAAFET development to China. In addition, advanced chip exports from companies like Nvidia were restricted, with these measures being progressively tightened and expanded over time.

Atomic Layer Deposition (ALD) is celebrating its 50th anniversary in 2024. The anniversary marks 50 years since Dr. Tuomo Suntola and his colleagues filed the first patent for Atomic Layer Epitaxy in 1974, which laid the foundation for ALD technology. This milestone will be celebrated at various events, including the ALD 2024 conference, where Dr. Suntola is expected to deliver the opening remarks .

ASM International, a leader in Atomic Layer Deposition (ALD), plays a crucial role in enabling Gate-All-Around Field Effect Transistors (GAAFETs) and continued semiconductor scaling. ALD's precision in depositing ultra-thin, uniform films is essential for creating the high-performance, low-power structures required by GAAFETs. This technology, along with other advanced processes such as epitaxy and selective etching, supports the intricate fabrication steps needed for these next-generation transistors.

The production of GAAFETs requires a significant increase in the use of ALD technology - maybe up to 40% more according to ASM. ALD is essential for creating the ultra-thin, uniform films needed for GAAFET structures, ensuring high-quality, defect-free layers that are critical for advanced transistor performance. This technology enables precise control over the deposition process, crucial for developing high-k dielectrics and other materials that enhance GAAFET performance and efficiency. As the semiconductor industry now transitions from FinFET to GAAFET technology, leveraging ALD's capabilities is vital for maintaining and advancing Moore's Law, enabling more powerful and energy-efficient chips using existing manufacturing infrastructure

Applied Materials has outlined next-generation tools essential for producing 3nm and GAA transistors, such as those in Samsung's upcoming 3GAE and 3GAP technologies. These advanced tools address the complexities of GAA transistor manufacturing, including precise lithography, epitaxy, and selective materials removal. Applied's Producer Selectra Selective Etch IMS tool is pivotal in defining channel width without damaging surrounding materials, while the Centura Prime Epi tool ensures clean deposition of Si and SiGe nanosheets. Additionally, their Integrated Materials Solution (IMS) systems integrate atomic layer deposition (ALD), thermal steps, and plasma treatments to optimize the gate oxide stack, enhancing performance and reducing gate leakage. These innovations are crucial as they enable higher performance, lower power consumption, and greater transistor density, aligning with the industry's move from FinFET to GAA technology.

Today GAA transistors are currently in mass production only by Samsung, which offered the technology to customers with its 3-nanometer process in 2022. Intel is set to follow, producing GAAFET on its 2-nanometer process expected to be available in its products later this year. TSMC, the market leader, plans to introduce GAAFET with its own 2 nm process in 2025. The GAAFET technology itself is not inherently suited for AI or military applications but represents an evolution in transistor design, enabling denser packing of transistors as lithography equipment and manufacturing processes advance. This technology shift, akin to transitioning to a new node, typically results in either reduced power consumption or improved performance by 15-25%.

The improvements facilitated by GAAFET could significantly enhance the capabilities available to China. SMIC, China's largest contract manufacturer, currently produces chips on a 7 nm process and is believed to be capable of reaching at least 5 nanometers with existing tools. The combination of this process with GAAFET could theoretically prevent China from falling too far behind Western advancements. However, China has been effectively shut out from developing GAAFET using tools from leading EDA companies, all of which are American. Additionally, the Dutch company ASML, dominant in the lithography equipment market, has not sold its EUV (Extreme Ultraviolet) machines to China and faced further restrictions in 2023 on selling its advanced DUV (Deep Ultraviolet) equipment. In April 2024, ASML took another step in the tech war against China by announcing that it would no longer service existing equipment in China, potentially crippling the country's semiconductor manufacturing capabilities. The specific details of the new export bans are still unclear, but Reuters notes that initial proposals have faced criticism from the U.S. semiconductor industry for being overly broad and extensive.

Source: USA överväger ytterligare GAAFET-sanktioner mot Kina – Semi14, www.ASM.com, Applied Materials Outlines Next-Gen Tools for 3nm and GAA Transistor Era (anandtech.com), Atomic layer deposition, next-gen transistors, and ASM (techfund.one)

ASML Unveils Hyper-NA EUV: Pioneering New Frontiers in Chip Innovation and Efficiency

ASML, the leader in lithography technology for semiconductor manufacturing, has launched its latest breakthrough: the Hyper-NA EUV tool and Intel being the first customer getting its first machine earlier this year. This leading-edge technology, which boosts the numerical aperture (NA) from 0.55 to 0.75, is poised to revolutionize chip design by enabling unprecedented levels of transistor density. Scheduled for introduction around 2030, Hyper-NA promises to extend the capabilities of chipmakers far beyond current limits, opening up new possibilities for intricate and powerful chip designs.

The presentation announcing ASML's Hyper-NA EUV technology was delivered by the company's former president, Martin van den Brink, at imec's ITF World event in Antwerp. 

Reduction in Double Patterning Complexity: Hyper-NA EUV technology simplifies the lithography process by reducing the need for double patterning, i.e., like Litho-Etch-Litho-Etch (LELE) etc., a method that involves aligning two masks perfectly to create intricate chip designs. By providing higher resolution and precision, Hyper-NA EUV minimizes the challenges and costs associated with double patterning, streamlining production and enhancing overall efficiency for chipmakers. However, there are a myriad of multi-patterning technologies deployed out there and SMIC, the main Chinese foundry, is reportedly using sextuple-patterning for its 5 nm technology.

Hyper-NA EUV technology is designed to significantly increase the productivity of semiconductor manufacturing, enabling the processing of 400 to 500 wafers per hour. This improvement will help chipmakers meet the growing demand for high-performance chips more efficiently, reducing production time and costs while maintaining high precision and quality.

The adoption of Hyper-NA EUV presents a myriad of opportunities for the semiconductor industry. As Intel has already installed the first High-NA systems, showcasing the potential of these advanced tools to enhance processor performance. As other industry leaders like TSMC, Samsung, Micron, and SK Hynix explore the adoption of High-NA and eventually Hyper-NA, the competitive landscape is set for a dynamic transformation. Innovations such as advanced polarizers to overcome light polarization issues and improvements in resist materials and etch selectivity will enable more precise and efficient chip manufacturing.

ASML’s Hyper-NA EUV technology is not just a short-term solution but part of a long-term roadmap that will sustain chip innovation for the next decade and beyond. Collaborative research and development efforts, including Imec’s simulations and Zeiss’s lens designs, highlight the cooperative spirit driving this technological advancement. As chip designers like Nvidia, Apple, and AMD leverage these tools at leading foundries such as TSMC, the future of chip design looks brighter than ever, promising enhanced productivity, technological leadership, and sustained growth. Hyper-NA EUV is set to redefine what is possible in the world of semiconductors, driving the industry towards new heights of efficiency and performance.

Sources: ASML Aims for Hyper-NA EUV, Shrinking Chip Limits - EE Times

Air Liquide signed major contract to support the semiconductor industry in the U.S. with an investment of more than 250 million dollars

Air Liquide has announced a significant investment exceeding $250 million to construct a new industrial gas production facility in Idaho, USA. This plant will supply ultra-pure nitrogen and other essential gases to Micron Technology, Inc., a leading semiconductor manufacturer, as well as other local customers. The facility, part of a long-term contract, will play a crucial role in the production of memory chips and is expected to be operational by the end of 2025. This project will generate hundreds of jobs during both the construction and operational phases and is designed to be highly efficient, incorporating digital technologies and modularization to ensure reliability and quick delivery.

Matthieu Giard, Chief Executive Officer of Americas for the Air Liquide Group, said

We are pleased to further strengthen our 30 year-long partnership with Micron Technology. Our partner’s trust in Air Liquide reinforces our position in the Electronics industry as a technology leader with strong innovation capabilities. This investment will support the production of leading-edge memory chips, notably to meet the growing demand for computing capacities required by Artificial Intelligence. This contract illustrates our strategy to further accompany our customers in their development, including in the U.S. The Electronics activity is a strong driver of our 2025 strategic plan ADVANCE, which closely links financial and extra-financial performances.

This initiative exemplifies Air Liquide's commitment to technological advancement and environmental sustainability in the semiconductor sector. The new production unit will be 5% more power-efficient than previous generations and aims to use 100% renewable energy within five years. Matthieu Giard, CEO of Americas for Air Liquide, highlighted the long-standing partnership with Micron Technology and the strategic importance of this investment in supporting the demand for advanced memory chips, driven by the rise of artificial intelligence. Scott Gatzemeier of Micron Technology emphasized the project’s role in enhancing the U.S. semiconductor supply chain, driving significant growth in domestic material sourcing, and bolstering the semiconductor ecosystem across the country.

Source: Air Liquide signed major contract to support the semiconductor industry in the U.S. with an investment of more than 250 million dollars | Air Liquide

NCD Co., Ltd. has supplied ALD equipment for manufacturing perovskite solar cells to Korea Electric Power Corporation

NCD Co., Ltd. has recently supplied KEPCO Research Institute (KEPRI) with its dedicated ALD equipment (Lucida GS-P360) for perovskite solar cells (PSCs). This is equipment for depositing SnO2 thin films, which plays a role as the electron transport layer (ETL) in high-efficiency PSCs. The Lucida GS-P360 enhances high productivity as it can simultaneously processes ALD on multiple glass substrates, making it suitable for mass production.

SnO2 layers deposited via the ALD process allows for the uniform thin film deposition on the nanometer scale, offering higher light transmittance in the visible spectrum compared to TiO2. Additionally, SnO2 exhibits high conductivity and excellent stability. PSCs are gaining great attention as next-generation solar cells due to their simplicity in fabrication, efficiency, and cost-effectiveness. KEPRI has focused on PSC research and achieved an efficiency of 19.8% on 50x50 mm² glass substrates. They are targeting commercialization with 150x150 mm² glass substrate modules, achieving 18% efficiency, and are developing a 20 kW-class building-integrated photovoltaic (BIPV) system for demonstration, anticipating full-scale commercialization within a few years.

Although ALD processes generally offer advantages such as low-temperature processing, superior thin film quality, process reliability, and scalability, the slow deposition rate can significantly increase production costs. However, NCD's ALD equipment for PSCs employs NCD's proprietary high-productivity ALD technology, enabling the processing of SnO2 on 180x180 mm² glass substrates, achieving an outstanding throughput of over 100 glasses per hour, even with the use of high-temperature Sn precursors that are typically challenging to handle.

Moreover, the supplied equipment is capable of handling large-area glass substrates (360x360 mm²), facilitating the manufacture of large-area BIPV PSCs. Specifically, for BIPV applications, because glass substrates thicker than 2 mm are used, the heating of the glass substrates for the ALD process can be time-consuming, limiting productivity. However, NCD's Lucida GS-P360, equipped with a proprietary heating system (patent pending), significantly reduces the time required for heating thick glass substrates, thereby ensuring high productivity.

NCD Co., Ltd. is expected to lead the high-productivity ALD technology and equipment market for PSC manufacturing and will continue to strive to grow as the world's leading ALD company.

< Lucida GS-P360 >

About NCD Co., Ltd:

NCD Co., Ltd. is a rapidly growing Korean company specializing in the development and manufacturing of ALD (Atomic Layer Deposition) and CVD (Chemical Vapor Deposition) equipment. Founded in 2010 and based in Daejeon, NCD focuses on providing advanced equipment, process development, coating services, and consulting for industries such as solar cells and OLED displays. Their innovative solutions aim to enhance efficiency and productivity in high-volume manufacturing.

For more information, visit their official website: NCD Tech.

Jusung Engineering to Spin Off Semiconductor Business, Aiming for Market Revaluation and Strategic Growth

Jusung Engineering, a a first in Korea’s chipmaking equipment industry, has announced a significant restructuring aimed at enhancing its market valuation and navigating geopolitical risks. The company will spin off its highly successful semiconductor division into a new entity, marking a strategic move to unlock greater value for its shareholders and position itself for future growth.

Chairman Hwang Chul-ju highlighted the undervaluation of Jusung despite its proprietary technologies and leading market position. By creating a new entity for its semiconductor business, Jusung aims to elevate its market cap, which currently lags behind international competitors. The new semiconductor entity, tentatively named Jusung Engineering, will operate independently, allowing it to focus solely on expanding its technological capabilities and market presence.

The spin-off comes as Jusung's semiconductor division continues to excel with its advanced film deposition technologies, including selective semi-spheric silicon deposition and atomic layer deposition (ALD). These technologies are pivotal in the production of DRAM memory, NAND flash, and logic chips. As the demand for more integrated and smaller semiconductor devices grows, Jusung's ALD equipment is set to become increasingly crucial. Additionally, Jusung’s poly etchers, applicable across various semiconductor products, will play a significant role in diversifying the company’s offerings.

Despite achieving annual sales of 200 billion won ($146 million) and holding a market cap of 1.6 trillion won, Jusung's valuation remains significantly lower than its global peers. For instance, Dutch competitor ASM boasts a market cap of 47.3 trillion won. The spin-off is expected to narrow this gap, potentially achieving comparable sales records within five years. 

The decision also aims to mitigate risks from the ongoing US-China rivalry. By separating the semiconductor business, Jusung can better shield its other divisions, including display and solar panel equipment, from potential geopolitical fallout. This strategic insulation ensures that the company’s diverse operations remain resilient in the face of international tensions.

There is speculation about Hwang Eun-seok, the chairman’s son, taking the helm of the new semiconductor entity. With a doctorate in material science and experience at Samsung Semiconductors, Eun-seok is well-prepared for leadership, though Chairman Hwang emphasizes that any succession will be merit-based.

Jusung Engineering's spin-off of its semiconductor business represents a bold move to enhance its market valuation and strategically position itself for sustained growth. By creating a focused, independent entity, Jusung aims to capitalize on its technological strengths and navigate the complexities of the global semiconductor market more effectively. This restructuring is set to unlock new opportunities and reinforce Jusung's standing as a key player in the tech industry.

Sources: Jusung, Undervalued no more: Jusung Engineering to spin off chip business (naver.com)

Fundamentals of ALD course – 6-7 June 2024, University of Bath, UK

The "Fundamentals of ALD" course, scheduled for June 6-7, 2024 at the University of Bath, UK, targets newcomers and professionals seeking to deepen their understanding of atomic layer deposition (ALD). It will cover the theoretical and practical aspects of ALD, including surface chemistry, process configurations, reactor design, and material properties. Professors Gregory Parsons, Seán Barry, and Erwin Kessels will lead the course, offering both foundational insights and advanced techniques relevant to laboratory and industrial applications.

The course will run from noon-to-noon across two days, featuring seven detailed lectures interspersed with Q&A sessions and a mixer event on the first evening. Registration is open until May 24, 2024, with fees varying for industry professionals, academia members, and students. The event will take place in the “6 West South” building at the University of Bath, and participants are advised to arrange their own accommodation, with several hotel suggestions provided near the venue.

Link: Fundamentals of ALD course –  6-7 June 2024, University of Bath, UK – ALDAcademy

ASM a revenue of €639 million Q12024 - driven significantly by sales in Atomic Layer Deposition (ALD) and Epitaxy (Epi) technologies.

Here are the key points from ASM International NV's financial results for the first quarter of 2024:

The company reported a revenue of €639 million, at the upper end of their guidance, driven significantly by sales in Atomic Layer Deposition (ALD) and Epitaxy (Epi) technologies.

The foundry and memory segments were the leading contributors to revenue. While the combined logic/foundry segment saw a decline year-over-year, it improved from the previous quarter. The automotive semiconductor market showed weakness, whereas the memory market is showing signs of recovery.

• Gross margin increased to 52.9%, largely due to strong sales performance in the Chinese market.
• New orders reached €698 million, marking a 10% increase from the previous year, mainly driven by the foundry sector. The company expects continued demand for gate-all-around technology, with significant orders anticipated in the second half of the year.
• Despite a slowdown in certain segments like power/analog/wafer, ASM International maintains a strong financial position with a cash reserve of €720 million at the end of the quarter. Sales in China are expected to remain robust.

Samsung Sets New Industry Standard with 290-Layer V9 NAND employing mutli stack etch - Plans for 430-Layer Chips

 Samsung Electronics has initiated mass production of its 9th-generation 1Tb TLC vertical NAND (V-NAND), marking a significant advancement in memory technology. This new generation features the smallest cell size yet, improving bit density by approximately 50% over the previous generation. Innovations like cell interference avoidance and life extension techniques have been introduced to enhance reliability and product quality. By eliminating dummy channel holes, Samsung has also effectively reduced the memory cells' planar area, further emphasizing their commitment to leading the high-density, high-performance solid-state drive (SSD) market, particularly for AI applications.

Competitive situation in 3D NAND Flash technology (Golem.de)

One standout feature of the 9th-generation V-NAND is Samsung's advanced "channel hole etching" technology. This process involves stacking mold layers and simultaneously drilling through them, allowing for the creation of electron pathways through the industry's highest cell layer count in a double-stack structure. As the number of layers increases, so does the complexity of the etching process, necessitating more sophisticated techniques to efficiently pierce through these higher numbers. This technology not only showcases Samsung's process capabilities but also maximizes fabrication productivity, cementing its position as a leader in the SSD market.

According to Golem, Samsung's latest QLC-V9 memory chip outpaces its competitors in the NAND flash market with a groundbreaking 280-layer configuration that enhances SSD capacity, cost-efficiency, and speed. With a storage density of 28.5 GBit/mm², Samsung surpasses major rivals like YMTC and Micron, who report densities of 20.63 and 19.5 GBit/mm² respectively, and even outperforms Intel's upcoming 192-layer PLC-NAND. This technical superiority not only sets a new benchmark for memory chip performance but also enables Samsung to potentially introduce the first 8 TB single-sided M.2 SSDs, a significant advancement over current double-sided designs. The increase in interface speed to 3.2 GBit/s from the previous 2.4 GBit/s promises enhanced read speeds close to those of high-end SSDs, although improvements in write speed are yet to be detailed.

Market share, Q4 2023 (TrendForce)

Samsung Electronics is set to escalate its lead in the NAND flash memory market by starting mass production of its 290-layer ninth-generation (V9) vertical NAND chips, which promise enhanced performance for enterprise servers and AI and cloud devices. Building on its dominance since 2002, Samsung is also planning to introduce even more advanced 430-layer NAND chips next year to meet the growing demand for high-performance and large storage solutions in the AI era. This move is part of a broader competitive landscape where major chipmakers like SK Hynix and YMTC are also pushing forward with high-density NAND products, with SK Hynix planning to start producing 321-layer NAND chips early next year and YMTC set to unveil 300-layer chips later this year. Samsung's aggressive investment in NAND technology aims to develop chips with over 1,000 layers by 2030, highlighting the intensifying race among global chipmakers to innovate in chip stacking technology to cut costs and improve performance.

Sources: 

Samsung Electronics Begins Industry's First Mass Production of 9th-Gen V-NAND | Samsung Semiconductor Global

Rekord bei Speicherdichte: Samsungs QLC-V9-Speicherchip schlägt alle Konkurrenten - Golem.de

Samsung to produce 290-layer V9 NAND to win chip stacking war - KED Global

Linköping University Researchers Pioneer the Synthesis of 'Goldene - a Monolayer Gold Material

Researchers form Linköping University, Sweden, publish a novel method for synthesizing "goldene," a monolayer of gold, achieved by etching away Ti3C2 from a nanolaminated Ti3AuC2 structure using a hydrofluoric acid-free process. The Ti3AuC2 was initially formed by substituting Si in Ti3SiC2 with Au, utilizing a unique aspect of MAX phases—materials characterized by their layered structures and the ability to etch away specific layers. This process not only highlights a new avenue in the synthesis of 2D materials but also overcomes the limitations of previous methods that often required more complex and less environmentally friendly chemicals. The resulting goldene exhibits a lattice contraction of about 9% compared to bulk gold, confirmed via electron microscopy, with further characterization showing an increase in the Au 4f binding energy by 0.88 eV, suggesting altered electronic properties.

Graphical abstract. (From: Synthesis of goldene comprising single-atom layer gold)

The practical implications of goldene extend to various advanced technological applications. Its high surface-area-to-volume ratio, a characteristic of two-dimensional materials, could significantly enhance its catalytic and electronic properties. Applications in fields such as electronics, catalysis, and medicine are discussed, with potential uses ranging from improved catalytic converters to novel approaches in cancer treatment through photothermal therapies. The intrinsic stability of goldene, supported by ab initio molecular dynamics simulations, suggests that despite some physical challenges like curling and agglomeration, the material holds substantial promise for the development of next-generation devices and systems.

The production of atomically thin gold layers in the past typically involved methods that produce few atoms in thickness rather than true monolayers and often required complex supporting substrates or matrices to stabilize the gold layer. The method of exfoliating gold from a nanolaminated MAX phase as described in the publication is a novel approach, potentially opening new pathways for the production and application of gold in nanotechnology and materials science.

 

Schematic illustration of the preparation of goldene. (From: Synthesis of goldene comprising single-atom layer gold),

The production process of goldene is scalable and could potentially be adapted for the synthesis of other non-van der Waals 2D materials. The study outlines further research avenues, including the exploration of different etching schemes and surfactants to enhance the stability and yield of the synthesized layers. The success in manipulating the atomic structure of gold at such a fundamental level not only paves the way for innovative applications but also deepens our understanding of material science at the atomic scale, opening doors to new research in 2D material science.

Source: Synthesis of goldene comprising single-atom layer gold | Nature Synthesis

Intel's Strategic Leap with 14A Node and DSA: Pioneering Next-Gen Semiconductor Manufacturing

Semi Analysis recently published a deeper dive into of Directed Self Assembly (DSA) and prospects of Intel using it at their 14A node (Link below). Intel's latest efforts in semiconductor manufacturing have brought considerable attention to its 18A node, yet it's the 14A node that is most important according to the analysis for the success of Intel Foundry's IDM 2.0 strategy. While the industry watches the ongoing discussions around the merits of TSMC's N2 and Intel’s 18A technologies, Intel is quietly setting a foundational stage with its 14A node, aiming to solidify customer trust and secure critical, high-value chip projects for the future. A key element in Intel's strategy may be the adoption of DSA that could significantly reduce lithography costs. DSA utilizes the self-organizing properties of block copolymers (BCPs) that assemble into predetermined patterns when guided by an underlying template. This approach promises to lower the doses required in extreme ultraviolet (EUV) lithography, allowing for more efficient patterning at reduced costs.

However, integrating DSA into commercial manufacturing involves challenges such as defectivity and pattern limitations, which could hinder its adoption. So I looked more into historical patent filings and found that reveal a typical hype cycle with increased filings during periods of peak expectations, followed by a decline as practical challenges emerged. Intel and TSMC have been consistently filing DSA patents, indicating sustained investment and belief in DSA's potential. Merck, among other chemical suppliers, has significantly increased patent filings, aligning with technological advancements in DSA. Please find on overview below.

It is well known that Intel plans to be the first major company to implement ASML’s high-NA EUV lithography scanners in high volume, despite the higher costs associated with single exposure high-NA systems compared to low-NA double patterning. It was also recently reported on X and other places that ASML is delivering a High-NA System to another player. SemiAnalysis argues that, the economic challenge posed by high-NA technology is addressed through the integration of DSA, which can improve the final pattern quality and dramatically reduce the necessary dose, thus potentially making high-NA economically more viable.

The benefits of DSA are significant: 

• The ability to produce finer features with lower line edge roughness and increased throughput, thanks to its ability to heal discrepancies in the EUV guide patterns. 
• Substantial cost savings and improved yield, especially for layers critical to the performance of advanced logic chips (bigger dies like AI accelerators).

However, DSA's integration into a commercial manufacturing environment is not without risks. The risks associated with Intel's adoption of DSA include:

• The primary risk with any new patterning technology is defectivity, for DSA it is linked to the chemical purity of the block copolymers (BCP). Synthesizing BCP to extremely high purities is challenging, and any inhomogeneity directly impacts the critical dimension (CD), leading to defects. Trace metals need to be below 10 parts-per-trillion, and filtering out organic impurities is difficult, impacting the viability of DSA for mass production. My assessment - Expect this to come from a MERCK or a Japanese chemical vendor.
• DSA is inherently limited to producing 1D line/space patterns or contact hole arrays, restricted to a single pitch per layer. This complicates the integration with other process technologies that might require more diverse patterning capabilities. However, these issues have potential solutions similar to those used in multi-patterning schemes.
• Despite the theoretical benefits and recent advances in DSA, it remains largely untested in high-volume, leading-edge manufacturing. Intel is pioneering the use in high-NA scenarios, but the broader adoption across the industry, including by competitors like TSMC who are also developing DSA, remains uncertain. 

Source: Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA) (semianalysis.com)

So let´s do the Patbase Test - how does this hold out if we dig into historical and current patent filing by the suspects!

Yes indeed, we have seen much increased filing the past decade or so representing a typical hype cycle. The hype cycle is a model developed by Gartner that describes the progression of a technology from inception to widespread adoption and maturity. It typically consists of five phases: the Technology Trigger, Peak of Inflated Expectations, Trough of Disillusionment, Slope of Enlightenment, and Plateau of Productivity. So for DSA in semiconductor manufacturing, the technology first garnered attention when its potential applications in advanced lithography were identified (2000-2010), marking the Technology Trigger. Interest surged about 2011, leading to a Peak of Inflated Expectations around 2016/2017, evidenced by a spike in patent filings as companies raced to capitalize on the emerging technology. However, as practical and economic challenges such as defectivity and integration complexities became evident, the enthusiasm waned, and DSA entered the Trough of Disillusionment. During this phase, the technology's limitations led to a decline in interest as initial expectations were not met. Over time, as more sustainable applications and improvements are developed, DSA may progress into the Slope of Enlightenment, where understanding and optimization occur as described in the assessment by SemiAnalysis, before finally reaching the Plateau of Productivity in the years to come, where it becomes a standard part of semiconductor manufacturing processes. This progression through the hype cycle reflects the typical maturation path of innovative technologies in the industry. Please note that there is a delay in patent filing data of up to 18 months so 2022, 2023 and 2024 are not complete yet.

Patent filing since 2000 in DSA (Patbase, 2024-04-19)

2. Yes, Intel is actively filing DSA patents and in the lead, and so is TSMC, along with other key players in the ecosystem. Over the past decade, the pattern of DSA patent filings has been quite revealing. Initially, GlobalFoundries and IBM in Upstate New York were early filers. GlobalFoundries ceased their filings around the time they decided not to pursue 7 nm and nodes below. IBM also stopped filing after completing their 2 nm demonstration on 300 mm wafers in 2021. Main contenders Intel and TSMC have been consistently filing DSA patents throughout the hype cycle and have continued to do so. Notably, there has been a clear acceleration in Intel's patent filings since 2019, although there was a slight drop during the COVID-19 lockdowns. Looking at chemical suppliers, Merck has taken the lead, with increased filings beginning in parallel with Intel from 2019 onwards, and accelerating until today. Other suppliers such as JSR, Shin-Etsu, and Brewer Science are also active in the DSA space. In the segment of wafer equipment OEMs, Tokyo Electron and SCREEN have been dominant. However, SCREEN appears to have recently exited the game.

DSA Patent filing last decade (Patbase , 2024-04-19)

In Summary - good assessment by SemiAnalysis and i passes the Patbase Test!

Ahead of the 50 Years of ALD celebration in Helsinki, learn about the origins, growth and future of the AVS ALD Conference with Greg Parsons and Steve George

The AVS ALD Conference is the main event for those in Atomic Layer Deposition. The 3-day meeting rotates between the US, Europe and Asia, chock full of interesting parallel sessions, an industry exhibition, and a few sponsored extracurricular activities. In August, the ALD conference will return for the first time in 20 years to Helsinki, Finland, the technologys place of origin. 2024 marks 50 years since Tuomo Suntolas original patent application for ALD, and this year we will celebrate the meteoric rise of the atomic scale process. In this exclusive interview from The ALDepartment, Tyler sits down with two of the founding members of the AVS ALD Conference, Professor Greg Parsons from North Carolina State University, and his PhD advisor at the University of Colorado Boulder, Professor Steven George, to talk about the origins, growth and future of the meeting. Greg and Steve discuss the challenges surrounding the conception of the conference, an unexpected letter from a major ALD company, the enormous success of the 1st conference and how they believe the meeting may change in the future. 

In this Interview: 

00:00 Intro 

01:43 How the conference started 

10:00 An unexpected letter from ASM 

12:16 The first AVS ALD conference 

22:37 Growth and direction 

33:12 Future of AVS ALD

42:16 Reflections and favorite conferences

A New Zr Precursor Enhances Wafer-Scale Zirconium Dioxide Films

A new class of Zirconium (Zr) precursor, featuring boratabenzene ligand, has been developed by a team led by Mohd Zahid Ansari at Yeungnam University, enabling the production of highly conformal ZrO2 thin films via Atomic Layer Deposition (ALD). This innovation, detailed in a recent study published in Science Advances, uses tris(dimethylamido)dimethylamidoboratabenzene zirconium and oxygen as reactants to achieve amorphous ZrO2 films at temperatures ranging from 150–350 °C on SiO2/Si substrates.

The new approach decouples the conventional ALD process, enhancing the deposition temperature window and achieving a growth per cycle of 0.87 Å, which surpasses previous methods using different Zr precursors. The films exhibit extreme conformality with complete step coverage, even on substrates with complex topographies, marking a significant advancement in semiconductor fabrication.

This development not only streamlines the manufacturing process by using O2 as a mild oxidant but also promotes safer and more efficient production methods. The films transition into nanocrystalline cubic ZrO2 upon annealing at 850 °C, enhancing their properties for potential use in high-temperature applications and as coatings for optical filters. The research team's breakthrough paves the way for next-generation semiconductor devices with improved performance and reliability.

The use of ZrO2 in DRAM helps in addressing several challenges associated with the miniaturization of memory devices. As device dimensions continue to shrink, traditional silicon dioxide (SiO2) used in older generations of DRAM becomes less effective due to increased leakage currents and decreased reliability. ZrO2, with its higher dielectric constant, allows for greater data storage capacity and improved efficiency without compromising the device's size or power requirements.

Source: New class of Zr precursor containing boratabenzene ligand enabling highly conformal wafer-scale zirconium dioxide thin films through atomic layer deposition - ScienceDirect

SK hynix to Lead in Advanced DRAM Production, Overtaking Samsung with Earlier Start

Korean SK hynix is set to initiate mass production of its advanced 6th generation 10nm class DRAM (node 1c) in the third quarter of this year, ahead of its competitor Samsung Electronics. The move positions SK hynix to potentially lead in the DDR5 server memory market, which is needed for data centers operated by major tech companies. SK hynix has outlined a strategic internal roadmap that includes achieving necessary customer certifications in anticipation of a surge in demand, especially following compatibility approval with Intel's server platforms. This certification is crucial as Intel holds a dominant share in the global server CPU market. 

The DDR5 DRAM from SK hynix is designed to be compatible with Intel CPUs, a significant advantage given Intel’s extensive market presence. Meanwhile, Samsung plans to start its mass production of similar DRAM by the end of the year, having shared its development roadmap at the recent MemCon 2024 conference. Both companies are using leading-edge Extreme Ultraviolet (EUV) lithography in their processes, which enhances chip yield and power efficiency over previous generations.

SK hynix's new M16 DRAM plant in Icheon, Gyeonggi Province / Courtesy of SK hynix

Source: SK hynix Leads with ‘6th Generation 10 nm’ DRAM Production Ahead of Samsung - Businesskorea

Hanwha to supply ALD Equipment for Molybdenum Deposition for Memory Applications

According to Korean media, Hanwha Precision Machinery is developing a new type of thermal atomic layer deposition (ALD) equipment for depositing molybdenum, which is emerging as a superior material for metal gates in next-generation semiconductors due to its lower resistivity and lack of fluoride residue. The new technology, still in the prototype stage and expected to take three years to commercialize, uses molybdenum dichloride dioxide (MoO2Cl2) as a precursor. This initiative marks Hanwha's expansion into the semiconductor fabrication equipment market, collaborating with industry giants like SK Hynix on future projects, including the development of hybrid bonding equipment for high bandwidth memory production.

At two recent conferences, EFDS ALD For Industry and CMC 2024 this week in Phoenix, Air Liquide presented HVM ready solution for MoO2Cl2 sub fab delivery. They also confirmed that it is already in HVM. Other sources claim that Mo is also in HVM for DRAM. However, no reverse engineering is publicly available as of to day.

Air Liquide presenting HVM ready sub fab solution for MoO2Cl2 precursor delivery at EFDS ALD for Industry in Dresden, Germany.

Hanwha developing thermal ALD equipment for deposition of molybdenum - THE ELEC, Korea Electronics Industry Media (thelec.net)

Apple Partners with Taiwanese Largan to Advance iPhone Camera Plastic Lenses Using ALD Technology - Updated

Apple has been replacing the glass lenses in future iPhone cameras with advanced plastic lenses that have successfully passed customer testing. Two years prior, Apple's supplier Largan invested heavily in ALD (Atomic Layer Deposition) deposition machines specifically for this purpose, costing over $13.9 million each. This investment paid off with significant business from the coating of lenses for the iPhone 15 series, which introduced a periscope lens in its Pro model—a first for iPhones.

Looking ahead, there's anticipation that these new plastic lenses might feature in the iPhone 16 or 17. Largan's chairman, Lin Enping, confirmed the successful testing of a new plastic film, though it remains uncertain if it will be ready for the next iPhone release. This transition to plastic could potentially enhance camera durability, particularly by reducing lens flare and protecting the lenses from damage in case of a fall.

Speculation abounds that Apple might be the customer Lin referred to, although he did not specify. Market analysts highlight that a move to plastic lenses would not only signify a significant technological shift but also align with Apple's ongoing innovation in camera technology.

Update: Apple has used plastic lenses up to and including the iPhone 15 line-up – with one exception. The tetraprism lens used in the iPhone 15 Pro Max is a glass-plastic hybrid known as 1G3P – that is, one glass element, three plastic. This is a compromise designed to bring some of the quality gain from a glass element, without the disadvantages of an all-glass design. Many of the elements in a lens are there purely to correct for various types of distortion. Using at least one glass element eliminates some of those distortions, allowing for fewer elements. Apple's Glass And Plastic Hybrid Lens In The iPhone 15 Pro Max Will Spark A Trend For The Competition To Follow (wccftech.com)

The iPhone 16 Pro is tipped to receive the 5x optical zoom tetraprism lens currently available only on the largest iPhone 15 Pro Max model. This lens will bring Apple’s current most powerful zoom capabilities to the smaller of the two Pro models. However, according to another rumor from last year, the iPhone 16 Pro Max may pull ahead again with an even stronger “ultra-long” telephoto camera. New Apple Leak Reveals Major iPhone 16 Pro Camera Upgrade (forbes.com)

Largan Precision Co., Ltd., based in Taiwan, is a leading manufacturer of optical lens modules, primarily for smartphones and cameras. Renowned for supplying high-quality camera lenses for Apple's iPhone, Largan specializes in high-end lens modules. The company has invested heavily in advanced technologies such as atomic layer deposition (ALD) to enhance lens durability and image quality. Largan's significant production capacity and commitment to innovation make it a key player in the optics industry, pivotal in advancing smartphone camera technology. This role is critical for meeting the high demands of major smartphone manufacturers like Apple.

Source: Apple Seeks to replace Glass Lenses in Future iPhone Cameras with next-gen Plastic Lenses that have already passed customer testing - Patently Apple

Kokusai Electric Showcased Batch ALD Technology for 40-28nm Nodes at SEMICON China 2024

At SEMICON China 2024, Kokusai Electric Corporation emphasized its strengths in atomic layer deposition (ALD) technology. The company showcased its batch-type ALD systems, which are particularly adept at achieving high-quality, uniform film deposition on multiple wafers simultaneously. This technology ensures excellent film thickness control and good step coverage, crucial for advanced semiconductor manufacturing. As the Chinese market increasingly transitions from chemical vapor deposition (CVD) to ALD due to its precision, Kokusai is poised to meet this rising demand, especially in fields like 3D stacking and miniaturization.

Kokusai highlighted its ALD technology specifically for mature semiconductor technology nodes in the 40 to 28nm range at SEMICON China 2024. This focus addresses the growing demand for precise film quality in these specific nodes within the Chinese market.

Source: Kokusai Electric Zeroes in on Film Quality Improvement | AEI (dempa.net)

Rémi Maillat's Watch Brand Launches €145,500 Titanium Timepiece with Nature-Inspired, ALD-Coated Green Dial

The watchmaker founded by Rémi Maillat in 2017 reveals its deep connection with nature with a bold monochromatic titanium timepiece. The spiral dial motif is covered in a shade of green, inspired by both the glowing aurora borealis and the green meadows of spring. The striking colour was achieved using the ALD (Atomic Layer Deposition) coating method, in which the craftsmen deposited extremely thin layers of copper oxide, which interacted with light to create this distinctive hue. Priced at €145,500, it is a testament to craftsmanship and innovation in the world of horology.

KRAYON PRESENTS 

« ANYWHERE AURORA » 

THE FIRST TITANIUM WATCH BY KRAYON

A new colour, Green. Like the reflection with our intimate relationship with nature. A Limited Edition of only 25

Lovers of green rejoice. It's a green that evokes the powerful phenomena of nature. The skies that become fluorescent with the hypnotic northern lights. But also, the first days of spring with the rebirth of fertile soil. It can also be the green that evokes fresh grass after rain, lush meadows, forests, valleys, and that need for wide-open spaces that inspires us to embark on adventure. It’s a colour that heralds a feeling of renewal, of optimism and a new, organic energy directly linked with our natural universe – surprising yet self-evident, as if it had always been part of Krayon’s spirit since its foundation only six years ago.

The brand founded by Rémi Maillat in 2017 has a profound connection to nature. This connection is manifest in its hallmark complication: a personal and intimate ephemeris. Until now, this theme has consistently been presented in various shades of blue, often drawing inspiration from reflections on water surfaces. Today, for the first time, KRAYON boldly explores a new palette and combines it with a new, lighter, more modern metal: Grade 5 titanium.

Anywhere Aurora | Krayon

Applied Materials Pioneer® CVD film for EUV Sculpta and DRAM Sym3 Etch applications

Applied Materials continues to lead in semiconductor technology with its introduction of the Producer® XP Pioneer® CVD patterning film at the SPIE Advanced Lithography + Patterning conference. This latest innovation is critical for DRAM scaling and EUV lithography, offering improved etch selectivity and pattern fidelity due to enhanced film density and stiffness. Optimized for use with the Sculpta® pattern-shaping system, Pioneer allows for advanced patterning capabilities, crucial for maintaining precise feature dimensions. With its adoption by leading foundry-logic and memory manufacturers, the Pioneer system is set to significantly enhance Applied Materials' portfolio and revenue, affirming its leadership in CVD technologies.

Applied Materials' Draco™ hard mask and Sym3® Y HT etch system have revolutionized DRAM production by enabling the etching of perfectly cylindrical capacitor holes, significantly enhancing etch selectivity and improving critical dimension uniformity, which contributes to a notable increase in the company's market share in DRAM.

Demand for DRAM innovation continues to grow to feed the insatiable need for memory bandwidth in the AI era. The recently launched Pioneer CVD patterning film has already been adopted by leading memory manufacturers for DRAM patterning. Pioneer is a completely new CVD architecture based on a unique high-density carbon formula that is more resilient to etch chemistries used in the most advanced process nodes, permitting thinner film stacks with superior sidewall feature uniformity.

A thinner hard mask means less vertical distance is required for etch, resulting in a lower aspect ratio. This allows use of lower-power plasma and offers better control of the ratio of ions to radicals. A higher concentration of ions produces more efficient etches with better control, allowing desired patterns to be transferred to the wafer with exceptional fidelity. Pioneer is also being co-optimized with Applied’s new Sym3® Y Magnum® etch system to provide better control over conventional carbon films for critical etch applications in memory processing.

For EUV Lithography the Pioneer CVD patterning film developed by Applied Materials addresses the stringent demands of EUV lithography by increasing film density and stiffness, which enhances etch selectivity and allows for finer pattern control, vital for the ultra-fine dimensions required in advanced chip manufacturing.

Source: Building on an Unmatched Foundation of CVD Innovation (appliedmaterials.com)

AlixLabs announces EU-wide APS Trademark and nearing commercialization on 300-millimeter wafer equipment

The European Intellectual Property Office grants Swedish semiconductor startup registration of the phrase APS (ALE Pitch Splitting).

Lund, Sweden – April 5th, 2024, AlixLabs AB, a Swedish semiconductor startup specializing in Atomic Layer Etching, announces that it has been granted a certification of registration for its trademark APS by the European Union Intellectual Property Office. The acronym APS stands for Atomic Layer Etching (ALE) Pitch Splitting and describes the company’s revolutionary process that aims to enable the semiconductor industry produce chips of the future at Ångström scale (1Å = 0.1 nanometer) at lower cost and energy use.

Jonas Sundqvist, CEO of AlixLabs (top) and Thomas Engstedt CEO of Nanovac and Dmitry Suyatin CTO of AlixLabs (Bottom).

“As we are nearing commercialization of our technology on 300-millimeter (12-inch) silicon wafers, it feels great to finally have a unique trademark to our unique semiconductor manufacturing process,” comments Jonas Sundqvist, CEO of AlixLabs. “We have been etching transistor fins since 2019, and within the upcoming quarters we will have fully validated the APS process on 300-millimeter wafers with new equipment developed by our fellow countrymen at Nanovac.”

Having previously demonstrated APS on bulk silicon, AlixLabs aims to install the new Nanovac-developed equipment in the summer of 2024. Once up and running, the goal is to finalize a commercial APS process that can be licensed to leading-edge semiconductor manufacturers to enable cheaper, more energy-efficient and sustainable production of advanced chips.

“This 300-millimeter wafer tool combines our deep industry knowledge with practical design innovations, aiming to offer improved precision and efficiency in semiconductor manufacturing,” says Thomas Engstedt, founder and CEO at Nanovac. “It’s a disruptive step forward for Atomic Layer Etching and APS processing, setting a solid foundation for future advancements by employing modular design concepts.”

APS is the first trademark of AlixLabs, joining the company’s growing portfolio of patents related to the APS process that includes one EU, two U.S., and two Taiwanese patents.

About AlixLabs

Established in 2019 in Lund, Sweden, AlixLabs emerged as a spin-off from Lund University with a mission to enable the cost-effective and energy-conscious fabrication of semiconductors, particularly logic and memory components. AlixLabs boasts patented recognition for its groundbreaking APS technique, a process that achieves nanostructure division through etching. This method holds approved patents across the USA, Taiwan, and Europe. The APS acronym signifies ALE Pitch Splitting, leveraging ALE (Atomic Layer Etching), a plasma-based dry etching cyclic methodology. For more details, please visit www.alixlabs.com

Surfs are going to be up at the PRiME Symposium G01 on ALD & ALE Applications 20, in Honolulu | Oct. 6-12, 2024

Every four years, the PRiME Joint International Meeting is held under the auspices of the Electrochemical Society (ECS), joint with its sister Societies of Japan and Korea. This fall, PRIME 2024 will be held on Oct. 6-11, 2024 in Honolulu, Hawaii, and is expected to gather over 4000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

General information and the Meeting Program can be found here: CALL FOR PAPERS.

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 20” encourage you to submit your abstract(s) on topics, comprising but not limited to:

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials;

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.;

3. Interconnects and contacts: integration of ALD films with Cu and low-k materials;

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory;

5. New precursors and delivery systems;

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence

7. Coating of nanoporous materials by ALD;

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD;

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.;

10. ALD for energy storage applications;

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll deposition;

12. Area-selective ALD;

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc.

FYI: Last year in Gothenburg, our symposium G01 on ALD & ALE Applications 19 attracted a record number of 78 presentations, composing a full 4-day schedule of 66 oral (of which 18 invited), plus 12 poster presentations.

We will traditionally attract more attendants from Far East and expect to be as successful this fall in Hawaii.

Abstract submission

Meeting abstracts should be submitted not later than the deadline of April 12, 2024 via the ECS website: Submission Instructions

Invited speakers

List of confirmed invited speakers (from North America, Asia and Europe):

1. Bart Macco, TU Eindhoven, Netherlands, Review of ALD for solar cells

2. Maarit Karppinen, Aalto University, Finland, ALD/MLD for energy / membrane technology

3. Chad Brick, Gelest, USA, Silanes and silazanes precursors for Area Specific Deposition

4. Makoto Sekine, Nagoya Univ., Japan, Low damage ALE of AlGaN

5. Rong Chen, HUST Univ. Wuhan, China, ALD for Cataysis and other applications

6. Mikhael Bechelany, IEM, Montpellier, France, Recent Advancements and Emerging Applications in ALD on High-Porosity Materials

7. Miika Mattinen, Univ Helsinki, Finland, ALD of dichalcogenides for electrocatalysis

8. Bonggeun Shong, Hongik University, Korea, Theory of area-selective ALD

9. Miin-Jang Chen, National Taiwan Univ., Inhibitor-free Area-Selective ALD

10. Hyungjun Kim, Yonsei University, Korea, ALD of “Group 16 Compounds” for Emerging Applications (2D TMDCs)

11. Agnieszka Kurek, Oxford Instruments, United Kingdom, Faster ALD for Emerging Quantum Applications

12. Matthew Metz, Inte, USA, Keynote on "Materials Challenges in Future Semiconductor Devices"

13. Junling Lu, University of Science and Technology of China, ALD for Catalysis

14. Sung Gap Im, KAIST, Korea, Vapor-phase Deposited Functional Polymer Films for Electronic Device Applications

15. Jason Croy, Argonne National Lab, USA, Next-gen batteries & ALD

16. Mark Saly, Applied Materials, USA, Key Challenges in Area Selective Deposition: from R&D Scale to High Volume Manufacturing

Visa and travel

For more information, see: VISA AND TRAVEL INFORMATION

In addition, Mrs. Francesca Spagnuolo at the ECS (Francesca.Spagnuolo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society.

For (limited) general travel grant questions, please contact travelgrant@electrochem.org.

We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 20, in Honolulu | Oct. 6-12, 2024 !