Thursday, May 27, 2021

Atomic billiards helps to understand Atomic Layer Deposition

In the beautiful German city of Münster, scientists are playing games on an atomic scale to help ALD developers understand what is going on in their process. Critical ALD parameters, such as the evolution of film closure and thickness with increasing cycle number are determined with a game of billiards at the atomic level. This game is called LEIS (Low Energy Ion Scattering), the most surface specific chemical analysis technique available to the surface scientist.

The fundamental principles behind LEIS are surprisingly simple: In an ultrahigh vacuum chamber, light charged particles (ions) are aimed at the sample where they collide with the atoms in and on the sample. These collisions obey the same laws of physics as collisions between large objects, such as balls. This means that the ions are bouncing (or scattering) back with high speed (or energy) when they collide with a heavy atom and with low energy after a collision with a light atom. The energy of the scattered ions is measured to determine the mass of the surface atoms.

Figure 1: The principle of LEIS: When ions collide with surface atoms, their energy after the collision depends on the mass of the atoms that they collided with. A LEIS spectrum shows the number of returned ions as a function of their energy. This represents the surface concentrations of different elements, sorted after their mass.

LEIS helps to develop and optimize ALD processes

We show an example of a co-operation between scientists at Tascon in Münster and the ALD experts from ASM Microchemistry Oy in Helsinki, Finland where the initial formation of a GaSb film on SiOx was investigated.

Figure 2 shows a set of LEIS spectra for the increasing number of ALD cycles recorded with Neon ions. There are two peaks due to collisions with Gallium (Ga) and Antimony (Sb) atoms in the outermost atomic layer of these samples. Antimony atoms are heavier than Gallium atoms and therefore the peak from collisions with Antimony lies at higher energy than the Gallium peak.

Figure 2: 5 keV 20Ne+ LEIS spectra of increasing cycle numbers of GaSb deposited on SiOx
As one would expect, the amount of Gallium in the outermost atomic layer is increasing continuously with increasing cycle number (from red to purple) showing how the fraction of Gallium increases in the outermost atomic layer. The Antimony behaves differently, though. After increasing initially, its signal goes through a maximum (the green spectrum), and with increasing cycle number the amount of Antimony at the surface decreases. With this valuable information, the ALD expert can optimize the deposition process.

LEIS separately analyzes the outermost atomic layer and the layers below it

As we have seen, LEIS is sensitive to the outermost atomic layer of a sample. The used noble gas ions (Helium or Neon) lose their charge as soon as they enter the material. Since the instrument can only detect ions, the neutral Helium or Neon atoms that collided in deeper layers are not detected. Therefore, the peaks in the spectrum from figure 2 represent Gallium and Antimony at the surface.

Particularly when Helium ions are used, there is a second effect. A Helium atom, that collided in deeper layers, may lose an electron as it leaves the surface. The probability for this re-ionization is small enough to recognize the peaks in the spectra, but large enough to cause an additional signal in the spectrum, as shown in figure 3, a set of spectra recorded with Helium ions from the same GaSb deposition study.

Figure 3: 7 keV 4He+ LEIS spectra of increasing cycle numbers of GaSb deposited on SiOx.
Again, we see the Gallium peak increasing and the Antimony peak going through a maximum. This time, we also see the Silicon (Si) peak decreasing with increasing cycle number, confirming that the substrate is getting covered. But we also see that with increasing cycle number shoulders appear on the left side of the Gallium and Antimony peaks (indicated by the dashed arrows).

These shoulders are caused by collisions from Gallium and Antimony atoms below the surface. The Helium atoms have slowed down while traveling through the sample on their way to and from the colliding atom. The more the shoulder extends to lower energy, the more the atoms have slowed down and the deeper the colliding atom was in the sample. The fact that the shoulders are extending more and more to the left with increasing cycle number shows that the film is getting thicker.

Since LEIS is a quantitative analysis technique, the surface fractions can be determined from the spectra. Figure 4 shows a ternary diagram for the composition of the sample surface with increasing cycle number. It clearly shows that initially Gallium and Antimony are deposited together. But as the film is almost closed, the Gallium deposition starts to dominate.

Figure 4: Ternary diagram showing the surface composition of the samples with increasing cycle number. The colors of the data points correspond to the colors of the spectra.
This example shows the value of LEIS in the study of ALD. Because of its surface specificity and the need for ever thinner films, the role of LEIS in ALD is expected to increase in the coming years.


The GaSb films in this study were kindly provided by ASM Microchemistry Oy, Helsinki, Finland.

Guest blog by Rik ter Veen and Karsten Lamann, Tascon GmbH, Münster, Germany

About the authors:

Rik ter Veen and Karsten Lamann are scientists at Tascon GmbH, a service provider and consulting company for the analysis of surfaces, films and interface for over 20 years with two locations in Germany and one in the USA. In addition to LEIS, the subject of this blog, Tascon offers surface and materials analysis with techniques such as ToF-SIMS, XPS and SEM-EDX. If you are interested in their services or have questions about LEIS, or other techniques, the authors can be contacted through their website.

Wednesday, May 26, 2021

Vaccines perfected from the atoms up - Forge Nano technology enables next-gen vaccine formulation platform using ALD

Vaccines perfected from the atoms up - Forge Nano technology enables next-gen vaccine formulation platform using Atomic Layer Deposition.

The vaccine of the future is here. Designed from the atoms up, this disruptive technology platform enables; thermally stable, combined-dose, time released, single injection vaccines!

Forge Nano platform technology is being used to develop innovative vaccines that can withstand higher temperatures, combine multiple doses, and release over time, all in one injection. Using Atomic Layer Deposition, these vaccine formulations can be controlled at the atomic level.

VitriVax, Inc. a Colorado based formulation technology company, utilizes Forge Nano’s Atomic Layer Deposition platform technology to engineer thermostable, single-shot vaccines across a broad range of indications. Using the cGMP certified PANDORA ALD tool, developed and manufactured by Forge Nano, VitriVax uses its proprietary Atomic Layering Thermostable Antigen and Adjuvant (ALTA™) technology platform to enable thermostable, single-shot vaccines, that can be applied to a wide variety of antigens and adjuvants to project against thermal and chemical degradation, and enable controlled release, incorporating prime doses + additional booster doses in a single-shot administration.

VitriVax’s vaccine formulation platform addresses both of these challenges by enabling vaccines to be made thermostable up to 70°C (158°F), and the combination of prime and boost doses into a single injection with timed release, eliminating the need for a follow up injection. The platform uses a technology called atomic layer deposition (ALD) to coat the active ingredient in the vaccine with a protective layer of adjuvant (commonly used in vaccines to stimulate immune response). That coating then slowly dissolves to release the dose inside. The current generation of ALD system in use by VitriVax operates at the scale of around 1000 doses per run. (LINK)

“In light of the current global pandemic, vaccine storage, distribution, and efficacy has never been more important. We are proud to see our platform being used to make vaccines that can be more easily transported, with more efficient and precisely controlled doses. Future technologies are being enabled by controlling things at the atomic level. Our platform is being used every day to enable precision and control at the atomic scale.” Dr. Paul Lichty- CEO Forge Nano.

Forge Nano specializes in optimizing the way surfaces interact at the atomic level. Using proprietary technology, Forge Nano can apply nano coatings onto the surface of virtually anything. Forge Nano’s platform technology unlocks a level of precision and control that is unrivaled by other surface engineering technologies.

About VitriVax, Inc:

Based in Boulder, CO, VitriVax’s mission is to eliminate barriers to global vaccination. Through its ALTA formulation platform, and driven by a world-class team of scientists, engineers and entrepreneurs with expertise in vaccine development, virology and chemical engineering, VitriVax is dedicated to significantly increasing the availability of human and animal vaccines around the world.

Thursday, May 20, 2021

Plasway, Fraunhofer IKTS and BALD Engineering to present fast SiO2 PEALD at ALD2021

Get ready for ALD/ALE 2021 and don´t miss new record-breaking fast ALD using 3D printed ceramic de Laval Rocket nozzle technology by Plasway, Fraunhofer IKTS and BALD Engineering.

♦ Realization and Dual Angle In-situ OES Characterization of Saturated 10-100 ms Precursor Pulses in a 300 mm CCP Chamber Employing de Laval Nozzle Ring Injector for Fast ALD

♦ we use two fast scanning, with ≤10 ms acquisition time per spectrum ranging from 200 nm to 800 nm, Optical Emission Spectrometers with a resolution in the range of 0.7 nm.

♦ We present the results for PEALD of SiO2 exhibiting substrate surface saturation for 30 ms of BDEAS pulse and 50 ms of O2

Realization and Dual Angle, In-situ OES Characterization of Saturated 10-100 ms Precursor Pulses in a 300 mm CCP Chamber Employing de Laval Nozzle Ring Injector for Fast ALD

Abhishekkumar Thakur1, Stephan Wege1, Sebastian Bürzele1, Elias Ricken1, Jonas Sundqvist2, Mario Krug3

1Plasway Technologies GmbH, 2BALD Engineering AB, 3Fraunhofer IKTS

ALD-based spacer-defined multiple patterning schemes have been the key processes to continued chip scaling, and they require PEALD or catalytic ALD for low temperature and conformal deposition of spacers (typically SiO2) on photoresist features for the subsequent etch-based pitch splitting. Other SiO2 applications in the logic and the memory segments include gap fill, hard masks, mold oxides, low-k oxides, hermetic encapsulation, gate dielectric, inter-poly dielectric ONO stack, sacrificial oxide, optical films, and many more. ALD is limited by low throughput that can be improved by raising the growth per cycle (GPC), using new ALD precursors, performing batch ALD or fast Spatial ALD, shrinking the ALD cycle length, or omitting purge steps to attain the shortest possible ALD cycle. Today’s latest and highly productive platforms facilitate very fast wafer transport in and out of the ALD chambers. Current 300 mm ALD chambers for high volume manufacturing are mainly top-down or cross-flow single wafer chambers, vertical batch furnaces, or spatial ALD chambers.

We have developed a Fast PEALD technology [1], realizing individual precursor pulses saturating in the sub-100 ms range. The key feature of the technology is the highly uniform, radial injection of the precursors into the process chamber through several de Laval nozzles [2]. To in-situ study (concomitantly from the top and the side of the wafer surface) individual ALD pulses in the 10-100 ms range, we use two fast scanning (≤10 ms acquisition time per spectrum ranging from 200 nm to 800 nm) Optical Emission Spectrometers with a resolution in the range of 0.7 nm.

Saturation curves for SiO2 Fast PEALD

We present the results for PEALD of SiO2 exhibiting substrate surface saturation for 30 ms of BDEAS pulse (Fig. 1) and 50 ms of O2 plasma pulse (Fig. 2). All the processes were carried out in a 300 mm, dual-frequency (2 MHz and 60 MHz) CCP reactor in the temperature range of 20 °C to 120 °C and at ~1 Torr max. pulse pressure. The in-situ, time-resolved OES study of O2 plasma pulse, indicating saturation of  O* (3p5Pà3s5S) emission peak already at 50 ms pulse duration (Fig. 3, 4) and associated extinction of reactive O* within 161 ms (Fig. 5), suggest room for yet faster process. The mean GPC diminishes with the electrostatic chuck temp (Fig. 6).

We will present a more optimized PEALD SiO2 process and stacking of Fast PEALD SiO2 on top of Fast PEALD Al2O3 in the same chamber without breaking the vacuum. The results will comprise XPS, TEM, film growth uniformity across 300 mm wafer, and residual stress investigation for the film stack.    


[1] AVS ALD2020, Abstract Number: 2415, Oral Presentation: AM-TuA14

[2] Patent US20200185198A1

ALD/ALE 2021 Technical Program June 27-30, 2021

Virtual Meeting Overview & Highlights

The AVS 21st International Conference on Atomic Layer Deposition (ALD 2021) featuring the 8th International Atomic Layer Etching Workshop (ALE 2021) will be adapted into a Virtual Meeting comprised of Live and On Demand Sessions. The event will feature:

AVS ALD/ALE 2021 Conference Page 

Live Tutorial Session with live Q&A Chat Opportunities
(Sunday, June 27, 2021)

  • Parag Banerjee (University of Central Florida, USA), “Seeing Is Believing: In situ Techniques for Atomic Layer Deposition (ALD) Process Development and Diagnostics”
  • Arrelaine Dameron (Forge Nano, USA), “ALD Powder Manufacturing”
  • Henrik Pedersen (Linkoping University, Sweden), “Let’s Talk Dirty – Battling Impurities in ALD Films”
  • Riikka Puurunen (Aalto University, Finland), “Fundamentals of Atomic Layer Deposition: An Introduction (“ALD 101”)”
  • Fred Roozeboom (Eindhoven University of Technology, The Netherlands), “ALE and ALD: Two Biotopes of a Kind in Atomic-Scale Processing”

Live Plenary, Awards, and Student Finalists with live Q&A Chat Opportunities (Monday, June 28, 2021)

  • Plenary Speaker: Steven George (University of Colorado Boulder, USA), “Mechanisms of Thermal Atomic Layer Etching”
  • Plenary Speaker: Todd Younkin (Semiconductor Research Corporation, USA), “Materials & Innovation – Essential Elements that Underpin the Next Industrial Revolution
  • Live Parallel Technical Sessions with live Q&A Chat Opportunities (Tuesday-Wednesday, June 29-30, 2021)

  • On Demand Oral Sessions (Starting Monday, June 28, 2021)

  • On Demand Poster Sessions with a Mix of Pre-recorded (Video or Audio) Talks and/or PDF files

Note: Live and On Demand Sessions available on Mobile App/Online Scheduler through July 31, 2021 and then to AVS members in the AVS Technical Library. Live Sessions will also be recorded and added to the On Demand Sessions.

Thursday, May 13, 2021

Schweden wollen mit Ätz-Spalttechnik Chipproduktion in Sachsen umkrempeln

Alix Labs aus Lund testet Verfahren nun im Silicon Saxony, berichtet Heiko Weckbrodt bei

Lund/Bannewitz, 13. Mai 2021. Ingenieure aus Schweden und Sachsen wollen gemeinsam die Mikroelektronik-Produktion umkrempeln. Dafür hat das schwedische Technologie-Unternehmen „Alix Labs“ ein Verfahren entwickelt, das die Produktion neuester Computerchips mit Strukturgrößen unterhalb von zehn Nanometern (Millionstel Millimeter) stark vereinfachen und verbilligen soll. Dabei geht es auch darum, den Einsatz teurer Belichtungsanlagen mit „Extremer Ultraviolett-Strahlung“ (EUV) zu vermeiden, die etwa 120 Millionen Euro pro Maschine kosten und für die es weltweit nur eine Quelle gibt: ASML aus den Niederlanden. Um auf alternativen Wegen feinste Chipstrukturen zu erzeugen, setzen die Schweden auf eine „Pitch-Splitting-Methode“ (APS) mittels Atomlagen-Ätzen (Atomic Layer Etching, abgekürzt ALE). „Plasway Technologies“ aus Bannewitz in Dresden transferiert dieses Verfahren nun in einen industrienahen Maßstab auf 300 Millimeter großen Siliziumscheiben (Wafer).
Weiterlesen: LINK

„In Schweden haben wir keine 300-Millimeter-Infrastruktur“, erklärt „Alix Labs“-Chef Jonas Sundqvist die Kooperation mit den Sachsen. „Unsere Technologie kann in bestehende Prozessabläufe der Halbleiterherstellung integriert werden. Theoretisch könnten Chipfabriken wie die Globalfoundries-Fab 1 in Dresden unsere Methode einführen und dann 10- oder 7-Nanometer-Chips herstellen ohne teure EUV-Anlagen.“ Als Kunden sieht er aber auch Branchenriesen wie Intel, TSMC und Samsung.

Wednesday, May 12, 2021

A Molecular Drone for Atomic‐Scale Fabrication Working under Ambient Conditions

Pretty cool stuff going on, please check the interview of the scientist here (LINK). Thanks for sharing this one Henrik Pedersen.

A Molecular Drone for Atomic‐Scale Fabrication Working under Ambient Conditions

Matteo Baldoni Francesco Mercuri Massimiliano Cavallini
Advanced Materials Communications, First published: 12 April 2021

The direct manipulation of individual atoms has led to the advancement of exciting cutting‐edge technologies in sub‐nanometric fabrication, information storage and to the exploration of quantum technologies. Atom manipulation is currently performed by scanning probe microscopy (SPM), which enables an extraordinary spatial control, but provides a low throughput, requiring complex critical experimental conditions and advanced instrumentation. Here, a new paradigm is demonstrated for surface atom manipulation that overcomes the limitations of SPM techniques by replacing the SPM probe with a coordination compound that exploits surface atom complexation as a tool for atomic‐scale fabrication. The coordination compound works as a “molecular drone”: it lands onto a substrate, bonds to a specific atom on the surface, picks it up, and then leaves the surface along with the extracted atom, thus creating an atomic vacancy in a specific position on the surface. Remarkably, the feasibility of the process is demonstrated under electrochemical control and the stability of the fabricated pattern at room temperature, under ambient conditions.

Phthalocyanine molecule can act as a ‘molecular drone’ from Chemistry World on Vimeo.

Saturday, May 8, 2021

Worldwide silicon wafer area shipments increased 4% to 3,337 million square inches in the first quarter of 2021

MILPITAS, Calif. — May 3, 2021 — Worldwide silicon wafer area shipments increased 4% to 3,337 million square inches in the first quarter of 2021 compared to the fourth quarter of 2020, topping the previous historical high set in the third quarter of 2018, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. First-quarter 2021 silicon wafer shipments saw 14% growth from the 2,920 million square inches logged during the same quarter last year.
From Semi data

“Logic and foundry continue to drive strong demand for silicon wafers,” said Neil Weaver, chairman SEMI SMG and Vice President, Product Development and Applications Engineering at Shin Etsu Handotai America. “The memory market recovery further bolstered shipment growth in the first quarter of 2021.”

Data cited in this release includes polished silicon wafers such as virgin test and epitaxial silicon wafers, as well as non-polished silicon wafers shipped to end users.

Silicon wafers are the fundamental building material for the majority of semiconductors, which, in turn, are vital components of all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin disks are produced in diameters of up to 12 inches and serve as the substrate material on which most semiconductor devices, or chips, are fabricated.

The SMG is a sub-committee of the SEMI Electronic Materials Group (EMG) and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi). The purpose of the SMG is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics on the silicon industry and the semiconductor market.

For more information, please visit SEMI Worldwide Silicon Wafer Shipment Statistics.

Webinar - Decadal Plan for Semiconductors: New Compute Trajectories for Energy Efficiency

SIA/SRC [LINK]: Computing and, more generally, Information and Communication Technologies (ICT) is the social-economic growth engine of the modern world. Rapid advances in computing have provided increased performance and enhanced features in each new generation of products in nearly every market segment, whether it be servers, PCs, communications, mobile, automotive, or entertainment, among others.

The use of information and communication technologies continues to grow without bounds dominated by the exponential creation of data that must be moved, stored, computed, communicated, secured and converted to end user information. Ever-rising energy demands for computing versus global energy production are creating new risk, therefore new computing paradigms need to be discovered that would result in dramatically improved energy efficiency of computing.

This webinar intends to identify a compelling research agenda based on the Decadal Plan for Semiconductors, led by SRC to discover new approaches to computing with a focus on changing the current mainstream compute trajectory. The underlying technical challenge is bit-utilization efficiency in computation.

Friday, May 7, 2021

BALD Engineering & Friends Virtual ALD Fest June 27-30 (tbd), 2021 with Free Beer

BALD Engineering Virtual ALD Fest June 27-30 (tbd), 2021 with Free Beer. A splendid event for everyone attending AVS ALD 2021 or ALE 2021 virtually. The Fest will be streaming live from Dresden Germany and a number of additional locations worldwide - To be announced

1. Beer opening ceremony & Tutorial How to open a beer bottle the German way and how to pour a Hefe Weizen
2. ALD Market Briefing with beer
3. Beer drinking competition with several entries (to be announced)

Please vote on Twitter:

Applied Materials MEMORY MASTER CLASS 2021 - slide deck

I missed this opportunity, however, I am grateful for Lita Shon-Roy just sending me the link to the slide deck - Tack så mycket. 

Slide deck for the Memory Class LINK

Next class up is Logic June 16, 2021 followed by more interesting topics in 2nd half 2021:

  • Specialty semiconductors
  • Heterogeneous design and advanced packaging
  • Inspection and process control

Teaser slide (Credit Dr. Sony Varghese, Director of Strategic Marketing at at Applied Materials)

You are welcome to contact us at TECHCET ( to dig further into the future surge of materials to realize the data-driven economy:

  • ALD/CVD precursors
  • Metals/PVD Targets
  • Photoresist
  • Wet chemicals
  • CMP pads & slurries
  • Bulk, Rare and Speciality gases
  • Wafers

Applied Materials Introduces Materials Engineering Solutions for DRAM Scaling

  • New Draco™ hard mask material co-optimized with Sym3® Y etcher to accelerate DRAM capacitor scaling
  • DRAM makers adopting Black Diamond®, the low-k dielectric material pioneered by Applied Materials to overcome interconnect scaling challenges in logic
  • High-k metal gate transistors now being introduced in advanced DRAM designs to boost performance and reduce power while shrinking the periphery logic to improve area and cost
SANTA CLARA, Calif., May 05, 2021 (GLOBE NEWSWIRE) -- Applied Materials, Inc. today announced materials engineering solutions that give its memory customers three new ways to further scale DRAM and accelerate improvements in chip performance, power, area, cost and time to market (PPACt).
The Draco hard mask resolves this issue with a new material whose selectivity is more than 30 percent higher than conventional DRAM capacitor hard masks. It enables the deposition of a 30 percent thinner hard mask, thus decreasing the capacitor’s aspect ratio and easing the difficulty of the etch process.

The digital transformation of the global economy is generating record demand for DRAM. The Internet of Things is creating hundreds of billions of new computing devices at the edge which are driving an exponential increase in data transmitted to the cloud for processing. The industry urgently needs breakthroughs that can allow DRAM to scale to reduce area and cost while also operating at higher speeds and using less power.
Applied Materials is working with DRAM customers to commercialize three materials engineering solutions that create new ways to shrink as well as improve performance and power. The solutions target three areas of DRAM chips: storage capacitors, interconnect wiring and logic transistors. They are now ramping into high volume and are expected to significantly increase Applied’s DRAM revenue over the next several years.

Introducing Draco™ Hard Mask for Capacitor Scaling

Since over 55 percent of a DRAM chip’s die area is occupied by the memory arrays, increasing the density of these cells is the biggest lever for reducing cost per bit. Data is stored as charges in cylindrical, vertically arranged capacitors that need as much surface area as possible to hold adequate numbers of electrons. As DRAM makers narrow the capacitors, they also elongate them to maximize surface area. A new technology challenge to DRAM scaling has emerged: the etching of the deep capacitor holes threatens to exceed the limits of the “hard mask” material that acts as a stencil to determine where each cylinder is placed. If the hard mask is etched through, the pattern is ruined. Taller hard masks are not viable because as the combined depth of the hard masks and capacitor holes exceeds certain limits, etch byproducts remain and cause bending, twisting and uneven depths.

Applied Producer® XP Precision® Draco™ CVD

The solution is Draco™, a new hard mask material that has been co-optimized to work with Applied’s Sym3® Y etch system in a process monitored by Applied’s PROVision® eBeam metrology and inspection system that can take nearly half a million measurements per hour. The Draco hard mask increases etch selectivity by more than 30 percent which enables a shorter mask. Draco hard mask and Sym3 Y co-optimization includes advanced RF pulsing which synchronizes etching with byproduct removal to enable patterning holes that are perfectly cylindrical, straight and uniform. The PROVision eBeam system gives customers massive, immediate actionable data on hard mask critical dimension uniformity which is the key to capacitor uniformity. Applied’s solution provides customers with a 50-percent improvement in local critical dimension uniformity and reduces bridge defects by 100X, thus increasing yields.

Implementation of Draco for DRAM capacitors. (Applied Materials Master Memory Class May the 5th 2021 LINK)

“The best way to quickly solve materials engineering challenges with our customers is to co-optimize adjacent steps and use massive measurements and AI to optimize process variables,” said Dr. Raman Achutharaman, group vice president, Semiconductor Products Group at Applied Materials.

Bringing Black Diamond® Low-k Dielectric to the DRAM Market

A second key lever of DRAM scaling is reducing the die area needed by the interconnect wiring that routes signals to and from the memory arrays. Each of the metal lines is surrounded by an insulating dielectric material to prevent interference between data signals. For the past 25 years, DRAM makers have used one of two silicon oxides – silane and tetraethoxysilane (TEOS) – as the dielectric material. Continual thinning of the dielectric layers has reduced DRAM die sizes but created a new technology challenge: the dielectrics are now too thin to prevent capacitive coupling in the metal lines whereby signals interfere with one another causing higher power consumption, slower performance, increased heat and reliability risks.

The solution is Black Diamond®, a low-k dielectric material first used in advanced logic. With DRAM designs now experiencing similar scaling challenges, Applied is adapting Black Diamond to the DRAM market and making it available on the highly productive Producer® GT platform. Black Diamond for DRAM enables smaller, more compact interconnect wires that can move signals through the chips at multi-gigahertz speeds without interference and at lower power consumption.

High-k Metal Gate Transistors Bring PPAC Improvements to DRAM

A third key lever of DRAM scaling is improving the performance, power, area and cost of the transistors used in the periphery logic of the chip to help drive the input-output (I/O) operations needed in high-performance DRAM like those based on the new DDR5 specification.

Until today, DRAM used transistors based on polysilicon-oxide which were phased out in foundry-logic by the 28-nanometer node because extreme thinning of the gate dielectric allowed electrons to leak, thereby wasting power and limiting performance. Logic makers adopted high-k metal gate (HKMG) transistors, replacing the polysilicon with a metal gate and the dielectric with hafnium oxide, a material that improves gate capacitance, leakage and performance. Now memory makers are designing HKMG transistors into advanced DRAM designs to improve performance, power, area and cost. In DRAM as in logic, HKMG will increasingly replace polysilicon transistors over time.

This technology inflection in DRAM creates growth opportunities for Applied Materials. The more complex and delicate HKMG materials stack is challenging to manufacture, and in-vacuum processing of adjacent steps using Applied’s Endura® Avenir™ RFPVD system has become the industry’s preferred solution. HKMG transistors also benefit from Applied’s epitaxial deposition technologies such as Centura® RP Epi along with film treatments including RadOx™ RTP, Radiance® RTP and DPN which are used to fine-tune the transistor characteristics for optimum performance.

“Draco hard mask and Black Diamond low-k dielectric are being adopted by leading DRAM customers, and the first HKMG DRAMs are now being introduced,” added Dr. Achutharaman. “Applied Materials projects billions of dollars in revenue growth as these DRAM inflections play out over the next several years.”

Additional information about the growth outlook for these technologies is being provided at Applied’s 2021 Memory Master Class being held later today. For more information, please visit the investor page of our website at

Wednesday, May 5, 2021

BASF and Umicore have entered a non-exclusive patent cross-license agreement for battery cathode active materials and their precursors

BASF and Umicore have entered into a non-exclusive patent cross-license agreement covering a broad range of cathode active materials (CAM) and their precursors (PCAM), including chemistries such as nickel cobalt manganese (NCM), nickel cobalt aluminum (NCA), nickel cobalt manganese aluminum (NCMA) and lithium rich, high manganese high energy NCM (HE NCM).

CAMs are critical for the performance, safety and cost of lithium-ion batteries used in modern electromobility and other applications. The interplay between PCAM and CAM and the development of these materials are crucial to maximize battery cell performance. For many years, BASF and Umicore have been investing intensively in product innovation for low, medium and high nickel PCAM and CAM resulting in each company owning sizeable and largely complementary patent portfolios.

BASF Research on high-performance battery materials at BASF’s laboratory in Ludwigshafen, Germany (above). Umicore 3D open battery cell (below).

Building on each other’s strong product technology expertise to support the technological needs of their customers, BASF and Umicore have entered into a landmark patent agreement allowing both partners to combine a wider range of IP-protected technologies related to features such as chemical composition, powder morphology and chemical stability. The agreement increases both parties’ ability to customize their materials to meet the increasingly diversified and complex customer requirements at the battery cell and application level. Furthermore, through this agreement both parties can increase even more their product development speed demonstrating their commitment to addressing the main challenges e-mobility is facing, such as energy density, safety and cost while enhancing transparency and reducing IP-risks for battery cell manufacturers and their customers.

The agreement covers more than 100 patent families filed in Europe, US, China, Korea and Japan. Both parties retain the right to enforce their own IP-rights against third parties in the future.

“This agreement with Umicore enables even faster, more sustainable and innovative battery materials development to serve our customers including battery cell manufacturers and automotive,” said Dr. Peter Schuhmacher, President of BASF Catalysts. “The continuous development of battery materials will accelerate the transformation towards full electrification and thus support the world’s efforts to fight climate change.”
Marc Grynberg, CEO of Umicore, commented: “This agreement with BASF is an important step in promoting cathode material innovation. It strengthens our technology positioning and further increases our ability to develop bespoke solutions which meet the most stringent performance and quality standards of our battery and automotive customers.”

Imec and AIXTRON Demonstrate 200 mm GaN Epitaxy on AIX G5+ C

Imec and AIXTRON Demonstrate 200 mm GaN Epitaxy on AIX G5+ C for 1200V Applications with Breakdown in Excess of 1800V

LEUVEN (Belgium), APRIL 29, 2021 — Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and AIXTRON, the leading provider of deposition equipment for compound semiconductor materials, have demonstrated epitaxial growth of gallium-nitride (GaN) buffer layers qualified for 1200V applications on 200mm QST® substrates, with a hard breakdown exceeding 1800V. The manufacturability of 1200V-qualified buffer layers opens doors to highest voltage GaN-based power applications such as electric cars, previously only feasible with silicon-carbide (SiC)-based technology. The result comes after the successful qualification of AIXTRON’s G5+ C fully automated metal-organic chemical vapor deposition (MOCVD) reactor at imec, Belgium, for integrating the optimized material epi-stack.

AIX G5+ C reactor module with cassette-to-cassette wafer handler (

Wide-bandgap materials gallium-nitride (GaN) and silicon-carbide (SiC) have proved their value as next-generation semiconductors for power-demanding applications where silicon (Si) falls short. SiC-based technology is the most mature, but it is also more expensive. Over the years tremendous progress has been made with GaN-based technology grown on for example 200mm Si wafers. At imec, qualified enhancement mode high-electron-mobility transistors (HEMTs) and Schottky diode power devices have been demonstrated for 100V, 200V and 650V operating voltage ranges, paving the way for high-volume manufacturing applications. However, achieving operating voltages higher than 650V has been challenged by the difficulty of growing thick-enough GaN buffer layers on 200mm wafers. Therefore, SiC so far remains the semiconductor of choice for 650-1200V applications – including for example electric cars and renewable energy.

For the first time, imec and AIXTRON have demonstrated epitaxial growth of GaN buffer layers qualified for 1200V applications on 200mm QST® (in SEMI standard thickness) substrates at 25°C and 150°C, with a hard breakdown exceeding 1800V. Denis Marcon, Senior Business Development Manager at imec: “GaN can now become the technology of choice for a whole range of operating voltages from 20V to 1200V. Being processable on larger wafers in high-throughput CMOS fabs, power technology based on GaN offers a significant cost advantage compared to the intrinsically expensive SiC-based technology.”

Key to achieving the high breakdown voltage is the careful engineering of the complex epitaxial material stack in combination with the use of 200mm QST® substrates, executed in scope of the IIAP program The CMOS-fab friendly QST® substrates from Qromis have a thermal expansion that closely matches the thermal expansion of the GaN/AlGaN epitaxial layers, paving the way for thicker buffer layers – and hence higher voltage operation.

Dr. Felix Grawert, CEO and President of AIXTRON “The successful development of imec’s 1200V GaN-on-QST® epi-technology into AIXTRON’s MOCVD reactor is a next step in our collaboration with imec. Earlier, after having installed AIXTRON G5+C at imec’s facilities, imec’s proprietary 200mm GaN-on-Si materials technology was qualified on our G5+ C high-volume manufacturing platform, targeting for example high-voltage power switching and RF applications and enabling our customer to achieve a rapid production ramp-up by pre-validated available epi-recipes. With this new achievement, we will be able to jointly tap into new markets.” Currently, lateral e-mode devices are being processed to prove device performance at 1200V, and efforts are ongoing to extend the technology towards even higher voltage applications. Next to this, imec is also exploring 8-inch GaN-on-QST® vertical GaN devices to further extend the voltage and current range of GaN-based technology.

EMD Electronics Creates Center of Excellence for Atomic Engineering by Combining Thin Films R&D Lab with Intermolecular

  • Unique capabilities with novel organo-metallic precursors and applications will enable customers to explore and test advanced materials for next-generation devices
  • Centralized innovation hub to speed up the delivery of material solutions to customers
San Jose, Calif., May 04, 2021 – EMD Electronics, a business of Merck KGaA, Darmstadt, Germany, today announced the creation of a Center of Excellence for atomic engineering at Intermolecular’s San Jose facility. The capabilities of EMD Electronic’s Thin-Films Applications R&D lab have been merged with Intermolecular’s advanced electronics capabilities to create a centralized innovation hub for our customers. This will enable seamless integration of testing and deposition of new materials for next-generation devices.

EMD Electronics "We've established a Center of Excellence for Atomic Engineering! Our  Thin Films Applications R&D lab has merged with Intermolecular's advanced electronics capabilities to create a centralized innovation hub for our customers. This will enable seamless integration of testing and deposition of new materials for next-generation semiconductors." (Quote and photo above from EMD Electronics LinkedIn Announcement LINK)

“Intermolecular’s 150,000 sqft facility in the heart of Silicon Valley is the perfect center to converge materials innovation and testing for our global customers,” said Anand Nambiar, Head of Semiconductor Materials business unit at EMD Electronics. “To continue scaling down to advance nodes and develop next-generation applications, a reliable supply of innovative materials is required. Our expertise in atomic engineering in combination with Intermolecular’s unique tools and processes, will enable our customers to test, validate, prototype and introduce new advanced technologies and materials faster in the market.”

“Ongoing miniaturization drives our customers to build their devices from the atoms up in complex 3D arrangements. Our advanced deposition materials allow them to create differentiation in their products,” said Casper van Oosten, Business Field Head and Managing Director for Intermolecular, Inc. “Until now, the value chain process to test and validate materials involved multiple steps and was time consuming. By combining capabilities, we now have access to the right team, tools and data and can provide our customers with a more seamless integration to prove new organometallic materials for electronic applications.”

On March 4, Merck KGaA, Darmstadt, Germany moved the Silicon Valley Innovation Hub to San Jose’s Intermolecular site creating a unique space for innovation and collaboration with start-ups at the intersection of life science, healthcare and electronic materials. The building boasts 30,000 square feet of cleanroom, chemical labs, offices, a collaboration area and event spaces. Intermolecular, Inc. (“Intermolecular”) is the trusted partner for materials innovation and a wholly-owned subsidiary of the EMD Electronics business of Merck KGaA, Darmstadt, Germany.

About EMD Electronics

EMD Electronics is the North America electronics business of Merck KGaA, Darmstadt, Germany. EMD Electronics’ portfolio covers a broad range of products and solutions, including high-tech materials and solutions for the semiconductor industry as well as liquid crystals and OLED materials for displays and effect pigments for coatings and cosmetics. Today, EMD Electronics has approximately 2,000 employees around the country with regional offices in Tempe (AZ) and Philadelphia (PA). For more information, please visit

About Intermolecular

Intermolecular is a trusted partner for materials innovation and the Silicon Valley science hub of Merck KGaA, Darmstadt, Germany and its electronics business. Intermolecular explores, tests and develops advanced materials that are revolutionizing the next generation of electronics that make lives easier, entertaining and more productive. For more than 15 years, the team, methodologies and quality data have driven impactful outcomes, market opportunities and innovative product designs for customers.

About Merck KGaA, Darmstadt, Germany

Merck KGaA, Darmstadt, Germany, a leading science and technology company, operates across healthcare, life science and electronics. Around 58,000 employees work to make a positive difference to millions of people’s lives every day by creating more joyful and sustainable ways to live. From advancing gene editing technologies and discovering unique ways to treat the most challenging diseases to enabling the intelligence of devices – the company is everywhere. In 2020, Merck KGaA, Darmstadt, Germany, generated sales of € 17.5 billion in 66 countries.

The company holds the global rights to the name and trademark “Merck” internationally. The only exceptions are the United States and Canada, where the business sectors of Merck KGaA, Darmstadt, Germany operate as EMD Serono in healthcare, MilliporeSigma in life science, and EMD Electronics. Since its founding 1668, scientific exploration and responsible entrepreneurship have been key to the company’s technological and scientific advances. To this day, the founding family remains the majority owner of the publicly listed company.

Tuesday, May 4, 2021

CBS 60 Minutes - Chip shortage highlights U.S. dependence on fragile supply chain

Seventy-five percent of semiconductors, or microchips — the tiny operating brains in just about every modern device — are manufactured in Asia. Lesley Stahl talks with leading-edge chip manufacturers, TSMC and Intel, about the global chip shortage and the future of the industry.
  • Pat Gelsinger: 25 years ago, the United States produced 37% of the world's semiconductor manufacturing in the U.S. Today, that number has declined to just 12%
  • Within the world of global collaboration, there's intense competition. Days after Intel announced spending $20 billion on two new fabs, TSMC announced it would spend $100 billion over three years on R&D, upgrades, and a new fab in Phoenix, Arizona, Intel's backyard, where the Taiwanese company will produce the chips Apple needs but the Americans can't make.

Intel CEO Pat Gelsinger shows CBS correspondent Lesley Stahl a silicon wafer.

Monday, May 3, 2021

APTC from South Korea is developing CVD, ALD and oxide etcher systems as it expands its portfolio

Since 2002, APTC has engaged in the manufacturing of dry etcher systems for mass semiconductor production. Today, the company supplies 300mm plasma etching systems, 200mm plasma etching systems, plasma doping systems, and light-emitting-diode etching systems. Over the past 19 years, APTC has been an established supplier for SK Hynix in South Korea and its mass production subsidiaries in China. SK Hynix is the second-largest memory chipmaker and third-largest semiconductor company globally.

300 mm Leo Poly Etcher system from APTC

With its numerous patents, awards, original plasma source technology and market leadership as South Korea’s sole domestic supplier of poly etching equipment, APTC is gearing up for growth at home and overseas. Fully committed to research and development (R&D) in pursuit of quality and innovation, APTC has invested US$20 million in American engineering capabilities, maintaining an R&D office in the United States, where it aims to work with tier-one semiconductor companies.

Listed on the Korea Exchange under the leadership of its current CEO, the company has revitalized its business strategy with plans to explore new markets, new clients, and new technologies. The state-of-the-art plasma technology also has a number of applications in the next-generation dry etch sector and its related innovations.

In semiconductor manufacturing, chemical vapor deposition (CVD) is a method used to produce high-performance and high-quality solid materials such as thin film in a vacuum, while atomic layer deposition (ALD) is a vapor phase technique of laying thin films on a substrate. APTC is developing CVD, ALD, and oxide etcher systems as it expands its portfolio of offerings.

Source: New strategy, markets and innovation fuel APTC’s rise in semiconductor etcher systems (LINK)

Saturday, May 1, 2021

Jusung to spend 36.3 billion won to build new production facility

Fab ALD and CVD equipment firm Jusung Engineering will spend 36.3 billion won to build a new production facility in Gwangju, where the company is based, it said on Thursday. In addition, it is reported that Jusung recently sold SK Hynix 30 ALD systems.

Source: Jusung to spend 36.3 billion won to build new production facility

Nanexa AB started the first clinical study with ALD based PharmaShell® at the Karolinska University Hospital

Nanexa AB (publ) today announces that the company has started its first clinical study with PharmaShell®, a phase I study in Nanexa's product project NEX-18, at the Karolinska University Hospital.

The study aims to show that the company's NEX-18 product, a long-acting formulation of azacitidine (the active substance in the drug Vidaza), provides the desired safety and pharmacokinetic profile. In the study, two doses of NEX-18 will be studied. The study will be conducted at Karolinska University Hospital in Stockholm and Akademiska Sjukhuset in Uppsala.

“The start of this study is a very big milestone in Nanexa's development. It is with great enthusiasm that we now see that the study is getting started. We expect the study to be completed during the third quarter.”, said David Westberg, CEO of Nanexa.

The NEX-18 product is being developed to improve the treatment of MDS (Myelodysplastic Syndrome), a form of hematological cancer that mainly affects the elderly. This is done by utilizing the unique properties of the PharmaShell® concept to create a controlled release depot formulation. Today's treatment means that injections are given at hospitals seven days in a row each month. The goal of the NEX-18 project is to simplify treatment by only having to give one injection. In addition to greatly simplifying for patients, Nanexa sees that NEX-18 will provide significant cost savings compared to current treatment.

“With the results of this study, we intend to continue the clinical development with a phase II study to achieve clinical Proof of Concept. After that, the goal is to run NEX-18 further towards commercialization, either through a license partner or as an own project, whatever option is deemed to create most value for Nanexa”, said David Westberg.

ALD – The coating technology behind the drug delivery system PharmaShell®

The technology used by Nanexa to manufacture the shells that make up PharmaShell® is Atomic Layer Deposition (ALD). In ALD, reactive gases are used which, with atomic layer by atomic layer, build up a surface coating with high precision. ALD has been used in the electronics industry for decades and is thus well established for larger scale production and automation.

ALD can also be used at low temperatures, down to room temperature, unlike other surface coating techniques which usually use considerably higher deposition temperatures, thereby risking inactivating the drug. A further advantage of ALD is that the coating is carried out under dry conditions, which makes it possible to coat drugs that are quickly dissolved in water or other solvents.

By building up an atomic layer for atomic layer with ALD, the thickness of the coating can be controlled with extremely high precision. Drug particles of various sizes and shapes can be coated since the only thing required for coating to be formed is that the reaction gases can reach the surface.
About Nanexa AB (publ)

Nanexa AB is a nanotechnology drug delivery company focusing on the development of PharmaShell®, a new and groundbreaking drug delivery system with great potential in a number of medical indications. Within the framework of PharmaShell®, Nanexa has partnership agreements with among others, AstraZeneca.