Thursday, August 29, 2019

Picosun launch new high power Micro Wave Plasma ALD

ESPOO, Finland, 29th August 2019 – Picosun Group, the leading supplier of AGILE ALD® (Atomic Layer Deposition) thin film coating solutions, reports excellent results obtained with its next generation R&D PEALD (plasma-enhanced ALD) technology.

PEALD enables deposition at low temperatures and of several materials that could not be deposited with thermal process only. The drawback of PEALD, however, is damage to the sample surface, caused by ion bombardment. Picosun’s solution to this is remote plasma method, where the plasma source is located high enough above the sample, and the reactive species hitting the surface are radicals, not high-energy ions.

“Picosun’s operating philosophy is based on constant improvement and development, as we want to offer our customers always the best-in-class, leading quality ALD solutions. Our Picoplasma™ equipment has been a hit product in the R&D community since its launch, and we have now upgraded it to a completely new level, to enable even faster processing with superior film quality and purity,” says Dr. Jani Kivioja, CTO of Picosun Group.

Picosun’s next generation PEALD solution is based on remote, high power microwave plasma (MWP). The compact, lightweight plasma generator can be integrated to existing PICOSUN® R&D ALD reactors as such. The new plasma-ALD solution realizes deposition with virtually no added particles, with extremely low metal contamination and with far shorter cycle times compared to the previously used method. Excellent film quality and uniformity have been obtained(*), and the new MWP allows wider operating range (in terms of plasma parameters) which widens also the selection of available ALD processes.

“We are pleased to provide our customers with our new, thoroughly upgraded plasma-ALD solution. There are several important application areas, such as medical devices and MEMS, where substrates are sensitive and require processing at low temperatures. Now we have an ideal solution to this, which will again facilitate ALD’s breakthrough to yet new components and devices,” continues Dr. Kivioja.

(*) Film properties, SiO2 as an example:
Wafer size Dep. temperature GPC Film non-uniformity (1σ, 5mm EE, 49pts) Leakage current (@4MV) Particles (@>0,25µm) Metal contamination (Fe, Ti, Cr, Mn, Ni, Cu, Zn atoms)
200 mm 400 °C 0.86 Å/cycle 1.7 % (~10 nm film) 2.1 x 10-8 A/cm2 < 60 < 2 x 1010 /cm2

Tuesday, August 27, 2019

New coating paves the way for low weight lithium metal batteries

A Dynamic, Electrolyte-Blocking, and Single-Ion-Conductive Network for Stable Lithium-Metal Anodes

Zhiao Yu, David G. Mackanic, Wesley Michaels, Jian Qin, Yi Cui, Zhenan Bao
Published:August 26, 2019 DOI:


  • A multifunctional network material is proposed to stabilize lithium-metal anodes
  • Improved cyclability is achieved for high-voltage lithium-metal full battery
  • Direct lithium-metal processability enables practical application
  • Crosslinking chemistry is tuned to study the synergistic stabilizing effects

Implementation of lithium (Li)-metal anodes requires developments to solve the heterogeneity and instability issues of naturally formed solid-electrolyte interphase (SEI). The artificial SEI, as an alternative, enables an ideal interface by regulating critical features such as fast ion transport, conformal protection, and parasitic reaction mitigation. Herein, for the first time, we integrate all of these desired properties into a single matrix, the dynamic single-ion-conductive network (DSN), as a multifunctional artificial SEI. The DSN incorporates the tetrahedral Al(OR) 4 − (R = soft fluorinated linker) centers as both dynamic bonding motifs and counter anions, endowing it with flowability and Li + single-ion conductivity. Simultaneously, the fluorinated linkers provide chain mobility and electrolyte-blocking capability. A solution-processed DSN coating was found to simultaneously hinder electrolyte penetration, mitigate side reactions between Li and electrolyte, maintain low interfacial impedance, and allow homogenous Li deposition. With this coating, long cycle life and high Coulombic efficiency are achieved for Li-metal battery in a commercial carbonate electrolyte.

Surface-Inhibiting Effect in Chemical Vapor Deposition of Boron–Carbon Thin Films from Trimethylboron

Here are deep insights to the understand of conformal boron-carbon films in very high aspect ratio structures by researchers from Linköping University, Sweden. If you don't have the journal access, please check the pre-print (LINK).

Surface-Inhibiting Effect in Chemical Vapor Deposition of Boron–Carbon Thin Films from Trimethylboron

Laurent Souqui, Hans Högberg, Henrik Pedersen
Chem. Mater. 201931155408-5412 LINK

We use the ability to control surface chemistry in chemical vapor deposition (CVD) to deposit boron–carbon films into pores with an aspect ratio of 60:1 without clogging the opening, and into lateral trenches with ratios of up to 2000:1. In contrast to many other surface-controlled CVD processes, operating at low temperatures (100–250 °C) and pressures (10–1000 Pa), we use trimethylboron at a higher temperature (700 °C) and pressure (5000 Pa), affording a surface-inhibited CVD process in hydrogen ambient. We show that the deposition rate is highly dependent on the partial pressure of hydrogen; decreasing proportionally to the logarithm of the partial pressure. The surface-controlled effect is not encountered in argon ambient. We propose that this is explained by a competitive adsorption of growth species and inhibiting dihydrogen or atomic hydrogen species following a Temkin isotherm.

Team Hjulbusarna Motrosport in Swedish Badhotelrallyt 2019

Team Hjulbusarna Motrosport Sven Karlsson/Prof. Henrik Pedersen in a Volvo 244 bursting through the Swedish Badhotellrallyt 2019. BALD Engineering is proud to sponsor the team!

Monday, August 26, 2019

Vapor-deposited zeolitic imidazolate frameworks as gap-filling ultra-low-k dielectrics (Open Access)

Researches at Imec/KU Leuven show that MOF-CVD ZIF films demonstrate dielectric and mechanical characteristics competitive with state-of-the-art porous OSG dielectrics (a low-k organosilicate glass). They also argue that the MOF-CVD integration process may outperform porous OSG dielectrics in future integration schemes because of the gap-filling nature of the deposition process. Please check details below as well as quite some good stuff available in the Supplementary Information

Vapor-deposited zeolitic imidazolate frameworks as gap-filling ultra-low-k dielectrics (Open Access)

Mikhail Krishtab, Ivo Stassen, Timothée Stassin, Alexander John Cruz, Oguzhan Orkut Okudur, Silvia Armini, Chris Wilson, Stefan De Gendt & Rob Ameloot

Nature Communications volume 10, Article number: 3729 (2019) DOI

Abstract: The performance of modern chips is strongly related to the multi-layer interconnect structure that interfaces the semiconductor layer with the outside world. The resulting demand to continuously reduce the k-value of the dielectric in these interconnects creates multiple integration challenges and encourages the search for novel materials. Here we report a strategy for the integration of metal-organic frameworks (MOFs) as gap-filling low-k dielectrics in advanced on-chip interconnects. The method relies on the selective conversion of purpose-grown or native metal-oxide films on the metal interconnect lines into MOFs by exposure to organic linker vapor. The proposed strategy is validated for thin films of the zeolitic imidazolate frameworks ZIF-8 and ZIF-67, formed in 2-methylimidazole vapor from ALD ZnO and native CoOx, respectively. Both materials show a Young’s modulus and dielectric constant comparable to state-of-the-art porous organosilica dielectrics. Moreover, the fast nucleation and volume expansion accompanying the oxide-to-MOF conversion enable uniform growth and gap-filling of narrow trenches, as demonstrated for 45 nm half-pitch fork-fork capacitors.
The preparation method is described in detail in the paper and includes a number of PVD, ALD and CVD process steps as follows:

Preparation of MOF-CVD precursor layers on blanket wafer

The layers of ALD ZnO and PVD Co were prepared on highly-doped p++ Si substrates. ALD ZnO deposition was realized at 120 °C by 30 cycles of diethyl zinc (DEZ)/water precursor pulses separated by N2 purge steps (Savannah S200, Veeco Instruments Inc.). PVD Co film was sputtered on Ar-plasma precleaned Si substrate (NC7900, Canon Anelva Corp.).

Preparation of MOF-CVD precursor layer on patterned wafer

The fork–fork capacitor structures featuring 45 nm line/space width were prepared on p-type 300 mm Si-wafers according to a modified integration route (Supplementary Fig. 2) based on using sacrificial amorphous carbon (a-C) layer to form a pattern of passivated copper wires. The initial stack of layers above the substrate consisted of 1000 nm SiOx, 30 nm SiCN diffusion barrier, 90 nm a-C, and a multilayer hard-mask stack. After formation of a device pattern in the top positive resist coating with 193 nm immersion lithography, the pattern features were then transferred into the underlying a-C film. Following the wet removal of hard-mask residues, the exposed surfaces of a-C/SiCN were coated with 3 nm ALD TiN. The subsequent metallization steps included sputtering of 20 nm Cu seed, electroplating of 500 nm Cu, and chemical mechanical polishing down to the a-C film. The removal of a-C sacrificial layer was done in He/H2 remote plasma. Afterward, the metallic lines were passivated with a non-conformal 3 nm PECVD SiCN barrier layer and then additionally covered with a conformal 2 nm PEALD SiNx film. The deposition of CVD Co was realized at 200 °C on VECTOR Excel tool cluster (Lam Research Corp.). Before deposition of CVD Co on the SiCN/SiNx-passivated Cu pattern, the growth conditions were optimized on blanket SiNx surface to obtain 4.0 ± 1.0 nm Co layer across 300 mm wafer (assessed by RBS). ALD ZnO deposition on the metal lines passivated with SiNx layer was performed by applying the same growth conditions as used on blanket wafers (see above).

Vapor-phase conversion process (MOF-CVD)

For the conversion to appropriate ZIF layer, samples with precursor layers were placed in a glassware reactor (Supplementary Fig. 1). The glassware reactor was connected to a vacuum pump via a manual valve. Upon assembly the reactor was checked for leaks. The glass tube containing 2-methylimidazole powder (99%, CAS #693-98-1, Sigma-Aldrich) was connected to one of the ports of the glassware reactor via another manual valve. The whole setup was placed in a furnace preheated at 120 °C. After the temperature stabilization (15 min), the valve to the vacuum pump was opened, and the reactor was evacuated until pressure stabilization below 10 mbar. The vacuum valve was then closed and the valve to the 2-methylimidazole tube opened. The exposure of samples to vapors of 2-methylimidazole was set to 120 min, after which the precursor valve was closed, and the sample area of the reactor was kept under dynamic vacuum for 15 min to remove the unreacted organic linker from the sample surface and pores of formed ZIF films (activation). Finally, the reactor was let to cool down before the samples could be taken out for further characterization.
Two proposed routes for the integration of ultra-low-k MOF dielectrics in on-chip interconnects via the MOF-CVD process. Routes A and B differ in how the MOF precursor layer is formed around the interconnect wires. In Route A, metal oxide to be converted into MOF is deposited after passivation of metal lines, while Route B relies on selective conversion of metal oxide formed through controlled oxidation of the metal pattern From: Vapor-deposited zeolitic imidazolate frameworks as gap-filling ultra-low-k dielectrics
Validation of the MOF-CVD process and characterization of the deposited MOF thin films. a Schematic representation of the conversion of ALD ZnO and native CoOx to ZIF-8 and ZIF-67 and the corresponding increase in thickness as measured by spectroscopic ellipsometry (SE) and from SEM cross-sectional images. b Baseline-corrected GI-XRD diffraction patterns together with simulated powder diffractogram for ZIF-8. c Ellipsometric porosimetry with methanol and water as adsorbates. The amount of adsorbate corresponds to the change of the ellipsometric angle Delta (@633 nm) relative to the value recorded before introducing probe molecules. The values are normalized against the Delta change measured at methanol saturation pressure. d AFM topography images of MOF-CVD films: ZIF-8 (purple frame) and ZIF-67 (light blue frame) From: Vapor-deposited zeolitic imidazolate frameworks as gap-filling ultra-low-k dielectrics
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made. The images or other third party material in this article are included in the article’s Creative Commons license, unless indicated otherwise in a credit line to the material. If material is not included in the article’s Creative Commons license and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this license, visit

Thursday, August 22, 2019

Micron has started volume production of 10 nm-class DRAM (1z nm)

Micron announced on Thursday that it had started volume production of memory chips using its 3rd Generation 10 nm-class fabrication technology (also known as 1Z nm). The first DRAMs to be made using Micron’s 1Z nm process are 16 Gb monolithic DDR4 and LPDDR4X devices. 
The company claims that its 16 Gb DDR4 device consumes 40% less power than two 8 Gb DDR4 DRAMs (presumably at the same clocks). Meanwhile, Micron’s 16 Gb LPDDR4X ICs will bring an up to 10% power saving. One of the first products to use the company’s 16 Gb DDR4 devices will be high-capacity (e.g., 32 GB and higher) memory modules for desktops, notebooks, and workstations.
Source: Anandtech LINK
By Abhishekkumar Thakur

Thursday, August 15, 2019

ALD at V2019 in Dresden October 9th to 10th with Keynote by Dr. Suntola, Millenium Technology Prize winner of 2018

We are very happy to announce the almost complete program for the ALD Workshop at V2019 in Dresden, October 9th to 10th organized by EFDS:
  • Keynote Lecture to Atomic Layer Deposition by Dr. Tuomo Suntola, Millenium Technology Prize 2018
  • Presentations to “Atomic Layer Deposition” Program (Link) 
  • Workshop 5: October 9 – October 10, 2019Industrial Exhibition for Surface Technologies and adjacent Branches : Medical, Optics, Energy and ALD
  • Industrial Evening & V-Dinner
  • Information to Industrial International Funding
Downloads●  Profile of V2019 [PDF]
●  Time Schedule of V2019 [PDF]
●  Industrial Exhibition for Exhibitors [PDF]
●  Program to Atomic Layer Deposition (engl. Language) [PDF]
●  List of Exhibitors (Link)
●  Information for students and junior employees [PDF]
●  Information for job advertisements [PDF]

Lecutues | 2019.10.09 - FREE FOR ALL - No registration fee required

Lecture, part I

"45 years of ALD"
Prof. Tuomo Suntola, Picosun Oy, Espoo, Finland - Millenium Technology Prize 2018Abstract [PDF]
© Picture: By courtesy of Technology Academy Finland.
Lecture, part II
"Current and Emerging ALD Processes, Precursors and Applications in High Volume Production"
Jonas Sundqvist, Fraunhofer-Institut für Keramische Technologien und Systeme IKTS, Dresden, Germany
Abstract [PDF]
Presenations | 2019.09.10 & 2019.10.10

"Advances in quantitative characterization of thin films with help of AFM-based methods"
Malgorzata Kopycinska-Müller, Fraunhofer-Institut für Keramische Technologien und Systeme IKTS, Dresden, Germany
Abstract [PDF]

"In situ metrology for Atomic Layer Deposition processes"
Martin Knaut, Technische Universität Dresden, IHM, Dresden, Germany
Abstract [PDF]
"Conformality in Atomic Layer Deposition"
Véronique Cremers, Plasma Electronic GmbH, Neuenburg, Germany
Abstract [PDF]

"Oxides for Electronics"
Mari Napari, Department of Materials Science and Metallurgy, University of Cambridge, Cambridge, UK
Abstract [PDF]
"Atomic Layer Deposition of Indium Nitride using Hexacoordinated In–N Bonded Precursors and NH3 Plasma"
Nathan O´Brian, Linköping University, Linköping, Sweden
Abstract [PDF]
"Multi-layer Stacked ALD Coating for Hermetic Encapsulation of Implantable Biomedical Microdevices"
Christoph Hossbach, Picosun group, Espoo, Finnland
Abstract [PDF]
"Fast plasma ALD employing de Laval Nozzles for high velocity precursor injection"
Abhishekkumar Thakur, Plasway-Technologies GmbH, Dresden, Germany
Abstract [PDF]

More to follow...

Available: VPHA poster at AVS ALD 2019

[VHPA:] The VPHA poster on the ALD doctoral thesis list was updated, as planned, for the AVS 19th International Conference on Atomic Layer Deposition (ALD 2019) featuring the 6th International Atomic Layer Etching Workshop (ALE 2019), Figure 1 of the poster below. The poster will be included in the AVS collections, and it is currently available via the website.

  • Link to poster: here 
  • Link to abstract: here
  • Link to supplementary information - with full author list: here
The doctoral thesis collection is still certainly missing entries. Suggestions for additions are welcome. Please preferably provide the information via the Google Sheets file, which all can edit: VPHA-thesis-to-be-added.

Virtual Project on the History of ALD (VPHA) - in atmosphere of Openness, Respect, and Trust

Tuesday, August 13, 2019

ALDFun Workshop at TU Delft (NL) are now online

The presentations form the ALDFundamentals workshop organized at TU-Delft (NL) as videos of speaker and Powerpoint are now available online.

ALDFundamentals: Presentations LINK

Monday, August 12, 2019

Review of AVS ALD2019 by Prof. Kessels

Please finde here a review of AVS ALD2019 / ALE 2019 by Prof. Kessels, whom recieved the ALD Innovator Award and gave a presentation at the plenary session on Monday morning.

Report: Atomic Limits LINK
Presentation download: Atomic Scale Processing: from Understanding to Innovation LINK

BALD Engineering ALD News blog see doubled visitor traffic last 18 months

The overall monthly visitors to the News Blog doubled in 2018 from about 10,000 to about 20,000. Growth was seen in both the main blog section for ALD Technology news and the ALD Financial News.

The recent trend is increased traffic from India and China. India and China used to contribute to less than 10% of the visitor traffic, but recently they account for more than 25%. The typical monthly geographical origin of the visitors are:
  • 25% USA
  • 25% India and China
  • 25% Germany, France, Russia, Japan, Israel, Finland, and South Korea
  • 25% Rest of the world
Please contact Jonas Sundqvist ( for :
  • Banner sponsoring
  • Promotional blogs & press releases
  • Announcing ALD events (conferences, workshops, exhibitions)
  • Become a guest blogger

Friday, August 9, 2019

Lam Research Adds Global Wafer Stress Management Solutions to Portfolio to 3D NAND Scaling

FREMONT, Calif., Aug. 07, 2019 (GLOBE NEWSWIRE) — Lam Research Corp. (Nasdaq: LRCX) today announced new solutions to help customers increase chip memory density, which is needed for applications such as artificial intelligence and machine learning. With the introduction of VECTOR® DT for backside deposition and EOS® GS wet etch for film removal on backside and bevel, Lam continues the expansion of its stress management product portfolio.

While high aspect ratio deposition and etching are key enablers for 3D NAND scaling, the combination of increasing the number of layers while controlling wafer bow due to cumulative stress in the film stack has become a major challenge. Such stress-induced wafer distortion has a significant impact on wafer yield due to degraded lithography depth-of-focus, overlay performance, and structural distortion. To improve overall yield, wafer-, die-, and feature-level stresses need to be carefully managed at various steps throughout the entire manufacturing process flow, at times potentially resulting in the preclusion of otherwise performance-enhancing process steps due to their stress characteristics.

Designed to provide a cost-effective solution for controlling wafer bow in 3D NAND manufacturing, the VECTOR DT system is the newest addition to Lam’s plasma-enhanced chemical vapor deposition (PECVD) product family. VECTOR DT provides a single-step solution for wafer shape management by depositing a tunable counter-stress film on the back of the wafer without contacting the front side, thereby enabling improved lithography results, reduced bow-induced failures, and integration of high performance but highly stressed films. With strong customer adoption since its debut, the VECTOR DT installed base continues to grow as customers are transitioning to more than 96 layers.

In addition to depositing a counter stress film, Lam provides the flexibility to remove backside films, allowing customers to adjust wafer stress during the 3D NAND manufacturing flow. Lam’s EOS GS wet etch product complements the VECTOR DT by simultaneously removing backside and bevel films with industry-leading wet etch uniformity, while fully protecting the wafer front side. As part of a comprehensive wafer bow management solution, Lam’s EOS GS has also been adopted by memory manufacturers worldwide.

“As our customers continue to dramatically increase the number of memory cell layers, the cumulative stress and wafer bow can exceed the limits of a lithography tool. Minimizing stress-induced distortion is critical for achieving the desired yield and enabling the cost-per-bit roadmap,” said Sesha Varadarajan, senior vice president and general manager of the deposition product group at Lam Research. “With the addition of the VECTOR DT and EOS GS systems, we are expanding our stress management solutions portfolio for managing global stress in support of our customers’ vertical scaling roadmap.”
Source: Lam Research LINK

By Abhishekkumar Thakur

Thursday, August 8, 2019

Atomic Layer Deposition of Emerging 2D Semiconductors, HfS2 and ZrS2, for Optoelectronics

Miika Mattinen from Prof. Mikko Ritala's group, University of Helsinki, reports the ALD growth of 2D HfS2 and ZrS2—the potential rivals of the hot favorite 2D semiconductors MoS2 and WSe2. 

Abstract: Semiconducting 2D materials are studied intensively because of their promising performance in diverse applications from electronics to energy storage and catalysis. Recently, HfS2 and ZrS2 have emerged as potential rivals for the commonly studied 2D semiconductors such as MoS2 and WSe2, but their use is hindered by the difficulty of producing continuous films. 

Herein, we report the first atomic layer deposition (ALD) processes for HfS2 and ZrS2 using HfCl4 and ZrCl4 with H2S as the precursors. We demonstrate the deposition of uniform and continuous films on a range of substrates with accurately controlled thicknesses ranging from a few monolayers to tens of nanometers. The use of semiconductor industry-compatible precursors and temperatures (approximately 400 °C) enables facile upscaling of the process. The deposited HfS2 and ZrS2 films are crystalline, smooth, and stoichiometric with oxygen as the main impurity. 

By Abhishekkumar Thakur

Tuesday, August 6, 2019

ALD online education course Summer 2019 by Prof. Han-Bo-Ram Lee, of Incheon National University.

Here is an excellent source of ALD online education by Prof. Han-Bo-Ram Lee, of Incheon National University.

ALD Class in English 2019 Summer
1. Review of Fundamentals (
2. Introduction of ALD (
3. Basic Growth Characteristics of ALD (
4. ALD Precursors & Reactants (
5. ALD Systems (
6. ALD Applications for Si Devices (
7. Atomic Crafting Beyond ALD (

Monday, August 5, 2019

ASM International NV 2019 Q2 Results - Earnings Call

ASM International N.V. (Euronext Amsterdam: ASM) today reports its second quarter 2019 operating results (unaudited) in accordance with IFRS.

• New orders were €373 million. Excluding €103 million related to the patent litigation settlement new orders were €270 million.

• Net sales for the second quarter 2019 were €363 million. Excluding €103 million related to the patent litigation settlement, net sales were €260 million and increased 5% compared to the previous quarter.

• Gross profit margin was 59.0% in Q2 2019 and 42.8% excluding the patent litigation settlement compared to 41.3% in the previous quarter.

• Operating result increased to €150 million. Excluding the patent litigation settlement operating result was stable at €47 million compared to the previous quarter.

• Normalized net earnings, including the patent litigation settlement, for the second quarter 2019 increased by €72 million compared to Q1 2019. Besides the positive impact of the patent litigation settlement net earnings in Q2 were negatively impacted by adverse currency effects and the increase in taxes due to the full utilization of the remaining net operating losses in the Netherlands. Results from investments decreased to €2 million.


"Logic bookings increased compare to Q1 and were primarily driven by 10 nanometer related demand and early tools for 7nm. Foundry orders decreased so much compared to the record high level in Q1 and primarily reflected its further investments into 5 nm node. Memory orders during the second quarter increased compared to a low level in Q1 mainly driven by DRAM, The increased DRAM bookings during the quarter were largely related to specific customer demands, and in our view not indicative of a broad base recovery in spending in this segment. 
Looking at the bookings by product line, while ALD was again our largest product line, we also experienced healthy demand in for instance LPCVD and Epi business in the quarter. In terms of product lines ALD continues to be a solid driver for our company. 
The long-term outlook remains strong. The current most advanced nodes 10-nanometer in logic and 5-nanometer in foundry have been a major inflection in terms of ALD needs, driven by further miniaturization, new materials, and by new more complex device architecture, that are on the industry's roadmap, the need for additional ALD applications at future nodes will only further increase. This will support continuing healthy growth in these segments of the ALD market over the longer-term. 
Our focus in the memory segments of the ALD market remains the expansion of our swift available market, or so called SAM. We continue to invest in broadening our portfolio of ALD applications for future DRAM and 3D NAND device technology. In 3D NAND for instance as the industry moves to higher stacks of the 96 layers, 128 layers and beyond, the increasing device complexity and high aspect ratio structures will stimulate the needs for a higher number of single wafer ALD applications . We are targeting to increase our SAM and our share of the memory market step-by-step, as customers transition to next generation devices over the next years."

-CEO Charles del Prado

ASM International NV's (ASMIY) CEO Charles del Prado on Q2 2019 Results - Earnings Call Transcript by Seeking Alpha | LINK

Investor presentation Q2 2019 | LINK

Analyts reports:

ASM International: Strong Headwinds We Didn't Hear In Conference Call
Seeking Alpha: ASM International NV (OTCQX:ASMIY) reported 2Q earnings on July 23, 2019. According to financial disclosures, net sales for the second ...