Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn

In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.

In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.

Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.

NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025

While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.

Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.

Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.

Advanced Logic and Foundry Nodes: Key Growth Segments for Lam

Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.

Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.

Advanced Packaging Driven by AI Fuels Revenue Growth

The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.

Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.

Supporting Installed Base and Productivity in Memory Markets

Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.

As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.

Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance

Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.

Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025

In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.

Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.

Strategic Positioning in 2025 and Beyond

In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.

3D Ferroelectric NAND for Ultra-High Efficiency Analog Computing-in-Memory by SK hynix

3D FeNAND with Ultra-High Computing-in-Memory Efficiency: AI models containing up to trillions of parameters require substantial memory resources to handle the vast amounts of data. Energy-efficient analog computing-in-memory (CIM) devices such as 3D vertical NAND architectures are emerging as potential solutions because they offer high areal density and are non-volatile. SK hynix researchers will detail how they achieved analog computation in ultra-high-density 3D vertical ferroelectric NAND (FeNAND) devices for the first time. They used gate stack engineering techniques to improve the analog switching properties of 3D FeNAND cells, and achieved an unprecedented ≥256-conductance-weight levels/cell. The 3D FeNAND arrays improved analog CIM density by 4,000x versus 2D arrays, and demonstrated stable multiply-accumulate (MAC) operations with high accuracy (87.8%) and 1,000x higher computing efficiency (TOPS/mm²) versus 2D arrays. This work provides an efficient method to implement the processing of hyperscale AI models in analog CIM chips for edge computing applications, where speed and low power operation are the critical requirements, not extreme accuracy.

 

Above:

(1)   is a comparison of 2D and 3D arrays for analog-CIM applications.

(2)   is a TEM analysis  of the 3D FeNAND, showing (a) a top-down view of the device; (b) a cross-sectional view at low magnification; (c) a cross-sectional view at high magnification; and (d) a schematic illustration of the FeFET cells in the 3D FeNAND array.

Source: 

IEDM 2024 Paper #38.1, “Analog Computation in Ultra-High Density 3D FeNAND for TB-Level Hyperscale AI Models,” J.-G. Lee and W.-T. Koo et all, SK hynix https://www.ieee-iedm.org/press-kit

Samsung Sets New Industry Standard with 290-Layer V9 NAND employing mutli stack etch - Plans for 430-Layer Chips

 Samsung Electronics has initiated mass production of its 9th-generation 1Tb TLC vertical NAND (V-NAND), marking a significant advancement in memory technology. This new generation features the smallest cell size yet, improving bit density by approximately 50% over the previous generation. Innovations like cell interference avoidance and life extension techniques have been introduced to enhance reliability and product quality. By eliminating dummy channel holes, Samsung has also effectively reduced the memory cells' planar area, further emphasizing their commitment to leading the high-density, high-performance solid-state drive (SSD) market, particularly for AI applications.

Competitive situation in 3D NAND Flash technology (Golem.de)

One standout feature of the 9th-generation V-NAND is Samsung's advanced "channel hole etching" technology. This process involves stacking mold layers and simultaneously drilling through them, allowing for the creation of electron pathways through the industry's highest cell layer count in a double-stack structure. As the number of layers increases, so does the complexity of the etching process, necessitating more sophisticated techniques to efficiently pierce through these higher numbers. This technology not only showcases Samsung's process capabilities but also maximizes fabrication productivity, cementing its position as a leader in the SSD market.

According to Golem, Samsung's latest QLC-V9 memory chip outpaces its competitors in the NAND flash market with a groundbreaking 280-layer configuration that enhances SSD capacity, cost-efficiency, and speed. With a storage density of 28.5 GBit/mm², Samsung surpasses major rivals like YMTC and Micron, who report densities of 20.63 and 19.5 GBit/mm² respectively, and even outperforms Intel's upcoming 192-layer PLC-NAND. This technical superiority not only sets a new benchmark for memory chip performance but also enables Samsung to potentially introduce the first 8 TB single-sided M.2 SSDs, a significant advancement over current double-sided designs. The increase in interface speed to 3.2 GBit/s from the previous 2.4 GBit/s promises enhanced read speeds close to those of high-end SSDs, although improvements in write speed are yet to be detailed.

Market share, Q4 2023 (TrendForce)

Samsung Electronics is set to escalate its lead in the NAND flash memory market by starting mass production of its 290-layer ninth-generation (V9) vertical NAND chips, which promise enhanced performance for enterprise servers and AI and cloud devices. Building on its dominance since 2002, Samsung is also planning to introduce even more advanced 430-layer NAND chips next year to meet the growing demand for high-performance and large storage solutions in the AI era. This move is part of a broader competitive landscape where major chipmakers like SK Hynix and YMTC are also pushing forward with high-density NAND products, with SK Hynix planning to start producing 321-layer NAND chips early next year and YMTC set to unveil 300-layer chips later this year. Samsung's aggressive investment in NAND technology aims to develop chips with over 1,000 layers by 2030, highlighting the intensifying race among global chipmakers to innovate in chip stacking technology to cut costs and improve performance.

Sources: 

Samsung Electronics Begins Industry's First Mass Production of 9th-Gen V-NAND | Samsung Semiconductor Global

Rekord bei Speicherdichte: Samsungs QLC-V9-Speicherchip schlägt alle Konkurrenten - Golem.de

Samsung to produce 290-layer V9 NAND to win chip stacking war - KED Global

Hanwha to supply ALD Equipment for Molybdenum Deposition for Memory Applications

According to Korean media, Hanwha Precision Machinery is developing a new type of thermal atomic layer deposition (ALD) equipment for depositing molybdenum, which is emerging as a superior material for metal gates in next-generation semiconductors due to its lower resistivity and lack of fluoride residue. The new technology, still in the prototype stage and expected to take three years to commercialize, uses molybdenum dichloride dioxide (MoO2Cl2) as a precursor. This initiative marks Hanwha's expansion into the semiconductor fabrication equipment market, collaborating with industry giants like SK Hynix on future projects, including the development of hybrid bonding equipment for high bandwidth memory production.

At two recent conferences, EFDS ALD For Industry and CMC 2024 this week in Phoenix, Air Liquide presented HVM ready solution for MoO2Cl2 sub fab delivery. They also confirmed that it is already in HVM. Other sources claim that Mo is also in HVM for DRAM. However, no reverse engineering is publicly available as of to day.

Air Liquide presenting HVM ready sub fab solution for MoO2Cl2 precursor delivery at EFDS ALD for Industry in Dresden, Germany.

Hanwha developing thermal ALD equipment for deposition of molybdenum - THE ELEC, Korea Electronics Industry Media (thelec.net)

Surge in HBM Demand Marks Memory Market Recovery and Anticipated Growth in 2024 for Samsung

The global memory market, after experiencing a period of stagnation, has witnessed a resurgence in the third quarter, driven primarily by increased demand for high-density DRAM and NAND products in the PC and mobile sectors.

Samsung Electronics' financial results for 3Q23 highlighted a 12% QoQ revenue increase to 67.40 trillion Korean won, although there was a 12% YoY decrease. Notably, the company reported its highest quarterly profit for the year. Despite potential economic uncertainties in 2024, Samsung is optimistic about the recovery of the memory market and the rebound in smartphone demand. 

The memory sector saw a recovery compared to the previous quarter, especially in PC and mobile due to the rise in adoption of high-density DRAM and NAND products. The completion of customer inventory adjustments also played a role. Server demand was subdued for traditional servers due to macroeconomic uncertainties. However, strong demand persisted for AI-oriented high-density products. Samsung emphasized its focus on expanding sales of advanced node products like HBM DDR5, LPDDR5, and UFS 4.0. They also intend to manage high inventory products through production adjustments. The company expects the recovery trend in the memory market to accelerate further in the fourth quarter. Additionally, there has been a notable surge in HBM demand and the company is actively advancing its HBM businesses and plans to augment its HBM supply capacity by 2.5 times next year.

Trendforce on X (LINK)

The foundry division secured a record number of new orders, particularly in the HPC domain, despite a slow recovery in the mobile market. The new Taylor factory in Texas is set to begin production using the second-gen 3nm GAA process. The advanced packaging business has also been flourishing with orders from both domestic and international HPC clients.

Profits in the mobile panel business surged due to new flagship models from major clients. In contrast, the large panel business faced tepid demand. Samsung aims to cater to the growing mobile panel demand and increase profitability in the large panel sector by introducing new products and enhancing yield rates.

With the global economy expected to bounce back in 2024, the smartphone market's demand is anticipated to surge. High-end market growth is likely to continue, driven by the global recovery of the smartphone market.

Looking ahead to 2024, Samsung anticipates increased PC and mobile demand due to product replacement cycles initiated during the pandemic's early phase. High-density trends in both DRAM and NAND are expected to persist, propelled by on-device AI advancements. The company plans to focus on advanced node products, including 1B nanometer DDR5, LPDR5X, PCI Gen 5, and UFS 4.0, to bolster product competitiveness and profitability. Emphasizing the growing demand for generative AI, Samsung aims to strengthen its market position with high-density, low-power, and high-performance products for on-device AI, which has recently gained significant attention.

Sources;

TrendForce on X: "Samsung Electronics has released its financial results for 3Q23, reporting a quarterly revenue of 67.40 trillion Korean won—a 12% QoQ increase but 12% YoY decrease. The company achieved its highest quarterly profit of the year and anticipates that, despite ongoing global economic… https://t.co/RDKVjimgzN" / X (twitter.com)

Samsung Electronics Co Ltd (SSNLF) Q3 2023 Earnings Conference Call Transcript | Seeking Alpha

NEO Semiconductor Unveils Revolutionary 3D NAND and DRAM Innovations at Flash Memory Summit 2023

NEO Semiconductor, known for its expertise in 3D NAND flash and DRAM technologies, presented groundbreaking innovations at Flash Memory Summit 2023 in August. The full presentation can be seen on Youtube (below). CEO Andy Hsu's keynote introduced their latest creation, 3D X-DRAM™, designed to overcome DRAM's capacity limitations and replace 2D DRAM. This technology utilizes the existing 3D NAND flash process with minor modifications, streamlining development and reducing costs. Hsu also unveiled a new AI application, "Local Computing," promising a substantial enhancement in AI chip performance.

X-DRAM™ significantly reduces data latency and provides ultra-high data throughput to unleash the full potential of High-Bandwidth Memory (HBM). HBM uses many Through Silicon Via (TSV) to increase I/O bandwidth. However, the HBM data latency remains almost the same when using conventional DRAM because bit line lengths remain the same.

Furthermore, NEO Semiconductor showcased various novel memory structures derived from 3D X-DRAM™, tailored for applications like 3D NOR flash memory, 3D Ferroelectric RAM (FFRAM), 3D Resistive RAM (RRAM), 3D Magnetoresistive RAM (MRAM), and 3D Phase Change Memory (PCM). These innovations enable the transition from 2D to 3D memory cells.

Hsu underscored the significance of these technologies for the semiconductor industry, cloud providers, and enterprises, highlighting that 3D X-DRAM™ offers a high-speed, high-density, cost-effective, and high-yield solution.

The presentation addressed the challenges faced by DRAM and NAND flash memory in the context of AI applications and introduced two innovative solutions – 3D X-DRAM™ and 3D X-NAND™.

Being part of the prestigious Flash Memory Summit, NEO Semiconductor showcased its technologies at booth number 215, and interested parties had the opportunity to schedule meetings with the company at the event.

In summary, NEO Semiconductor unveiled groundbreaking advancements in 3D NAND flash and DRAM technologies at Flash Memory Summit 2023, offering solutions to critical challenges in memory performance and capacity.

Source: NEO Semiconductor to Present Its Ground-Breaking 3D NAND and 3D DRAM Architectures in Keynote Address at Flash Memory Summit 2023 - Neo Semiconductor | X-Nand

Tokyo Electron Introduces Breakthrough Memory Channel Hole Etch Technology for 3D NAND Flash, Reducing Global Warming Potential by 84%

Tokyo Electron's Innovative Etch Process Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers, Showcased at Symposium on VLSI Technology and Circuits

Tokyo Electron (TEL) has achieved a significant technological milestone by developing a cutting-edge etch technology capable of creating memory channel holes in advanced 3D NAND devices with over 400 layers. This breakthrough process, pioneered by the development team at Tokyo Electron Miyagi, leverages cryogenic temperatures to achieve exceptionally high etch rates, marking the first time dielectric etch application has been utilized in this temperature range.

The groundbreaking technology not only enables the etching of memory channel holes up to 10 µm deep with a high aspect ratio in just 33 minutes but also boasts an impressive 84% reduction in global warming potential compared to previous methods. The etched structure exhibits well-defined geometry, as demonstrated by cross-section SEM and FIB cut images.

Cross section SEM image of memory channel hole pattern after etching, and FIB cut image at the hole bottom.

TEL's research team behind this groundbreaking technology will present their findings at the prestigious 2023 Symposium on VLSI Technology and Circuits, a renowned international conference on semiconductor research. Their contribution showcases the potential for even larger capacity 3D NAND flash memory.

The presentation, titled "Beyond 10 µm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers," will be delivered by Y. Kihara, M. Tomura, W. Sakamoto, M. Honda, and M. Kojima from Tokyo Electron Miyagi Ltd. The session, scheduled for Tuesday, June 13, from 2 p.m. to 3:40 p.m., will take place in the NAND Flash section of the Technology Session 3 [Shunju II].

For detailed event information about the 2023 Symposium on VLSI Technology and Circuits, please click here. Stay tuned for TEL's technology presentation, which combines semiconductor advancements and environmental protection efforts. 2023 Symposium on VLSI Technology and Circuits

Source: Tokyo Electron Develops Memory Channel Hole Etch Technology That Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers and an 84% Reduction of Global Warming Potential | News Room | Tokyo Electron Ltd. (tel.com)

ALD to take over more and more as CVD and spin-on processes no longer are viable for 3D NAND

EE Times reports [LINK] about the recently announced Striker FE from Lam Research, an enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM. It employs advanced dielectric gapfill technology the company has dubbed “ICEFill” for filling 3D NAND and DRAM structures — as well as logic devices — in emerging nodes. 

Lam Research’s recently announced Striker FE enhanced atomic layer deposition (ALD) platform addresses semiconductor manufacturing challenges for 3D NAND as well as DRAM

Lam Research Striker FE - Key applications (LINK):

• Gapfill dielectrics
• Conformal liners
• Patterning spacers and masks
• Hermetic encapsulation
• Etch stop layers
• Optical films

The need for gapfill methods isn’t new, said Aaron Fellis, vice president and general manager of Dielectric ALD products, but the traditional ones no longer meet today’s needs, especially as 3D NAND is stacked higher. “They’re so tall and they have a number of different features that get etched through them to enable the integration of different steps,” he said. “Ultimately, they need to get filled back up with a dielectric material, most commonly silicon oxide.”

Legacy techniques, such as chemical vapor deposition, diffusion/furnace, and spin-on processes that are normally used as gapfill for semiconductor manufacturing are no longer viable for 3D NAND, Fellis said, due to trade-offs between quality, shrinkage, and gapfill voids. “They tend to shrink and distort the actual structure that the customer is building and designing.”

According to Risto Puhakka, president of VLSIresearch, Lam Research is a dominant player for ALD technology, and the demands of its technology reflect those placed on memory. It’s all about increasing density for applications, such as artificial intelligence, that require more bits while keeping costs the same, and that includes gapfill capabilities as the memories such as 3D NAND are stacked higher, he said. “The stacking becomes more and more challenging from the manufacturing perspective, but the chip makers themselves get it a little bit little anxious about how much they have to spend.” Sticking with a known material such as silicon oxide adds some predictability because it’s well understood

But just as 3D NAND stacking will eventually hit limits, so will the gapfill techniques and ALD technology, added Puhakka. “It has its own roadmap and limitations.”

TechInsights Webinar: ALD/ALE Process in Commercially Available Memory Devices

2018 saw memory product manufacturers Samsung, Hynix, Toshiba and Micron introducing 64- or 72- stacked layer 3D-NAND devices, and move into 1x generation DRAM devices.

This presentation will examine some of the different structures we have seen through the evolution of these technologies, in particular the latest 3D-NAND and DRAM parts. We will also look at several historical applications of ALD/ALE technology that have been observed through reverse engineering. We will highlight the importance of ALD/ALE process in advanced logic devices. In many cases, the technology could not have advanced without the implementation of ALD technology.

Information and registration: LINK

Process Power: The New Lithography - Advanced Energy

Here is a very insightful article by PETER GILLESPIE, VP & GM, Semiconductor Products, Advanced Energy Industries on the progress of Plasma RF Generators and Matching Networks. The article looks at applications in 3DNAND High Aspect Ratio Contacts (HARC) and Logic FinFET transitor fabrication using reactive ion etching and plasma CVD using the latest plasma technology. This is a an articel in a series of three in SEMICONDUCTOR DIGEST entitled “Process Power Steps Out from the Shadows,” looking at the leading edge technology node process challenges to highlight key drivers that are fundamentally transforming the role and importance of process power. 

Process Power: The New Lithography (SEMICONDUCTOR DIGEST, LINK) 

 

"Evolution of RF power supplies (plasma generators) and RF matching networks. Today’s RF power delivery systems are highly sophisticated with frequency tuning, complex pulsing regimes, and agile micro-second response." (Below)

 

 

TechInsights’ Memory Process: 3D NAND Word Line Pad webinar

TechInsights’ ‘Memory Process: 3D NAND Word Line Pad‘ #webinar compares 9x-layer 3D NAND devices from major manufacturers and discusses the process sequence with emphasis on the word line pad (WLP). Watch on demand here LINK 

 

Screendump from Webinar

Choppy Waters for Shipping $50B of Semiconductor Materials in 2020

Risky Sailing on the Global Supply-Chain Seas

San Diego, CA, Apr 17, 2020:TECHCET announces that:

 

• 2020 global material revenues in semiconductor manufacturing forecasted to decline by 3.0% year-over-year (YoY) despite growth in 1Q2020,
• Impact of COVID-19 pandemic on the global economy is creating choppy waters for shipping and supplying critical materials, as highlighted in recent Critical Materials Council (CMC) monthly meetings, and
• With a return of global economic growth by 2021, compound annual growth rate (CAGR) through 2025 is forecast at 3.5% as shown in the Figure (below).
 

 

“From our market research, materials suppliers are increasing production and sales to ensure safety-stock throughout the supply-chain in case there are further disruptions due to COVID-19 cases,” remarked Lita Shon-Roy, TECHCET President and CEO. “Even without further disruptions, we can already see leading economic indicators such as unemployment levels, metal prices and container shipping indices point toward a significant decline in global GDP.” This is supported by the International Monetary Fund’s (IMF’s) current outlook on 2020.

Currently, almost all chip fabs appear to be running at normal levels, with a few exceptions. During this difficult period, YMTC in Wuhan, China reportedly has maintained R&D and grown production of 3D-NAND chips. However, chip fabs in Malaysia report that the government required companies to request permission to continue operating at 50% staffing levels. One company in France had to temporarily reduce production due to their labor union insisting on temporary workforce reductions.

Significant value-added engineered materials including specialty gases, deposition precursors, wet chemicals, chemical-mechanical planarization (CMP) slurries & pads, silicon wafers, PVD/sputtering targets, and photoresists & ancillary materials for lithography are reporting healthy orders and in some cases will see better than expected revenues for 1Q2020 and April 2020. However, more than 60% of all materials are expected to be negatively impacted before year-end.

Overall demand for commodity materials, such as silane and phosphoric acid, is expected to decline YoY in 2020 by an average of 3% due to softening of the global economy. Average selling prices (ASP) for electronic-grade commodities may drop due to cost reductions in feed-stocks; for example, the global helium (He) gas market which had been forecasted to be in shortage with high ASPs throughout 2020 has already improved due to COVID-19 slowing down helium demand.

DRAM, 3D-NAND, and MPU chips for server / cloud-computing applications are now in high demand for virtual meetings and remote work. It is yet unclear how much of an increase in materials shipments will be needed to support this segment, however from TECHCET’s modeling of prior cycles it will likely be >7%. Despite such an increase in the materials used to make leading-edge ICs to build out data centers, shipments in support of legacy node IC fabrication are expected to decline this year.

Consequently, cloud-computing growth may not compensate for overall reduced semiconductor materials demands caused by economic downturns this year. By 2021 the global economy and all chip fabs should return to healthier growth, with materials markets for all IC devices expected to increase at a CAGR of +3.5% through 2025.

Critical Materials Reports™ and Market Briefings: TECHCET Shop
CMC Events: Click here to view all Events

Lam Research Adds Global Wafer Stress Management Solutions to Portfolio to 3D NAND Scaling

FREMONT, Calif., Aug. 07, 2019 (GLOBE NEWSWIRE) — Lam Research Corp. (Nasdaq: LRCX) today announced new solutions to help customers increase chip memory density, which is needed for applications such as artificial intelligence and machine learning. With the introduction of VECTOR® DT for backside deposition and EOS® GS wet etch for film removal on backside and bevel, Lam continues the expansion of its stress management product portfolio.

While high aspect ratio deposition and etching are key enablers for 3D NAND scaling, the combination of increasing the number of layers while controlling wafer bow due to cumulative stress in the film stack has become a major challenge. Such stress-induced wafer distortion has a significant impact on wafer yield due to degraded lithography depth-of-focus, overlay performance, and structural distortion. To improve overall yield, wafer-, die-, and feature-level stresses need to be carefully managed at various steps throughout the entire manufacturing process flow, at times potentially resulting in the preclusion of otherwise performance-enhancing process steps due to their stress characteristics.

Designed to provide a cost-effective solution for controlling wafer bow in 3D NAND manufacturing, the VECTOR DT system is the newest addition to Lam’s plasma-enhanced chemical vapor deposition (PECVD) product family. VECTOR DT provides a single-step solution for wafer shape management by depositing a tunable counter-stress film on the back of the wafer without contacting the front side, thereby enabling improved lithography results, reduced bow-induced failures, and integration of high performance but highly stressed films. With strong customer adoption since its debut, the VECTOR DT installed base continues to grow as customers are transitioning to more than 96 layers.

In addition to depositing a counter stress film, Lam provides the flexibility to remove backside films, allowing customers to adjust wafer stress during the 3D NAND manufacturing flow. Lam’s EOS GS wet etch product complements the VECTOR DT by simultaneously removing backside and bevel films with industry-leading wet etch uniformity, while fully protecting the wafer front side. As part of a comprehensive wafer bow management solution, Lam’s EOS GS has also been adopted by memory manufacturers worldwide.

“As our customers continue to dramatically increase the number of memory cell layers, the cumulative stress and wafer bow can exceed the limits of a lithography tool. Minimizing stress-induced distortion is critical for achieving the desired yield and enabling the cost-per-bit roadmap,” said Sesha Varadarajan, senior vice president and general manager of the deposition product group at Lam Research. “With the addition of the VECTOR DT and EOS GS systems, we are expanding our stress management solutions portfolio for managing global stress in support of our customers’ vertical scaling roadmap.”

Source: Lam Research LINK

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By Abhishekkumar Thakur

Applied Materials to buy Japan's Kokusai to boost memory chip business and ALD

Here are more details and analyst responses on the Applied Materials Kokusai purchase and my own thoughts at the end:

(Reuters, LINK) - U.S. chip gear maker Applied Materials Inc (AMAT.O) on Monday agreed to buy Japanese peer Kokusai Electric for $2.2 billion from KKR & Co Inc (KKR.N), as it bets on rising demand for memory chips used in data centers, 5G phones, and AI-powered devices.  

In summary:

• Kokusai is a small acquisition for Applied materials as compared to the previously failed mega-merger with Tokyo Electron, meaning that the road to approval should be easy. However, China’s willingness from a political standpoint is always a risk, Evercore analysts said. 
• Apart from China, the acquisition will need approvals from Israel, Ireland, Japan, Korea and Taiwan, Applied Materials Chief Financial Officer Dan Durn said on a call with analysts.
• Kokusai, which counts Samsung, SK Hynix, Toshiba and Micron among its top customers, reported revenue of $1.24 billion as of March 2018. 
• Kokusai’s batch wafer processing tools are less technology intensive than Applied Materials’ single wafer tools, the recent focus on ultra-thin films has driven renewed interest in this group, DA Davidson analysts said.

So this whole purchase is really about Applied Materials getting a state of the art ALD technology for the memory business (DRAM and 3DNAND). The last readout is a bit crazy, the analyst refers to ALD as an "Ultra Thin Films". Anybody who has followed the ALD business the previous 15-20 years know that Applied Materials has repeatedly failed to take a big market share in ALD and that a Japanese Large Batch ALD reactor is one of the most advanced and reliable ALD tools out there - simply because nobody would like to trash a full load of +100 product wafers. The top three domination has been by:

• ASM International
• Tokyo Electron
• Kokusai

The top 3 has been followed by Lam Research, Jusung Engineering, Wonik IPS and Applied Materials was always somewhere in this bunch. Even the inrodcution of the new Spatial ALD Olympia platform didn´t change things. It seems that Tokyo Electron took a large part of the spatial ALD market with their NT333 tool and ASM was able to defend their single wafer approach by making the XP platform super productive by adding more chamber slots (up to 16 for the latest ASM XP8 QCM).  

When it comes to IP in Spatial ALD, Tokyo Electron is No.1 followed by Applied Materials (see below).

IP Applications for spatial ALD

Magically, Kokusai settled the IP issues with ASM just before the Applied announcement (LINK). Historically, Kokusai has been masters in avoiding to call ALD ALD because of the IP situation. However, now there is a different situation and Kokusai also have single wafer ALD out there, and Applied is dominating the BEOL films deposition business so we can assume that Applied will enter top three and have a go at No 1. Exciting!

TechInsights’ Logic, NAND, DRAM and Emerging Memory Process Roadmaps are here

TechInsights’ Logic Process Roadmap offers an assessment and the anticipatory timing of new innovations from key players within the Logic space including: TSMC, Global Foundries, Intel & others. Download the roadmap here http://bit.ly/2FipHHA 

TechInsights’ technology roadmaps show you the innovations we are monitoring

For over 30 years, TechInsights has been reverse engineering semiconductors and advanced technology products, developing the world’s largest library of technical analysis. We have built this library through two approaches: by conducting analysis in response to client requests, and by proactively analyzing disruptive or innovative technologies as they are released.

We constantly monitor the consumer electronics market to determine which manufacturers are planning to release new solutions, and when. We maintain and regularly update technology roadmaps in several different areas: Logic, NAND Flash Memory, DRAM, Emerging Memory, and Internet of Things Connectivity Systems on Chips, and more.

Updates to the roadmaps shown below are released throughout the year; check this page for updates. 

What Will Come After V‐NAND—Vertical Resistive Switching Memory?

Here is a hot paper from Hwang in Advanced Materials on what may come after V-NAND/3DNAND Flash meory architecture. In the case of Vertical ReRAM we can assume that there are numerous opportunities for funky ALD materials and processes!

 

What Will Come After V‐NAND—Vertical Resistive Switching Memory?
Kyung Jean Yoon, Yumin Kim, Cheol Seong Hwang
Version of Record online:28 February 2019
https://doi.org/10.1002/aelm.201800914

 
Pathways to overcome the scaling limitation of vertical NAND flash memory (V‐NAND), the present market leading nonvolatile memory, providing new materials and array structure suggestions, are provided. Specifically, the favorable aspects of a vertical resistive random access memory (V‐ReRAM) structure, such as areal density and decoding schemes, are highlighted in comparison with the commercialized nonvolatile memories: 3D‐Crosspoint and V‐NAND.

Western Digital and Toshiba have developed a 128-layer 3D NAND die with TLC (3bits/cell) cell formatting and 512Gbit capacity.Acoording to etimates and modelling WD-Toshiba has the industry’s highest NAND density and models the suppliers at an 85 per cent wafer yield - thanks Terry Francis for sharing.

ASM International report recovery in the single-wafer ALD market due to strong 3D-NAND fab invest

Almere, The Netherlands, March 22, 2018 ASM International N.V. (Euronext Amsterdam: ASM) today publishes its 2017 Annual Report.

ASMI's Annual Report is also available on the company's website www.asm.com. The Annual Report includes the Corporate Responsibility Report and the Remuneration Report in order to increase the relevancy and quality of reporting to all stakeholders.

ASMI will hold its Annual General Meeting of Shareholders (AGM) on May 28, 2018. The AGM agenda with all related documents will be available in due time.

MESSAGE FROM THE CEO (asm.com LINK)

In 2017 we achieved significant progress against our strategic targets. Our sales benefited from a clear recovery in the single-wafer Atomic Layer Deposition (ALD) market, in particular driven by strong increases in the 3D-NAND segment. During the year we also successfully expanded our position in the epitaxy market with an important tool win from a leading foundry customer. In total, our revenue increased by 23% to a new record level. 

Please check out the financial data at a glance here (LINK).

Challenges in 3D-NAND high volume manufacturing

Planar NAND was scaled and at the end limited by the cost of lithography, wheras 3D NAND scaling is enabled by advanced deposition and etch processes defining complex high aspect ratio 3D structures. Here is an excellent article by Lam Research in Solid State Technology on the challenges in 3D-NAND fabrication.

Solis State Technology : LINK

Screen capture from Solid State Technology online magazine (LINK)

ASM International technical luncheon seminar in San Francisco at IEDM 2017, December 7

ASM International N.V. (Euronext Amsterdam: ASM) today announces that it will host a technical luncheon seminar in San Francisco, CA, US, on Wednesday, December 7, 2016, the third day of the IEDM Conference.

 

At this technology seminar ASM will highlight the challenges and potential solutions for achieving next generation 3D devices.

The agenda is as follows:

11:30 am Food and drinks

12:00 - 12:05 pm Ivo Raaijmakers (ASM) - Welcome and introduction

12:05 - 12:30 pm Invited speaker: Raghuveer Makala (SanDisk/WDC) - "Thin film deposition
challenges for 3D NAND"

12:30 - 12:55 pm Invited speaker: Jorge Kittl (Samsung) - "Perspectives on logic scaling and
implications for process requirements"

Following the presentations, there is an opportunity for open discussion and networking until 1:15 pm.

The ASM technology seminar will take place in the Golden Gate room (25th floor) at the Nikko Hotel (across from the Hilton San Francisco), San Francisco, CA 94102. The room will open at 11:30 am for invited attendees. Interested parties should contact Rosanne de Vries, +31 88 100 8569, rosanne.de.vries@asm.com.