Tuesday, September 17, 2024
Technological Innovations in Semiconductor Manufacturing: Insights from Tokyo Electron's 2024 Integrated Report
Tuesday, February 27, 2024
Applied Materials Unveils Cutting-Edge Patterning Technologies for Next-Gen Semiconductor Device Manufacturing
Applied Materials is leading the charge into the angstrom era of chipmaking, unveiling a suite of innovative solutions at the SPIE Advanced Lithography + Patterning conference. The company's focus is on overcoming the challenges posed by extreme ultraviolet (EUV) and high-NA EUV lithography, crucial for the production of chips at 2nm process nodes and below. Their approach integrates new materials engineering, metrology techniques, and pattern-shaping technology to enhance chip performance and yield.
To help overcome patterning challenges for leading-edge chips, Applied Materials offers a portfolio of technologies designed to complement the latest advances in lithography. The company’s newest innovations include the Producer® XP Pioneer® CVD patterning film, the Sym3® Y Magnum™ etch system, the Centura® Sculpta® pattern-shaping system and Aselta contour technology for design-based metrology.
Central to Applied Materials' advancements is the Sculpta® pattern-shaping technology, first introduced at the previous year's conference. Sculpta has seen growing adoption among top logic chipmakers for its ability to refine EUV patterning, notably reducing double patterning steps and mitigating defects such as bridge defects. This technology not only lowers patterning costs but also improves chip yields, showcasing its increasing importance in the semiconductor manufacturing landscape.
In response to the issue of EUV line edge roughness, Applied Materials has launched the Sym3® Y Magnum™ etch system. This innovative system employs a combination of deposition and etch processes within a single chamber to smooth out rough edges before etching, thereby enhancing yield and chip performance.
Additionally, the company introduced the Producer® XP Pioneer® CVD patterning film, designed for high-fidelity pattern transfer with enhanced resistance to etch chemistries. This film is especially significant for advanced process nodes, offering improved sidewall feature uniformity and co-optimization with both Sculpta and the Sym3 Y Magnum system for superior patterning capabilities.
To address the critical issue of feature alignment across chip layers, Applied Materials has acquired Aselta Nanographics, integrating its design-based metrology with Applied's leading eBeam systems. This integration enables a comprehensive metrology solution that significantly enhances feature placement accuracy, crucial for optimizing chip performance and yield.
Applied Materials' expansion of its patterning solutions portfolio underscores its commitment to advancing semiconductor technology. By addressing key challenges in EUV lithography and introducing groundbreaking technologies, the company is setting new standards for the industry, driving forward the capabilities of angstrom era chipmaking.
Thursday, February 15, 2024
AMEC's Revenue Grows with Advanced Etch Technology Fueling China's Semiconductor Surge
Monday, June 12, 2023
Tokyo Electron Introduces Breakthrough Memory Channel Hole Etch Technology for 3D NAND Flash, Reducing Global Warming Potential by 84%
Tokyo Electron's Innovative Etch Process Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers, Showcased at Symposium on VLSI Technology and Circuits
Tokyo Electron (TEL) has achieved a significant technological milestone by developing a cutting-edge etch technology capable of creating memory channel holes in advanced 3D NAND devices with over 400 layers. This breakthrough process, pioneered by the development team at Tokyo Electron Miyagi, leverages cryogenic temperatures to achieve exceptionally high etch rates, marking the first time dielectric etch application has been utilized in this temperature range.
The groundbreaking technology not only enables the etching of memory channel holes up to 10 µm deep with a high aspect ratio in just 33 minutes but also boasts an impressive 84% reduction in global warming potential compared to previous methods. The etched structure exhibits well-defined geometry, as demonstrated by cross-section SEM and FIB cut images.
TEL's research team behind this groundbreaking technology will present their findings at the prestigious 2023 Symposium on VLSI Technology and Circuits, a renowned international conference on semiconductor research. Their contribution showcases the potential for even larger capacity 3D NAND flash memory.
The presentation, titled "Beyond 10 µm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers," will be delivered by Y. Kihara, M. Tomura, W. Sakamoto, M. Honda, and M. Kojima from Tokyo Electron Miyagi Ltd. The session, scheduled for Tuesday, June 13, from 2 p.m. to 3:40 p.m., will take place in the NAND Flash section of the Technology Session 3 [Shunju II].
For detailed event information about the 2023 Symposium on VLSI Technology and Circuits, please click here. Stay tuned for TEL's technology presentation, which combines semiconductor advancements and environmental protection efforts. 2023 Symposium on VLSI Technology and Circuits
Wednesday, March 4, 2020
Lam’s new Sense.i Etch platform delivers industry-leading output and innovative sensor technology
- Lam Research (NASDAQ:LRCX) introduces the Sense.i tool, which etches finer 3D details on silicon wafers for chips.
- The Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs
- 3D features can help Lam customers like Samsung and SK Hynix put more memory capacity into small areas such as smartphones.
With core technology evolved from Lam’s industry-leading Kiyo® and Flex® process modules, the Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs. As dimensions shrink and aspect ratios increase, the Sense.i platform is designed to support future technology inflections.
Powered by Lam’s Equipment Intelligence® technology, the self-aware Sense.i platform enables semiconductor manufacturers to capture and analyze data, identify patterns and trends, and specify actions for improvement. Sense.i also features autonomous calibration and maintenance capabilities that reduce downtime and labor costs, and delivers machine learning algorithms that allow the tool to self-adapt to minimize process variations and maximize wafer output.
The Sense.i platform has a revolutionary space-saving architecture that will help customers meet their future wafer output targets by producing more than a 50% improvement in etch output density. As semiconductor manufacturers develop smarter, faster, and denser chips, processes are rapidly growing in complexity and number of steps. This requires a greater number of process chambers in a fab and reduces total output for a given floor space. The Sense.i platform’s smaller footprint benefits either a new fab build or a fab undergoing a node-to-node technology conversion.
“Lam is introducing the most innovative etch product that has been developed in the last 20 years,” said Vahid Vahedi, senior vice president and general manager of the Etch product group at Lam Research (LRCX). “Sense.i extends our technology roadmap to meet our customers’ next-generation requirements while solving the critical cost scaling challenges they’re facing in their business. With more than four million wafers processed on Lam etch systems every month, Lam has an installed-base that provides extraordinary learning to innovate, design, and produce the best tools for semiconductor manufacturing.”
Friday, December 21, 2018
Chinese AMEC 5nm plasma etching tools verified by TSMC
Earlier in 2018 AMEC Introduced the Primo Nanova® System, which is the Company's first ICP etch Product for Chipmakers' most advanced memory and logic (LINK). Besides ICP AMEC has products based on CCP etch and platforms for TSV Etch (LINK).
Advanced Micro-Fabrication Equipment Inc. (AMEC)
AMEC is China's leading provider of advanced process technology to global manufacturers of semiconductors and solid-state lighting (SSL) products. Headquartered in Shanghai, the company is an entrenched supplier of dielectric and TSV Etch tools, helping chipmakers build devices at process nodes as low as 7nm. To date, nearly 800 AMEC process units have been positioned at 40 leading-edge semiconductor fabs across Asia. The company is also well established in Europe with AMEC MEMS tools running in production at major IDMs. In addition, with its MOCVD system, the company helps SSL manufacturers build today's most advanced LED products. To learn more about AMEC, please visit www.amec-inc.com.
Saturday, March 31, 2018
Tokyo Electron reports on patterning technology for advancements in scaling
- Introduction of advanced patterning technology and challenges
- SADP – Scaling by thin film formation on sidewall
- SAQP – Scaling by extending SADP technology
- SAB – Scaling by etch selectivity to multiple materials
Full article: LINK
Tuesday, July 14, 2015
Applied Materials announced a next-generation etch tool at SEMICON West
Tuesday, April 7, 2015
A spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept!
F. Roozeboom, F. van den Bruele, Y. Creyghton, P. Poodt, and W.M.M. Kessels
ECS Journal of Solid State Science and Technology, 4 (6) pp. N5067-N5076 (2015). doi:10.1149/2.0111506jss
- The potential of ALD-assisted nanomanufacturing technologies like Atomic Layer Etching (ALEt) concepts derived from etch-purge-passivation/deposition-purge subroutines in (D)RIE and ALD is now clearly being recognized and promoted.
- The ongoing scaling of Moore's Law will soon require the implemention of these complementary technologies to meet the 10-nm challenges in surface and sidewall passivation of resist and feature patterns that is required to minimize interface, line edge and fin wall roughness.
- For cost reasons and flexibility in local pressure, i.e. (an)isotropy control, in the spatial etch and purge compartments one can envisage a gradual shift to the adoption of ALD-enabled RIE (we abbreviate it as ALDeRIE) in the spatial domain as well.
- Obviously, the spatially divided version is not commercially available yet and not straightforward, but – once realized for dedicated materials and topographies – it will certainly lead to far improved price-performance ratios in Atomic Layer Etching.