Showing posts with label RIE - Reacttive Ion Etching. Show all posts
Showing posts with label RIE - Reacttive Ion Etching. Show all posts

Tuesday, February 27, 2024

Applied Materials Unveils Cutting-Edge Patterning Technologies for Next-Gen Semiconductor Device Manufacturing

Applied Materials is leading the charge into the angstrom era of chipmaking, unveiling a suite of innovative solutions at the SPIE Advanced Lithography + Patterning conference. The company's focus is on overcoming the challenges posed by extreme ultraviolet (EUV) and high-NA EUV lithography, crucial for the production of chips at 2nm process nodes and below. Their approach integrates new materials engineering, metrology techniques, and pattern-shaping technology to enhance chip performance and yield.

To help overcome patterning challenges for leading-edge chips, Applied Materials offers a portfolio of technologies designed to complement the latest advances in lithography. The company’s newest innovations include the Producer® XP Pioneer® CVD patterning film, the Sym3® Y Magnum™ etch system, the Centura® Sculpta® pattern-shaping system and Aselta contour technology for design-based metrology.

Central to Applied Materials' advancements is the Sculpta® pattern-shaping technology, first introduced at the previous year's conference. Sculpta has seen growing adoption among top logic chipmakers for its ability to refine EUV patterning, notably reducing double patterning steps and mitigating defects such as bridge defects. This technology not only lowers patterning costs but also improves chip yields, showcasing its increasing importance in the semiconductor manufacturing landscape.

Over the next few years, chipmakers will be looking to create “angstrom era” chips that will use EUV and High-NA EUV lithography to pattern their smallest features. An entire ecosystem of capabilities will be required to enable this advanced patterning – including software and design tools, innovations in deposition and etch, advanced metrology and inspection systems, and entirely new approaches such as pattern shaping.

In response to the issue of EUV line edge roughness, Applied Materials has launched the Sym3® Y Magnum™ etch system. This innovative system employs a combination of deposition and etch processes within a single chamber to smooth out rough edges before etching, thereby enhancing yield and chip performance.

Additionally, the company introduced the Producer® XP Pioneer® CVD patterning film, designed for high-fidelity pattern transfer with enhanced resistance to etch chemistries. This film is especially significant for advanced process nodes, offering improved sidewall feature uniformity and co-optimization with both Sculpta and the Sym3 Y Magnum system for superior patterning capabilities.

To address the critical issue of feature alignment across chip layers, Applied Materials has acquired Aselta Nanographics, integrating its design-based metrology with Applied's leading eBeam systems. This integration enables a comprehensive metrology solution that significantly enhances feature placement accuracy, crucial for optimizing chip performance and yield.

Applied Materials' expansion of its patterning solutions portfolio underscores its commitment to advancing semiconductor technology. By addressing key challenges in EUV lithography and introducing groundbreaking technologies, the company is setting new standards for the industry, driving forward the capabilities of angstrom era chipmaking.

Source: Applied Materials Expands Patterning Solutions Portfolio for Angstrom Era Chipmaking | Applied Materials

Thursday, February 15, 2024

AMEC's Revenue Grows with Advanced Etch Technology Fueling China's Semiconductor Surge

AMEC, China's etching tools giant, forecasts a 30%+ revenue jump in 2023, driven by local semiconductor demand and replacing US parts with domestic ones.

Advanced Micro-Fabrication Equipment Inc. (AMEC), a leading Chinese provider of semiconductor etching tools, is set to witness a significant revenue surge exceeding 30% in 2023, buoyed by robust demand from China's burgeoning semiconductor manufacturing sector. AMEC's strategic focus on core technological innovations has enabled the deployment of an array of sophisticated chip-making equipment to domestic fabs, catering to the critical process of etching in semiconductor production. AMEC's revenue for 2023 is projected to hit 6.26 billion yuan ($879 million), marking a 32.1% increase from the previous year, underpinned by a substantial 8.36 billion yuan in new orders. This growth trajectory is further evidenced by an impressive net profit forecast ranging between 1.7 billion yuan and 1.85 billion yuan, showcasing year-on-year growth of 45% to 58%. Central to AMEC's success is its adeptness in navigating the challenges posed by tightened US semiconductor sanctions. 

The company has embarked on an ambitious strategy to diminish reliance on foreign components, with a commitment to replacing 80% of US-restricted components with locally sourced parts by the end of last year, aiming for a complete transition by 2024. AMEC's product lineup, particularly its core etching tools like the capacitively coupled plasma (CCP) and inductive coupled plasma (ICP) systems, is pivotal to its revenue stream, anticipated to constitute 75% of its total earnings for the year. These etching tools, essential for the intricate process of sculpting microscopic circuits onto semiconductor wafers, have gained substantial traction among Chinese foundries. This is a testament to AMEC's technological prowess and its role in bolstering China's self-sufficiency in semiconductor manufacturing. 

The company's market share in domestic CCP equipment is expected to soar to 60%, a significant leap from 24% in October 2022. Similarly, AMEC's foothold in the ICP equipment market is projected to reach an impressive 75%, marking a dramatic rise from virtually zero. This growth is particularly notable against the backdrop of declining mainland sales of once-dominant US chip equipment manufacturers like Lam Research. AMEC's technological offerings, characterized by advanced etching capabilities and innovation-driven development, cater primarily to China's semiconductor fabs. These fabs are integral components of the nation's strategic push towards self-reliance in semiconductor production, a sector that has become a focal point of international geopolitical tensions and trade restrictions. As such, AMEC not only stands as a technological leader but also as a key enabler of China's ambitions in the global semiconductor arena.

Monday, June 12, 2023

Tokyo Electron Introduces Breakthrough Memory Channel Hole Etch Technology for 3D NAND Flash, Reducing Global Warming Potential by 84%

Tokyo Electron's Innovative Etch Process Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers, Showcased at Symposium on VLSI Technology and Circuits

Tokyo Electron (TEL) has achieved a significant technological milestone by developing a cutting-edge etch technology capable of creating memory channel holes in advanced 3D NAND devices with over 400 layers. This breakthrough process, pioneered by the development team at Tokyo Electron Miyagi, leverages cryogenic temperatures to achieve exceptionally high etch rates, marking the first time dielectric etch application has been utilized in this temperature range.

The groundbreaking technology not only enables the etching of memory channel holes up to 10 µm deep with a high aspect ratio in just 33 minutes but also boasts an impressive 84% reduction in global warming potential compared to previous methods. The etched structure exhibits well-defined geometry, as demonstrated by cross-section SEM and FIB cut images.

Cross section SEM image of memory channel hole pattern after etching, and FIB cut image at the hole bottom.

TEL's research team behind this groundbreaking technology will present their findings at the prestigious 2023 Symposium on VLSI Technology and Circuits, a renowned international conference on semiconductor research. Their contribution showcases the potential for even larger capacity 3D NAND flash memory.

The presentation, titled "Beyond 10 µm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers," will be delivered by Y. Kihara, M. Tomura, W. Sakamoto, M. Honda, and M. Kojima from Tokyo Electron Miyagi Ltd. The session, scheduled for Tuesday, June 13, from 2 p.m. to 3:40 p.m., will take place in the NAND Flash section of the Technology Session 3 [Shunju II].

For detailed event information about the 2023 Symposium on VLSI Technology and Circuits, please click here. Stay tuned for TEL's technology presentation, which combines semiconductor advancements and environmental protection efforts. 2023 Symposium on VLSI Technology and Circuits

Source: Tokyo Electron Develops Memory Channel Hole Etch Technology That Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers and an 84% Reduction of Global Warming Potential | News Room | Tokyo Electron Ltd. (

Wednesday, March 4, 2020

Lam’s new Sense.i Etch platform delivers industry-leading output and innovative sensor technology

  • Lam Research (NASDAQ:LRCX) introduces the Sense.i tool, which etches finer 3D details on silicon wafers for chips.
  • The Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs
  • 3D features can help Lam customers like Samsung and SK Hynix put more memory capacity into small areas such as smartphones.
FREMONT, Calif., March 03, 2020 (LINK) -- Lam Research Corp. (Nasdaq: LRCX) today announced the launch of a completely transformed plasma etch technology and system solution, designed to provide chipmakers with advanced functionality and extendibility required for future innovation. Lam’s groundbreaking Sense.i™ platform offers unparalleled system intelligence in a compact, high-density architecture to deliver process performance at the highest productivity, supporting logic and memory device roadmaps through the coming decade.

With core technology evolved from Lam’s industry-leading Kiyo® and Flex® process modules, the Sense.i platform enables the critical etch capabilities required to continue advancing uniformity and etch profile control for maximizing yield and lowering wafer costs. As dimensions shrink and aspect ratios increase, the Sense.i platform is designed to support future technology inflections.

Powered by Lam’s Equipment Intelligence® technology, the self-aware Sense.i platform enables semiconductor manufacturers to capture and analyze data, identify patterns and trends, and specify actions for improvement. Sense.i also features autonomous calibration and maintenance capabilities that reduce downtime and labor costs, and delivers machine learning algorithms that allow the tool to self-adapt to minimize process variations and maximize wafer output.

The Sense.i platform has a revolutionary space-saving architecture that will help customers meet their future wafer output targets by producing more than a 50% improvement in etch output density. As semiconductor manufacturers develop smarter, faster, and denser chips, processes are rapidly growing in complexity and number of steps. This requires a greater number of process chambers in a fab and reduces total output for a given floor space. The Sense.i platform’s smaller footprint benefits either a new fab build or a fab undergoing a node-to-node technology conversion.

“Lam is introducing the most innovative etch product that has been developed in the last 20 years,” said Vahid Vahedi, senior vice president and general manager of the Etch product group at Lam Research (LRCX). “Sense.i extends our technology roadmap to meet our customers’ next-generation requirements while solving the critical cost scaling challenges they’re facing in their business. With more than four million wafers processed on Lam etch systems every month, Lam has an installed-base that provides extraordinary learning to innovate, design, and produce the best tools for semiconductor manufacturing.”

Friday, December 21, 2018

Chinese AMEC 5nm plasma etching tools verified by TSMC

DigiTimes report (LINK) that the Chinese OEM Advanced Micro-Fabrication Equipment (AMEC) announced recently its in-house developed 5nm plasma etching tools have been verified by Taiwan Semiconductor Manufacturing Company (TSMC). AMEC is already among TSMC's equipment suppliers for the foundry's 28nm, 10nm and 7nm processes.

Earlier in 2018 AMEC Introduced the Primo Nanova® System, which is the Company's first ICP etch Product for Chipmakers' most advanced memory and logic (LINK). Besides ICP AMEC has products based on CCP etch and platforms for TSV Etch (LINK).
 AMEC Introduced the Primo Nanova® System (AMEC)

Advanced Micro-Fabrication Equipment Inc. (AMEC)
AMEC is China's leading provider of advanced process technology to global manufacturers of semiconductors and solid-state lighting (SSL) products. Headquartered in Shanghai, the company is an entrenched supplier of dielectric and TSV Etch tools, helping chipmakers build devices at process nodes as low as 7nm. To date, nearly 800 AMEC process units have been positioned at 40 leading-edge semiconductor fabs across Asia. The company is also well established in Europe with AMEC MEMS tools running in production at major IDMs. In addition, with its MOCVD system, the company helps SSL manufacturers build today's most advanced LED products. To learn more about AMEC, please visit

Saturday, March 31, 2018

Tokyo Electron reports on patterning technology for advancements in scaling

If you are interested in the latest patterning technology you should read this excellent online publication by Ken Nawa at the Process Integration Center, Tokyo Electron. Tokyo Electron is one of the top supplier for wafer based advanced etch, deposition and clean (and more) tools for the semiconductor industry. Besides the evolution of semiconductor by scaling technology, he covers all the latest advanced technologies:
  • Introduction of advanced patterning technology and challenges
  • SADP – Scaling by thin film formation on sidewall  
  • SAQP – Scaling by extending SADP technology 
  • SAB – Scaling by etch selectivity to multiple materials

Full article: LINK 

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Tuesday, July 14, 2015

Applied Materials announced a next-generation etch tool at SEMICON West

 Applied Materials, Inc. announced a next-generation etch tool at SEMICON West, the Applied Centris(TM) Sym3(TM) Etch system, featuring an entirely new chamber for atomic-level precision manufacturing. To overcome within-chip feature variations, the Centris Sym3 system leapfrogs current tools to provide chipmakers with the control and precision needed to pattern and create densely packed 3D structures in advanced memory and logic chips.

Applied Materials Centris Sym3 - an entirely new chamber for atomic-level precision manufacturing

"Drawing on over 20 years of etch learning and our expertise in precision materials removal, the Sym3 system represents a brand new design, built from the ground up, that solves persistent and impending industry challenges," said Dr. Raman Achutharaman, vice president and general manager of Applied's Etch business unit. "Customer traction has been remarkable, resulting in the fastest adoption rate we've seen for an etch tool in the company's history, with record ramp to production at leading-edge fabs."

The Centris Sym3 etch chamber employs Applied's unique True Symmetry(TM) technology with multiple tuning controls for optimizing global process uniformity to the atomic level. Key to the design is a focus on controlling and removing etch byproducts, which are increasingly hampering within-chip patterning uniformity. The system mitigates byproduct re-deposition to overcome the challenges of line edge roughness, pattern loading and defects - issues that are becoming more limiting for each successive technology node. Combined with an advanced RF technology that controls ion energy and angular distributions, the Sym3 system delivers unsurpassed vertical profiles for high aspect ratio 3D structures.

The Centris Sym3 platform's six etch and two plasma clean process chambers feature system intelligence software to ensure that every process in every chamber matches precisely, enabling repeatability and high productivity for high-volume manufacturing.

Tuesday, April 7, 2015

A spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept!

Prof. Fred Roozeboom and co-workers F. van den Bruele, Y. Creyghton, P. Poodt, and Prof. W.M.M. Kessels (all from Eindhoven University of Technology and TNO, as driving forces behind Spatial ALD and ALE technology), have just published a fantastic open access publication in ECS Journal of Solid State Science and Technology. Just taste the title of this blog text for a moment and then continue reading or down load the article - it´s free, it´s OPEN ACCESS.

Cyclic etch /passivation-deposition as an all-spatial concept towards high-rate room temperature Atomic Layer Etching [OPEN ACCESS]
F. Roozeboom, F. van den Bruele, Y. Creyghton, P. Poodt, and W.M.M. Kessels
ECS Journal of Solid State Science and Technology, 4 (6) pp. N5067-N5076 (2015). doi:10.1149/2.0111506jss

Conventional (3D) etching in silicon is often based on the ‘Bosch’ plasma etch with alternating half-cycles of a directional Si-etch and a fluorocarbon polymer passivation. Also shallow feature etching is often based on cycled processing. Likewise, ALD is time-multiplexed, with the extra benefit of half-reactions being self-limiting, thus enabling layer-by-layer growth in a cyclic process. To speed up growth rate, spatial ALD has been successfully commercialized for large-scale and high-rate deposition at atmospheric pressure. We conceived a similar spatially-divided etch concept for (high-rate) Atomic Layer Etching (ALEt). The process is converted from time-divided into spatially-divided by inserting inert gas-bearing ‘curtains’ that confine the reactive gases to individual injection slots in a gas injector head. By reciprocating substrates back and forth under such head one can realize the alternate etching/passivation-deposition cycles at optimized local pressures, without idle times needed for switching pressure or purging. Another improvement toward an all-spatial approach is the use of ALD-based oxide (Al2O3, SiO2, etc.) as passivation during, or gap-fill after etching. This approach, called spatial ALD-enabled RIE, has industrial potential in cost-effective back-end-of-line and front-end-of-line processing, especially in patterning structures requiring minimum interface, line edge and fin sidewall roughness (i.e., atomic-scale fidelity with selective removal of atoms and retention of sharp corners). 

The publication starts with a History of 3D etching and a description of how and why plasma etching is a key enabling technology and then it gets down to business to introduce the concept behind layer-by layer growth (ALD) or etch (ALE) and more importantly the concept behind spatial layer-by-layer processing. Then via the cyclic Bosch process, and Spatial RIE with Spatial passivation we land at the Grand Finale - Spatial RIE process mode with Spatial ALD passivation!  Or even more beautifully formulated by Prof. Roozeboom himself a spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept!

Layer-by layer-processing
Figure 3.

Schematic of conventional CVD and plasma etching and their layer-by-layer counterparts, ALD and ALEt. ALEt is cycled between modification by chemisorption of a reactant at the surface and, subsequent volatilization of, ideally, one (sub)monolayer by irradiation with an energetic beam or reaction with a co-reactant. For simplicity reasons the etch processes (bottom pictures) are cartooned in plasma-assisted mode, and the deposition processes (top pictures) in thermal mode. The latter two could be plasma-assisted as well. In the conventional processes (CVD and Plasma etch) the chemical reactants are supplied simultaneously and non-interrupted, and in the layer-by-layer processes (ALD and ALEt) they are alternated. (picture used with permission)

Spatial ALD

Figure 4. 

Schematic representation of spatial ALD: a wafer moves horizontally back and forth under spatially divided and confined reaction zones. Arrows pointing upwards indicate exhaust lines. Notice the difference in height of the gas bearing compartments (typically ∼20 to 100 μm) and the deposition compartments (typical height a few mm, and lengths and widths of order ∼1-10 mm).(picture used with permission)

Convential Bosch etching by cyclic surface passivation half-cycles
Figure 6. 

Conventional Bosch etch process scheme for etching silicon with a pre-patterned hard mask atop, using alternating etch and passivation half-cycles. (picture used with permission)

Spatial RIE process mode with C4F8 passivation

Figure 7.

Schematic of spatial RIE process mode with C4F8 passivation of a wafer that reciprocates under spatially divided reaction zones. Arrows pointing upwards indicate exhaust lines. Notice the difference in height of the gas bearing compartments (typically ∼20 to 100 μm) and the plasma compartments (typical height ∼10 mm, and length of several 10 mm's and width of order ∼1 mm). The compartments are connected through a gas bearing envelope. Not to scale; wafers will pass the entire zones before shuttling back.  (picture used with permission)

Spatial ALD oxide passivation module in an all-spatial etch-passivation cluster concept

Figure 8. 

Schematic of alternative all-spatial RIE process mode with spatial ALD oxide passivation (e.g., SiO2, Al2O3, ..). ‘Si’ denotes a Si-precursor, TMA is trimethyl aluminum. Note, that for deep etching and for shallow (‘layer-by-layer’) etching the wafer exposure times in the respective zones will differ, which will imply different residence times, or different numbers of unit cells in the two main compartments.  (picture used with permission)

At the end after showing a number of case studies, Prof. Roozeboom et al summarizes - and we all believers will agree on these conclusions - namely that:
  • The potential of ALD-assisted nanomanufacturing technologies like Atomic Layer Etching (ALEt) concepts derived from etch-purge-passivation/deposition-purge subroutines in (D)RIE and ALD is now clearly being recognized and promoted.
  • The ongoing scaling of Moore's Law will soon require the implemention of these complementary technologies to meet the 10-nm challenges in surface and sidewall passivation of resist and feature patterns that is required to minimize interface, line edge and fin wall roughness.
  • For cost reasons and flexibility in local pressure, i.e. (an)isotropy control, in the spatial etch and purge compartments one can envisage a gradual shift to the adoption of ALD-enabled RIE (we abbreviate it as ALDeRIE) in the spatial domain as well. 
  • Obviously, the spatially divided version is not commercially available yet and not straightforward, but – once realized for dedicated materials and topographies – it will certainly lead to far improved price-performance ratios in Atomic Layer Etching. 

Fred Roozeboom appointed as ECS Fellow, The Electrochemical Society appointed Prof. dr. Fred Roozeboom as Fellow of the Electrochemical Society  for his Scientific contributions to Solid-State Science & Technology and its impact on the society. He has been awarded especially because of his contributions on the areas of rapid thermal processing, passive 3D and heterogeneous integration, reactive ion etching and atomic layer deposition (ALD). He received his award at the Plenary Session of the 226th ECS meeting. October 5, 2014, Cancun, Mexico.