Tuesday, September 17, 2024
Technological Innovations in Semiconductor Manufacturing: Insights from Tokyo Electron's 2024 Integrated Report
Thursday, July 11, 2024
Tokyo Electron Introduces Acrevia Tool to Enhance EUV Lithography
Tokyo Electron has introduced Acrevia, a state-of-the-art gas cluster beam (GCB) system aimed at refining patterns created by EUV lithography. This advanced tool is set to reduce the necessity for EUV double patterning, thereby improving chipmaking yields and lowering production costs. Acrevia addresses critical challenges such as line edge roughness (LER), a common issue in lithography that affects the precision of pattern edges and overall chip performance. By optimizing pattern sidewalls through precise etching, Acrevia promises to significantly enhance within-wafer uniformity and mitigate LER, contributing to higher yield and better chip reliability. While not replacing High-NA EUV lithography, Acrevia marks a substantial leap forward in semiconductor manufacturing innovation.
Sources:
Friday, April 19, 2024
Intel's Strategic Leap with 14A Node and DSA: Pioneering Next-Gen Semiconductor Manufacturing
Semi Analysis recently published a deeper dive into of Directed Self Assembly (DSA) and prospects of Intel using it at their 14A node (Link below). Intel's latest efforts in semiconductor manufacturing have brought considerable attention to its 18A node, yet it's the 14A node that is most important according to the analysis for the success of Intel Foundry's IDM 2.0 strategy. While the industry watches the ongoing discussions around the merits of TSMC's N2 and Intel’s 18A technologies, Intel is quietly setting a foundational stage with its 14A node, aiming to solidify customer trust and secure critical, high-value chip projects for the future. A key element in Intel's strategy may be the adoption of DSA that could significantly reduce lithography costs. DSA utilizes the self-organizing properties of block copolymers (BCPs) that assemble into predetermined patterns when guided by an underlying template. This approach promises to lower the doses required in extreme ultraviolet (EUV) lithography, allowing for more efficient patterning at reduced costs.
It is well known that Intel plans to be the first major company to implement ASML’s high-NA EUV lithography scanners in high volume, despite the higher costs associated with single exposure high-NA systems compared to low-NA double patterning. It was also recently reported on X and other places that ASML is delivering a High-NA System to another player. SemiAnalysis argues that, the economic challenge posed by high-NA technology is addressed through the integration of DSA, which can improve the final pattern quality and dramatically reduce the necessary dose, thus potentially making high-NA economically more viable.
The benefits of DSA are significant:
- The ability to produce finer features with lower line edge roughness and increased throughput, thanks to its ability to heal discrepancies in the EUV guide patterns.
- Substantial cost savings and improved yield, especially for layers critical to the performance of advanced logic chips (bigger dies like AI accelerators).
However, DSA's integration into a commercial manufacturing environment is not without risks. The risks associated with Intel's adoption of DSA include:
- The primary risk with any new patterning technology is defectivity, for DSA it is linked to the chemical purity of the block copolymers (BCP). Synthesizing BCP to extremely high purities is challenging, and any inhomogeneity directly impacts the critical dimension (CD), leading to defects. Trace metals need to be below 10 parts-per-trillion, and filtering out organic impurities is difficult, impacting the viability of DSA for mass production. My assessment - Expect this to come from a MERCK or a Japanese chemical vendor.
- DSA is inherently limited to producing 1D line/space patterns or contact hole arrays, restricted to a single pitch per layer. This complicates the integration with other process technologies that might require more diverse patterning capabilities. However, these issues have potential solutions similar to those used in multi-patterning schemes.
- Despite the theoretical benefits and recent advances in DSA, it remains largely untested in high-volume, leading-edge manufacturing. Intel is pioneering the use in high-NA scenarios, but the broader adoption across the industry, including by competitors like TSMC who are also developing DSA, remains uncertain.
Source: Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA) (semianalysis.com)
So let´s do the Patbase Test - how does this hold out if we dig into historical and current patent filing by the suspects!
Yes indeed, we have seen much increased filing the past decade or so representing a typical hype cycle. The hype cycle is a model developed by Gartner that describes the progression of a technology from inception to widespread adoption and maturity. It typically consists of five phases: the Technology Trigger, Peak of Inflated Expectations, Trough of Disillusionment, Slope of Enlightenment, and Plateau of Productivity. So for DSA in semiconductor manufacturing, the technology first garnered attention when its potential applications in advanced lithography were identified (2000-2010), marking the Technology Trigger. Interest surged about 2011, leading to a Peak of Inflated Expectations around 2016/2017, evidenced by a spike in patent filings as companies raced to capitalize on the emerging technology. However, as practical and economic challenges such as defectivity and integration complexities became evident, the enthusiasm waned, and DSA entered the Trough of Disillusionment. During this phase, the technology's limitations led to a decline in interest as initial expectations were not met. Over time, as more sustainable applications and improvements are developed, DSA may progress into the Slope of Enlightenment, where understanding and optimization occur as described in the assessment by SemiAnalysis, before finally reaching the Plateau of Productivity in the years to come, where it becomes a standard part of semiconductor manufacturing processes. This progression through the hype cycle reflects the typical maturation path of innovative technologies in the industry. Please note that there is a delay in patent filing data of up to 18 months so 2022, 2023 and 2024 are not complete yet.
Patent filing since 2000 in DSA (Patbase, 2024-04-19)
2. Yes, Intel is actively filing DSA patents and in the lead, and so is TSMC, along with other key players in the ecosystem. Over the past decade, the pattern of DSA patent filings has been quite revealing. Initially, GlobalFoundries and IBM in Upstate New York were early filers. GlobalFoundries ceased their filings around the time they decided not to pursue 7 nm and nodes below. IBM also stopped filing after completing their 2 nm demonstration on 300 mm wafers in 2021. Main contenders Intel and TSMC have been consistently filing DSA patents throughout the hype cycle and have continued to do so. Notably, there has been a clear acceleration in Intel's patent filings since 2019, although there was a slight drop during the COVID-19 lockdowns. Looking at chemical suppliers, Merck has taken the lead, with increased filings beginning in parallel with Intel from 2019 onwards, and accelerating until today. Other suppliers such as JSR, Shin-Etsu, and Brewer Science are also active in the DSA space. In the segment of wafer equipment OEMs, Tokyo Electron and SCREEN have been dominant. However, SCREEN appears to have recently exited the game.
In Summary - good assessment by SemiAnalysis and i passes the Patbase Test!
Tuesday, March 19, 2024
Tokyo Electron ALD of AlN Thin Films Report Unprecedented Uniformity on Large Batch 200 mm Tool
In the rapidly evolving world of semiconductor technology, achieving high uniformity in thin films is important for enhancing production yield and device performance. In a study led by Partha Mukhopadhyay and his team at Tokzo Electron has made significant strides in this domain, using ALD of aluminum nitride (AlN) thin films on a 200 mm large batch furnace platform. AlN is particularly relevant for gallium nitride (GaN)-based power industry, where AlN's wide bandgap, high dielectric constant, and superior thermal conductivity make it an ideal choice for various applications, including UV LEDs, transistors, and micro-electromechanical systems.
The study's focus lies in its ability to maintain extraordinary uniformity across large batches of 200 mm wafers, achieving a thickness variation of less than 0.5 Å. This level of uniformity was obtained by optimizing the ALD process in a reactor capable of handling over 100 wafers, marking a significant achievement in high-volume production environments. The research examined the effects of deposition temperatures, film thicknesses, and different substrate types, including Si, quartz, and GaN/Si(111), on the material and optical properties of the AlN films.
One of the key findings was the identification of an optimal narrow temperature window between 300°C and 350°C for the deposition process, with 350°C being the sweet spot. The study also delved into the nuanced challenges of nucleation on different substrates, revealing that substrate-inhibited growth and a non-linear deposition rate are pivotal factors to consider. This understanding is crucial for maintaining uniformity in extremely thin films, which are sensitive to the underlying substrate's crystal orientation.
From a compositional standpoint, the development showcased the high purity of the AlN films, with negligible carbon and oxygen contamination. This purity is essential for the semiconductor industry, particularly for applications where chemical stability is critical. The study's rigorous material analysis, which included techniques like XPS and TEM, provided in-depth insights into the AlN films' structural and compositional integrity.
Optically, the AlN films demonstrated a bandgap of 5.8 eV, a key attribute for their use in optoelectronic applications. The research also highlighted the refractive index's dependence on film thickness and deposition temperature, offering valuable data for the design and optimization of optical devices.
In summary, this study represents a significant progress in ALD of AlN thin films, combining high throughput with exceptional film uniformity and quality.
Friday, December 15, 2023
Tokyo Electron Develops an Extreme Laser Lift Off Technology That Contributes to Innovations in 3D Integration of Advanced Semiconductor Devices
Friday, September 15, 2023
Tokyo Electron Integrated Report/Annual Report 2023 available for download
For anyone involved in the semiconductor industry or those eager to gain fresh perspectives in this dynamic field, this report is a must-read. It not only showcases TEL's history and strategies but also sheds light on industry trends, sustainability practices, and the exciting developments shaping the future of semiconductor technology. Dive into this comprehensive report and unlock valuable knowledge about TEL's journey and the semiconductor industry at large.
Monday, August 28, 2023
The Future of Nanoimprint Lithography: Exploring Possibilities and Challenges for High-Volume Production
Nanoimprint lithography (NIL) has emerged as a promising technique for the replication of intricate nano-scale features, offering higher resolution and uniformity compared to traditional photolithography methods. As semiconductor technology advances towards smaller and more complex structures, NIL holds the potential to revolutionize high-volume production processes. In this blog post, we'll delve into the current status of nanoimprint lithography and the possibilities it presents for future high-volume productions, as well as the main issues and concerns that need to be addressed.
NIL utilizes a process where a patterned mask is brought into contact with a resist-coated substrate. The resist fills the relief patterns in the mask through capillary action, creating precise nano-scale features. With a focus on simplicity and cost-effectiveness, NIL doesn't require the complex optics found in traditional photolithography, making it an attractive option for semiconductor memory applications.
Early work on combining NIL and Atomic Layer Etching by AlixLabs Founders
Most Recent Achievements:
Recent study by TEL and Canon have demonstrated NIL's resolution capabilities of better than 10 nm, positioning the technology as a candidate for printing multiple generations of critical memory levels using a single mask. The potential to eliminate material waste by applying resist only where necessary adds to its appeal. Moreover, the simplicity and compactness of NIL equipment allow for clustered setups, enhancing productivity.
NIL Addressing Challenges in DRAM Scaling:
Dynamic Random Access Memory (DRAM) memory faces the challenge of continued scaling, with roadmap targets aiming at half pitches of 14 nm and beyond. The complexities of achieving tighter overlays, greater precision in critical dimensions, and edge placement errors demand innovative solutions. In DRAM fabrication, overlay requirements are even more stringent than in NAND Flash, with an error budget of 15-20% of the minimum half pitch.
Edge Placement Error (EPE):
EPE, the difference between intended and printed features, poses a significant challenge in modern semiconductor manufacturing. The intricacies of multiple patterning schemes and intricate device layouts contribute to EPE's complexity. Ensuring accurate placement of features is critical for maintaining device yield and performance.
The Quasi-Atomic Layer Etch (Quasi-ALE) process
The process is a specialized etching technique employed in advanced semiconductor manufacturing, particularly in processes like Nanoimprint Lithography (NIL). Quasi-ALE combines elements of Atomic Layer Etching (ALE) and conventional etching methods to achieve precise and controlled material removal. In the context of Nanoimprint Lithography, Quasi-ALE is used to etch materials with exceptional precision, targeting nanoscale features while minimizing damage to the surrounding areas. It involves a cyclic process where alternating etching and passivation steps are applied to the substrate. Each cycle removes a controlled layer of material, ensuring highly uniform etching and minimal lateral etch. One can discribe Quasi-ALE as a more productive way of performing ALE.
The key steps of the Quasi-ALE process typically involve:
1. Etch Step: During this step, a reactive gas is introduced into the etch chamber, which chemically reacts with the material to be removed. This reaction results in the selective removal of the material layer.
2. Passivation Step: In this step, a passivating species is introduced, forming a protective layer on the substrate surface. This layer prevents further etching and preserves the material beneath.
3. Purge and Repeat: The chamber is purged to remove any excess gases, and the process is repeated in a cyclical manner. Each cycle removes a controlled atomic layer of material.
Quasi-ALE is particularly advantageous for applications requiring high precision and control, such as in Nanoimprint Lithography, where maintaining accurate pattern dimensions and minimizing damage is critical. By combining the benefits of both ALE and traditional etching, Quasi-ALE enables advanced semiconductor manufacturing processes to achieve unprecedented levels of accuracy and uniformity.
Addressing EPE with Nanoimprint Lithography:
Researchers are actively exploring techniques to mitigate edge placement errors in nanoimprint lithography. This includes focusing on overlay accuracy, critical dimension uniformity (CDU), and local CDU. Compensatory methods such as dose control and reverse tone pattern transfer are being investigated to improve CDU and minimize errors.
The Role of Dose Control:
Varying the exposure dose offers a means of achieving small shifts in critical dimensions. Initial studies suggest that dose variations could lead to CD shifts of one to 2 nm. This strategy holds promise for enhancing CDU in the imprint process.
Reverse Tone Pattern Transfer:
Reverse tone processes, involving spin-on hard mask (SOHM) application and etch-back, offer an alternative approach to pattern transfer. While this method provides advantages such as reduced resist erosion and improved wall angles, trade-offs between CDU and line width roughness (LWR) need to be addressed.
Looking Ahead: The Possibilities and Challenges:
While NIL exhibits impressive potential, there are key challenges to overcome before it can be effectively integrated into high-volume semiconductor manufacturing. Ensuring precise overlay accuracy, managing complex CDU requirements, and effectively addressing edge placement errors remain pivotal. As the industry strives to achieve the roadmap's aggressive scaling targets, the evolution of nanoimprint lithography will undoubtedly play a crucial role.
Nanoimprint lithography is poised to reshape the semiconductor manufacturing landscape, offering higher resolution and cost-efficiency compared to traditional methods. With ongoing research and development, addressing challenges such as overlay accuracy, CDU, and EPE, the path to successful high-volume production through NIL seems promising. As technology continues to advance, the journey towards perfecting nanoimprint lithography is an exciting one, holding the potential to shape the future of chip fabrication.
Tokyo Electron (TEL):
TEL specializes in Nanoimprint Lithography (NIL) technology, offering precision equipment, advanced etching solutions, and expertise in process control. They excel in alignment, overlay correction, CDU management, and etching technology.
Canon:
Canon contributes to Nanoimprint Lithography (NIL) advancement by leveraging TEL's strengths in alignment, overlay correction, CDU management, and advanced etching solutions. They integrate these capabilities with the Reverse Tone Pattern Transfer, ensuring precise pattern replication and fidelity. Canon's focus on innovation drives high-resolution, cost-effective solutions for semiconductor manufacturing.
Canon has introduced a groundbreaking solution in the field of semiconductor technology with the development of the world's first mass-production equipment called the "FPA-1200NZ2C." This innovative tool utilizes nanoimprint lithography, a cutting-edge technique that involves imprinting nanometer-scale mask patterns onto substrates. By adopting this novel approach, Canon aims to overcome the limitations of conventional miniaturization methods. The FPA-1200NZ2C is already in use by Toshiba Memory, a prominent semiconductor memory manufacturer. This advancement marks a significant step forward in semiconductor manufacturing, enabling the creation of more intricate and advanced circuit patterns.
Sources:
High-Definition Nanoimprint Stamp Fabrication by Atomic Layer Etching — Lund University
Nanoimprint post processing techniques to address edge placement error (spiedigitallibrary.org)
Nanoimprint Lithography | Canon Global
FPD Lithography Equipment | Canon Global
Benefits of atomic-level processing by quasi-ALE and ALD technique - IOPscience
Acknowledgement :
Thanks for sharing the SPIE article on LinkedIn and giving insights Frederick Chen!
Tuesday, August 22, 2023
Tokyo Electron's Q1 2024 Earnings Call Unveils Resilient Performance and Strategic Focus
Monday, June 12, 2023
Tokyo Electron Introduces Breakthrough Memory Channel Hole Etch Technology for 3D NAND Flash, Reducing Global Warming Potential by 84%
Tokyo Electron's Innovative Etch Process Enables Ultra-fast 10-µm-deep Etching for 3D NAND Flash with Over 400 Layers, Showcased at Symposium on VLSI Technology and Circuits
Tokyo Electron (TEL) has achieved a significant technological milestone by developing a cutting-edge etch technology capable of creating memory channel holes in advanced 3D NAND devices with over 400 layers. This breakthrough process, pioneered by the development team at Tokyo Electron Miyagi, leverages cryogenic temperatures to achieve exceptionally high etch rates, marking the first time dielectric etch application has been utilized in this temperature range.
The groundbreaking technology not only enables the etching of memory channel holes up to 10 µm deep with a high aspect ratio in just 33 minutes but also boasts an impressive 84% reduction in global warming potential compared to previous methods. The etched structure exhibits well-defined geometry, as demonstrated by cross-section SEM and FIB cut images.
TEL's research team behind this groundbreaking technology will present their findings at the prestigious 2023 Symposium on VLSI Technology and Circuits, a renowned international conference on semiconductor research. Their contribution showcases the potential for even larger capacity 3D NAND flash memory.
The presentation, titled "Beyond 10 µm Depth Ultra-High Speed Etch Process with 84% Lower Carbon Footprint for Memory Channel Hole of 3D NAND Flash over 400 Layers," will be delivered by Y. Kihara, M. Tomura, W. Sakamoto, M. Honda, and M. Kojima from Tokyo Electron Miyagi Ltd. The session, scheduled for Tuesday, June 13, from 2 p.m. to 3:40 p.m., will take place in the NAND Flash section of the Technology Session 3 [Shunju II].
For detailed event information about the 2023 Symposium on VLSI Technology and Circuits, please click here. Stay tuned for TEL's technology presentation, which combines semiconductor advancements and environmental protection efforts. 2023 Symposium on VLSI Technology and Circuits
Sunday, September 4, 2022
Tokyo Electron is forcastiong high continued sales in semiconductor equipment sales 2023 - slow down in DRAM
Thursday, April 8, 2021
Why China denied Applied Materials take over of Hitachi Kokusai
Wednesday, March 24, 2021
Canon, SCREEN and Tokyo Electron to join Japan advanced chipmaking project for 2nm
Wednesday, February 3, 2021
LIVE Stream - Advanced Process Technologies to Enable Future Devices and Scaling (invited), Rob Clark Tokyo Electron
Saturday, November 28, 2020
Applied Materials will regain its No. 1 ranking in the semiconductor equipment market in 2020 from ASML
- Atomic Layer Deposition
- MOCVD
- Furnace
- Dielectric Etch
- Spray Processing
- Dielectric Etch (including ALE)
- Wet Stations
1. Move in to top 3 spot in ALD2. Take number 2 spot in Furnace business
Sunday, July 7, 2019
Rapid and Selective Deposition of Patterned Thin Films on Heterogeneous Substrates via Spin Coating
Source: "Rapid and Selective Deposition of Patterned Thin Films on Heterogeneous Substrates via Spin Coating" LINK
Saturday, March 16, 2019
VLSIresearch released its list of the top Semiconductor Equipment Suppliers for 2018 shown big wins for Japanese OEMs
Wednesday, May 2, 2018
Tokyo Electron is Challenging ASM International as The Leader in ALD Market share
- ALD Tube - Large batch furnaces, typically loading 100 or more wafers
- Single wafer platforms
- Multi wafer platforms, spatial or multi station
Saturday, March 31, 2018
Tokyo Electron reports on patterning technology for advancements in scaling
- Introduction of advanced patterning technology and challenges
- SADP – Scaling by thin film formation on sidewall
- SAQP – Scaling by extending SADP technology
- SAB – Scaling by etch selectivity to multiple materials
Full article: LINK