Showing posts with label Semiconductor equipment. Show all posts
Showing posts with label Semiconductor equipment. Show all posts

Saturday, November 28, 2020

Applied Materials will regain its No. 1 ranking in the semiconductor equipment market in 2020 from ASML

According to recent published data by The Information Network (Seeking Alpha LINK), Applied Materials will regain its top ranking in the semiconductor equipment market in 2020 from ASML. Fab equipment spend in 2020 was enhanced from pull-ins of sales into China and Taiwan, with 3Q QoQ increases of 22.5% and 36.2%, respectively.

As is well known ASML and Applied Materials does not compete in their  business segments, Lithography (ASML) resp. Deposition & Etch (Applied Materials). Applied Materials has a number 1 spot in PVD, CVD, Epi, CMP and Implant/Doping. However, business segments where Applied Materials so far has not been successful to reach a top 3 position in the past years include:
  • Atomic Layer Deposition
  • MOCVD
  • Furnace 
  • Dielectric Etch  
  • Spray Processing
  • Dielectric Etch (including ALE)
  • Wet Stations
As is known, Applied Materials have several times made very serious attempts to enter the ALD segment, but failed several times to compete with ASMI, Tokyo Electron and the South Korean OEMs (Jusung Engineering, Wonik IPS and Eugene Technology. In 2019 Applied Materials announced that it will acquire Japanese Kokusai (LINK) but the final agreement is yet not settled. If successful Applied will have an opportunity to kill 2 birds with one stone:

1. Move in to top 3 spot in ALD
2. Take number 2 spot in Furnace business


Table based on information and own assumptions in the article (Seeking Alpha LINK)

Saturday, March 16, 2019

VLSIresearch released its list of the top Semiconductor Equipment Suppliers for 2018 shown big wins for Japanese OEMs

VLSI Research report well above average growth for ASML (NL), Tokyo Electron (JPN), Advantest (JPN), Kokusai (JPN), Daifuku (JPN) and Canon (JPN) so a big win for Japan and the Netherlands last year. All Japanese companies outperform the market growth 2018!

Dan Hutchenson: "VLSIresearch released its list of the top Semiconductor Equipment Suppliers for 2018. Notable shifts were TEL passing Lam to take the top spot. Advantest past Screen for 7th with the highest growth of any chip equipment manufacturer. While ASM Pacific passed SEMES. For details, see: https://lnkd.in/gDxccnX

Most growth is seen in Litho as for each Immersion or EUV tool that is installed a bunch of Tokyo Electron tools come as well like e.g. the TEL Track platform.

With respect to ALD, judging by ASMI, TEL and Kokusai it seems that ALD was able to capture all of the growth in 2018 and maybe a bit more. In April the Japanese companies start their 2018 annual reporting so then we will know more for now we have the ASMI report to study (LINK).



Saturday, January 6, 2018

Lam Research and Tokyo Electron took market shares in 2017

Currently the fabs are running hot and expanding and 2018 is expected to continue to grow according to OEMs and market research companies like o VLSI Research (CEO Dan Hutcheson, see below). Solid State Technology reports, based on recent market research by The Information Network (LINK) that Market leader Applied Materials lost market shares in 2017 to the main competitor Tokyo Electron and Lam Research.

"Applied Materials 1.3 share points, dropping from 28.2% in 2016 to 26.9% YTD (year to date). Gaining share are Tokyo Electron Ltd. (TEL), which gained 2.4 share points while rising from 17.0% in 2016 to 19.4% in 2017 YTD. Lam Research gained 1.6 share points and growing from a 19.0% share in 2016 to a 20.6% share in 2017 YTD."


The three companies compete in the following areas with huge growth due to the memory boom in 2017 (3DNAND and DRAM):

  • conductor and dielectric etch equipment
  • deposition equipment - single/multiwafer ALD and CVD
CVD equipment share is roughly 3X that of ALD and ALD passed PVD in 2015 (according to VLSI Research). Furnace ALD and CVD is dominated by Tokyo Electron and Kokusai, however it is a smaller segment as compared to single and multi wafer ALD and CVD. ASMI, the leader in ALD single wafer equipment does not seem to have been able to grow with memory, down from 2.0% to 1.7%.

Please find the full article here: LINK

 


Wednesday, January 3, 2018

Get back to work - SEMI projects continued boom in fab equipment spending for 2018

MILPITAS, Calif. ─ January 2, 2018 ─ The year-end update to the SEMI World Fab Forecast report reveals 2017 spending on fab equipment investments will reach an all-time high of $57 billion. High chip demand, strong pricing for memory, and fierce competition are driving the high-level of fab investments, with many companies investing at previously unseen levels for new fab construction and fab equipment. See figure 1.
World Fab Forecast Figure 1
Figure 1


The SEMI World Fab Forecast data shows fab equipment spending in 2017 totaling US$57 billion, an increase of 41 percent year-over-year (YoY). In 2018, spending is expected to increase 11 percent to US$63 billion.

While many companies, including Intel, Micron, Toshiba (and Western Digital), and GLOBALFOUNDRIES increased fab investments for 2017 and 2018, the strong increase reflects spending by just two companies and primarily one region.

Thursday, August 11, 2016

Tokyo Electron to Begin Accepting Orders for Triase+™ EX-II™ TiON

Simultaneously as Lam Research launches Fluorine free Tungsten for 3DNAND and DRAM, Tokyo Electron is launching their newset version of the market leading TiN Trias Tool that has been dominated the TiN MIM Capacitor electrode (e.g. DRAM memory cells) market since there was a market for it. The first version that was rolled out to most DRAM fabs at the introduction of high-k used a processes called SFD - Sequential Flow Deposition, which is a sort of pulsed CVD with  proprietary reductive gas flow pulses by NH3. Later a even more advanced processes called ASFD -  Advanced Sequential Flow Deposition has been developed. The key to these type of TiCl4/NH3 based processes is that it will always beat ALD in terms of throughput without compromising in film quality including great stepcoverage, i.e., conformal growth. Yet another reason why Tokyo Electron has been dominating the TiN market is the use of in-situ clean by ClF3. 
 




 
Tokyo Electron to Begin Accepting Orders for Triase+™ EX-II™ TiON, a Single-Wafer Metallization System

Aug 8, 2016 Tokyo Electron Limited (TEL) announced today that it would begin accepting orders for the Triase+TM EX-IITM TiON (titanium oxynitride) single-wafer metallization system in August 2016.

The Triase+ EX-II TiON is a high-speed, single-wafer ASFD  [1] system capable of oxidizing TiN (titanium nitride) films. This new system inherits the optimized reactor chamber and unique gas injection mechanism that characterize the Triase+ EX-II TiN system. Because the TiON film deposited by the Triase+ EX-II TiON has a higher work function [2] than that of a conventional TiN film, it effectively reduces leakage current when used to form the electrodes of an MIM capacitor [3]. Customers already using the TiN system can upgrade to the TiON system by modifying their existing systems, thereby reducing investment costs.

"The Triase+ EX-II TiON is a product with significant cost and performance benefits that can meet the continual demand for miniaturization in semiconductor manufacturing processes," said Shingo Tada, Vice President and General Manager of Thin Film Formation BU at TEL. "We intend to keep expanding the type of films the Triase+ EX-II series can handle, enabling it to cover an even greater variety of metallization applications in the future."

Leveraging its ability to develop innovative technologies, TEL will continue to deliver products that add high value and optimize solutions to the technological problems associated with advanced devices.


[1] ASFD: Advanced Sequential Flow Deposition. A low-temperature processing method for forming nanoscale metal films with highly-engineered properties.
[2] Work function: The minimum quantity of energy required to remove an electron from the surface of a solid.
[3] MIM capacitor: Metal-Insulator-Metal capacitor. It consists of an insulator layer between two metal layers.

Wednesday, August 10, 2016

[UPDTAE] Lam Research launch New ALTUS(R) Max E Series for Low-fluorine, Low-stress, and Low-resistivity ALD Tungsten

[UPDATE] :  Lam Blog - Innovative Tungsten ALD Process Provides Pathway to New Memory Chip Production : http://blog.lamresearch.com/innovative-tungsten-ald-process-provides-pathway-to-new-memory-chip-production/


 ALTUS Max E Series 4 station chambers (Picture from Lam Blog)

FREMONT, CA -- (Marketwired) -- 08/09/16 -- Lam Research Corp. (NASDAQ: LRCX), an advanced manufacturer of semiconductor equipment, today introduced an atomic layer deposition (ALD) process for depositing low-fluorine-content tungsten films, the latest addition to its industry-leading ALTUS® family of products. With the industry's first low-fluorine tungsten (LFW) ALD process, the ALTUS Max E Series addresses memory chipmakers' key challenges and enables the continued scaling of 3D NAND and DRAM devices. Building on Lam's market-leading product portfolio for memory applications, the new system is gaining market traction worldwide, winning production positions at leading 3D NAND and DRAM manufacturers and placement at multiple R&D sites.

ALTUS Max E Series 4 station chambers shuffling wafers (Picture from Lamresearch.com)

"Consumer demand for ever more powerful devices is driving the need for high-capacity, high-performance storage, and deposition and etch are key process technology enablers of advanced memory chips," said Tim Archer, Lam's chief operating officer. "With the addition of the ALTUS Max E Series, we are expanding our memory portfolio and enabling our customers to capitalize on this next wave of industry drivers. Over the past twelve months, as the 3D NAND inflection has accelerated, we have doubled our shipments for these applications, leading to the largest deposition and etch installed base in our 3D NAND served markets."

As manufacturers increase the number of memory cell layers for 3D NAND, two issues have become apparent for tungsten deposition in the word line fill application. First, fluorine diffusion from the tungsten film into the dielectrics can cause physical defects. Second, higher cumulative stress in devices with more than 48 pairs has resulted in excessive bowing. The resulting defects and stress can cause yield loss, as well as degraded electrical performance and device reliability. Because of these issues, tungsten films for advanced 3D NAND devices must have significantly reduced fluorine and intrinsic stress. Further, as critical dimensions shrink, resistance scaling becomes more challenging for the DRAM buried word line, as well as for metal gate/metal contact applications in logic devices.

"As memory chip manufacturers move to smaller nodes, the features that need to be filled are increasingly narrow and have higher aspect ratios," said Sesha Varadarajan, group vice president, Deposition Product Group. "Lam's new LFW ALD solution uses a controlled surface reaction to tune stress and fluorine levels and to lower resistance, all while delivering the required tungsten fill performance and productivity. When compared to chemical vapor deposition tungsten, the ALTUS Max E Series lowers fluorine content by up to 100x, lowers stress by up to 10x, and reduces resistivity by over 30%, solving some of our customers' most critical scaling and integration challenges."

The ALTUS Max E Series with LFW ALD technology offers a unique all-ALD deposition process that leverages Lam's PNL® (Pulsed Nucleation Layer) technology, which is the industry benchmark for tungsten ALD with 15 years of market leadership and more than 1,000 modules in production. Lam led the transition of chemical vapor deposition (CVD) tungsten nucleation to ALD tungsten nucleation with its PNL technology. The company continued that leadership by advancing low-resistivity tungsten solutions with its products ALTUS® Max with PNLxT™, ALTUS® Max with LRWxT™, and ALTUS® Max ExtremeFill™ for enhanced fill performance.

The ALTUS products use Lam's quad-station module (QSM) architecture to allow per-station optimization of tungsten nucleation and fill for fluorine, stress, and resistance without compromising fill performance since station temperature can be set independently. The QSM configuration also maximizes productivity of the all-ALD process by providing up to 12 pedestals per system, enabling the highest footprint productivity in the industry.

Wednesday, June 22, 2016

Hydrogen Peroxide Gas Delivery for ALD, Annealing, and Surface Cleaning in Semiconductor Processing

In order for IDMs and Foundries to follow Moore’s Law, semiconductor engineers have been forced to continuously shrink semiconductor device dimensions, so that some barrier layers are as thin as 3 atoms. Semiconductor processes affected by shrinkage include atomic layer deposition (ALD), annealing, wafer cleaning, thermal oxidation, thin film growth, etching, and interface layer passivation. Present materials used in semiconductors can breakdown at this atomic scale and must be replaced by new materials to meet low power consumption, high performance and low cost targets. These new replacement materials come with their own set of process challenges.

Atomic Layer Depostion


ALD has been used in high-volume semiconductor manufacturing since 2004 [1] and according to Chuck del Prado, CEO of ASMi, one of the world-leading companies in the field [2]:

“ALD is now firmly established as a key enabling technology. Today, ALD has become a critical technology for the manufacture of virtually all leading-edge semiconductor devices. The leading customers in our industry have already ramped several device generations based on our ALD equipment – for high-k metal gate applications in logic and foundry and for multiple patterning applications in the memory sector.”
 

The 3D challenge in high aspect ratio structures


The new atomically ultrathin films are more sensitive to environmental conditions than thicker structures from past design nodes. Precise cleaning and preparation is required to prevent atoms from straying into other layers. Complicating the process is that these layers are no longer planar, but are three dimensional shapes with very high aspect ratios approaching 150:1 for DRAM memory cell capacitors and 3DNAND flash memory charge trap devices, creating inverted skyscrapers on an atomic layer.


Samsung presented a low cost manufacturing of 20 nm DRAM and beyond at IEDM2015 using honeycomb structure narrow gap air-spacer technology (left). For visualisation, here (right) the advanced High Aspect Ratio etch and ALD that is required for 3DNAND flash memory manufacturing in a reverse engineering cross section by Chipworks from a SAMSUNG V-NAND Flash array.
Processing at the bottom of these extremely deep structures is nearly impossible. There are two main challenges:
  1. Chemicals must be stable enough to reach the bottom, but reactive enough to be effective when they contact the bottom target site.
  2. Low temperatures are needed to prevent migration of atoms in and out of the layers, so the chemicals must be active at low temperatures.
Chemicals used today for thin film oxidation do not meet these manufacturing challenges. This has forced R&D engineers to look for alternatives. The range of oxidants in use today include water, ozone and O2 plasma. Yet, in one way or another, all of these oxidants are deficient for fabrication of these new device structures under atomic level constraints. To address these challenges, RASIRC has developed a new technology that enables the common liquid oxidant, hydrogen peroxide, to be converted into a controlled and repeatable oxidant gas. This new product is called the Peroxidizer®. 
 

Hydrogen Peroxide Gas (HPG)

RASIRC specializes in products that generate and deliver gas to fabrication processes. Each unit is a dynamic gas plant in a box—converting common liquid chemistries into safe and reliable process gas on demand.. First to generate ultra-high purity (UHP) steam from de-ionized water, RASIRC technology can now also deliver hydrogen peroxide gas in controlled, repeatable concentrations.

Hydrogen Peroxide Gas (HPG) is a powerful and versatile oxidant for processing new materials and 3D structures. HPG is now available in stable, high concentration and offers significant benefits to ALD, annealing and cleaning applications. The Peroxidizer is an order of magintude improvement over its predecessor and overcomes the limits of pre‐humidification and high concentration H2O2 liquid supply by concentrating liquid inside the vaporizer. It handles gas flows of 5 to 30 slm in vacuum or atmospheric conditions. It delivers H2O2 concentrations from 12,500 to 50,000 ppm, which equates to 1.25 to 5% gas by volume. The Peroxidizer delivers a 4:1 water to Peroxide ratio. This is not possible with other high temperature vaporization methods due to H2O2 decomposition.

The membrane used in the vaporizer preferentially vaporizes H2O2 relative to water. This allows the concentration to stay below 75% and 90°C in the vaporizer while being able to generate 50,000 ppm. The fab only needs to supply 30% w/w, which is already in use throughout most facilities.


The above frames illustrate the Peroxidizer concentration process. At top, vaporizer is filled with 30% w/w H2O2. As move to the bottom, carrier gas passes through vaporizer solution and water vaporizes preferentially. Last frame shows that solution has reached mass balance and stable, high concentration H2O2 can be sent to process.

Hydrogen peroxide is a hazardous chemical and must be handled properly to prevent exposure of operators to unsafe chemical conditions. With proper design, installation, and operator training, hydrogen peroxide can be a viable alternative to other oxidants. The Peroxidizer includes a range of safety features focused on temperature, concentration, pressure, liquid and gas leak detection, venting and liquid handling. 

H2O2 is auto‐refill capable. If a continuous supply of 30% H2O2 liquid is available, the Peroxidizer can run 24/7. For R&D, the Peroxidizer can be manually refilled with an internal source container to run 4 to 24 hours depending on flow rate.
  • Primary interlock loop will shutoff power when any of a number of safety conditions occur.
  • Temperature safeties include redundant thermal interlocks with thermal switches for heaters.
  • H2O2 liquid and headspace temperatures are interlocked into the safety control loop.
  • Concentration safety features include level sensors for overfill and low liquid conditions. If liquid level is too low, an alarm is displayed and carrier gas turned off to prevent further liquid concentration.
  • Pressure safety features include direct pressure monitoring, pressure relief, and direct vent lines to channel high pressure vapor directly to scrubbed exhaust in case of overpressure conditions.
  • Leak safety features include a flood sensor to detect liquid leaks.
  • The system is ducted for exhaust ventilation to prevent HPG exposure in case of H2O2 liquid or gas leak. A ventilation pressure switch will trigger the interlock loop if ventilation is not adequate. A ppm HPG monitor is recommended in the exhaust ducting.
  • The drain line has a float switch to monitor for drain back up.
  • An optional condenser is available to condense HPG and water vapor before it goes to vent. Alternatively, scrubbers can be used to convert HPG directly to oxygen and water. 
To learn much more about the operating principles and process demonstration results from the HPG technology you can download a paper here: „Hydrogen Peroxide Gas Delivery for Atomic Layer Deposition, Annealing, and Surface Cleaning in Semiconductor Processing“, By Jeffrey Spiegelman, Russ Holmes and Zohreh Shamsi [Link] 
Dan Alvarez, CTO of RASIRC, will be presenting a poster entitled „Hydrogen peroxide gas for improved nucleation and initiation in ALD“ at The 16th International Conference on Atomic Layer Deposition (ALD 2016). He will also be presenting a paper entitled „Novel anhydrous hydrazine delivery for low temperature silicon nitride passivation of SiGe(110)“. RASIRC will also have an exhibit at stand 48. This will be a three-day meeting dedicated to the science and technology of atomic layer controlled deposition of thin films. The conference will take place on 24-27 July 2016 at the Convention Centre Dublin, Ireland. This is an excellent opportunity to meet Dan Alvarez and RASIRC founder and President Jeff Spiegelman to learn more about ther exciting HPG technology. 
Dan Alvarez CTO (left) and RASIRC founder and President Jeff Spiegelman (right).  

Refernces
[1] “2004 -The Year of 90-nm: A Review of 90 nm Devices”, Dick James, Chipworks Inc. Advanced Semiconductor Manufacturing Conference and Workshop, 2005 IEEE/SEMI, Munich, Germany.]
[2] ASMi Annual Reporting (2015)  

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