Monday, December 30, 2013

Selective Area Spatial Atomic Layer Deposition (SALD) by Kodak

Carolyn R. Ellinger and Shelby F. Nelson
Chem. Mater. January 30, 2014 (Web)
Spatial atomic layer deposition (SALD) is gaining traction in the thin film electronics field because of its ability to produce quality films at a fraction of the time typically associated with ALD processes. Here, we explore the process space for the fabrication of thin film patterned-by-printing electronics using the combination of SALD and selective area patterning. First, a study of SALD growth conditions for the three primary components of our metal oxide thin film electronics, namely alumina (Al2O3) dielectric, zinc oxide (ZnO) semiconductor, and aluminum doped ZnO (AZO) conductor, provides insight into the potential trade-offs in performance, substrate latitude (temperature), and process speed. At constant precursor partial pressures, the precursor exposure times and substrate temperatures were varied from 25 to 400 ms and from 100 to 300 °C, respectively. The very short gas exposure and purge times obtainable only with a spatial implementation of ALD are shown always to be advantageous for throughput and process speed, even though growth is far from the “ideal” ALD condition of saturated monolayer growth. Using the same range of process conditions, we evaluated the ability of very thin layers of poly(vinyl pyrrolidone) (PVP) to inhibit film growth. We demonstrate that PVP sufficiently inhibits the growth of all three materials at temperatures at or above 150 °C to usefully pattern high-quality electronic devices. Additionally, we found that very thin layers of PVP are most effective at higher temperatures and fast ALD cycles. Thus, faster SALD cycles are advantageous from both throughput and patterning performance perspectives.

Sunday, December 8, 2013

A CMOS-compatible and highly scalable approach to future ferroelectric memory

Even though researched for several decades, the ferroelectric fi eld effect transistor (FeFET) based on traditional perovskitebased ferroelectrics like PZT or SBT still has fundamental shortcomings. Its potential, however, remains unchallenged.

Like for DRAM, FRAM data storage depends on charge per area and therfore 3D scaling is a must. At IEDM 2006 (Koo et al, above) an attempt to scale FRAM in 3D was presented, as can be seen no charge gain per cell is made since no ferroelectric material (PZT of ferroelctric phase) is depoited on the sidewalls of the trench. In addition, the physical thickness of PZT limits the trench diameter.[1]

Unlike the current-based STT-MRAM, RRAM, PCRAM and Flash technologies the ferroelectric approach is based on a fi eld effect and consumes the lowest power during switching. Scalability and manufacturability on the other hand still remain a major issue when utilizing perovskite-based ferroelectrics.

TEM micrographs of the TiN/Si:HfO2/SiO2/Si gate stack and the complete FeFET device showing steep sidewall angles as a result of extensive RIE development.[2]

Recently however, a method to engineer ferroelectricity in the well-known and fully CMOS-compatible HfO2 based dielectrics was discovered. With this ability at hand a consortium of researchers from GLOBALFOUNDRIES, NaMLab gGmbH, and Fraunhofer IPMS-CNT were able to demonstrate that the two order of magnitude scaling gap, prevailing ever since the introduction of FeFETs, is fi nally closed at the 28 nm technology node. As indicated in Figure 1 the world´s most aggressively scaled FeFETs were successfully fabricated using ferroelectric Si:HfO2 in a 28 nm HKMG stack (TiN/Si:HfO2/SiO2/Si). Excellent 300 mm yield, switching in the nanosecond range, and 10-year retention were achieved with fi rst silicon. The consortium further demonstrated endurance characteristics matching demands of current NVMs utilizing wear leveling.

From VLSI 2012 presentation [2] - a comparasion of HfO2 based FeFET with previously published FeFET work based on PZT and similar materials. [presentation available thru Research Gate]
As prensented on IEDM 2013 by J. Müller et al, the implementation of FE-HfO2 into device structures similar to state of the art DRAM storage capacitors or HKMG transistors yields highly competitive 1T/1C and 1T FRAM solutions. Excellent retention and fast switching has been demonstrated. The improvement of the endurance characteristic of the material remains an open challenge for broadening the scope of potential memory applications. [1]

From IEDM 2013 abstratct [1] The prospects of FE-HfO2-based capacitors are contrasted to state of the art FRAM (table). STEM cross sections of an Al:HfO2–based trench capacitor array (#30k, 1.6 μm depth). P-E-Hysteresis reveal a stable Pr of 14 μC/cm2 (planar: 15 μC/cm2) in 3D-cpacitors enabling a Pr of 150 μC/cm2 in planar area projection.
[1] Ferroelectric Hafnium Oxide A CMOS-compatible and highly scalable approach to future ferroelectric memories
J. Müller, T.S. Böscke, S. Müller, E. Yurchuk, P. Polakowski, J. Paul, D. Martin, T. Schenk, K. Khullar, A. Kersch, W. Weinreich, S. Riedel, K. Seidel, A. Kumar, T.M. Arruda, S.V. Kalinin, T. Schlösser, R. Boschke, R. van Bentum, U. Schröder, T. Mikolajick
Proceedings of International Electron Devices Meeting 2013, (2013) 280-283

[2] Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG
J Müller, E Yurchuk, T Schlösser, J Paul, R Hoffmann, S Müller, D Martin, S Slesazeck, P Polakowski, J Sundqvist, M Czernohorsky, K Seidel, P Kücher, R Böschke, M Trentzsch, K Gebauer, U Schröder, T Mikolajick
Proceeding of Symposium on VLSI Technology (VLSIT) 2012; 06/2012

[post will be updated with more publications on this topic]