Monday, December 30, 2013

Selective Area Spatial Atomic Layer Deposition (SALD) by Kodak

Carolyn R. Ellinger and Shelby F. Nelson
Chem. Mater. January 30, 2014 (Web)
Spatial atomic layer deposition (SALD) is gaining traction in the thin film electronics field because of its ability to produce quality films at a fraction of the time typically associated with ALD processes. Here, we explore the process space for the fabrication of thin film patterned-by-printing electronics using the combination of SALD and selective area patterning. First, a study of SALD growth conditions for the three primary components of our metal oxide thin film electronics, namely alumina (Al2O3) dielectric, zinc oxide (ZnO) semiconductor, and aluminum doped ZnO (AZO) conductor, provides insight into the potential trade-offs in performance, substrate latitude (temperature), and process speed. At constant precursor partial pressures, the precursor exposure times and substrate temperatures were varied from 25 to 400 ms and from 100 to 300 °C, respectively. The very short gas exposure and purge times obtainable only with a spatial implementation of ALD are shown always to be advantageous for throughput and process speed, even though growth is far from the “ideal” ALD condition of saturated monolayer growth. Using the same range of process conditions, we evaluated the ability of very thin layers of poly(vinyl pyrrolidone) (PVP) to inhibit film growth. We demonstrate that PVP sufficiently inhibits the growth of all three materials at temperatures at or above 150 °C to usefully pattern high-quality electronic devices. Additionally, we found that very thin layers of PVP are most effective at higher temperatures and fast ALD cycles. Thus, faster SALD cycles are advantageous from both throughput and patterning performance perspectives.

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