Monday, February 10, 2025

AlixLabs Demonstrates 3 nanometers on Intel Silicon – Without EUV

The Swedish semiconductor company has fabricated leading-edge structures without using complex and costly lithography techniques.

The Swedish semiconductor company AlixLabs announces that it has used its technology to etch structures equivalent to commercial 3-nanometer circuits on Intel test silicon. Notably, this has been achieved without the use of extreme ultraviolet lithography (EUV) or advanced multi-patterning techniques such as SADP and SAQP (Self-Aligned Double Patterning and Self-Aligned Quad Patterning, respectively).


AlixLabs, a startup based in Lund, specializes in the development of Atomic Layer Etching (ALE), a type of plasma-based dry etching for cutting-edge structures, and ALE Pitch Splitting (APS), which enables transistor fins to be split using etching. The advantage of this approach is that it significantly reduces costs at the cutting edge, where wafer prices skyrocket with each new generation.

"We are pleased to demonstrate how APS can help the industry reduce its dependence on multi-patterning while lowering costs and environmental impact. Our technology enables the fabrication of sub-10-nanometer structures on silicon, and through Intel’s Test Vehicle Program, we have proven that sub-5-nanometer structures can be achieved using etching alone."
– Dmitry Suyatin, CTO and Co-Founder of AlixLabs

According to Dmitry Suyatin, AlixLabs’ CTO, this demonstration was made possible through Intel’s Test Vehicle Program, which provided test silicon for AlixLabs to process with its APS technology. While ALE has traditionally been limited to structures in the 10-nanometer class, AlixLabs' APS technique has significantly simplified the manufacturing of structures smaller than 5 nanometers.

Etching 3-nanometer-class structures without advanced EUV lithography, using only immersion lithography, is a significant breakthrough—provided the technology can be scaled and applied in practical manufacturing. AlixLabs has previously stated its goal of seeing its technology adopted by TSMC and Samsung for their 2-nanometer processes.


Since the industry moved past the 28-nanometer node, multi-patterning has become increasingly necessary to create smaller structures and transistors. This lithographic technique involves breaking down complex patterns into simpler ones and sequentially patterning them onto the silicon wafer for higher precision and detail. Lithography can perform this in two, three, or four steps (SADP, SAQP), though more steps are theoretically possible, they are considered too complex and costly for practical use at smaller nodes.

"APS technology demonstrates that complex multi-patterning techniques such as SADP and SAQP are not needed to manufacture circuits at 5 nanometers and below. This increases the potential to use immersion lithography for critical mask layers in 3-nanometer processes. These results were achieved with our early Alpha equipment, and Beta equipment will follow later in 2025. We thank Intel for enabling this demonstration and providing high-quality test silicon."
– Jonas Sundqvist, CEO and Co-Founder of AlixLabs

While lithographic multi-patterning is often necessary, it comes with several downsides. Each additional step requires more masks, which must be precisely aligned to form the final, complex pattern. Even a slight misalignment can lower yield and performance, but more importantly, it significantly extends production time. Avoiding multi-patterning whenever possible is therefore always preferable.

It is essential to distinguish between "nanometer-class" structures and actual physical nanometer measurements. What AlixLabs has achieved is a metal pitch (the distance between metal interconnects connecting transistor gates) of 25 nanometers through dry etching. This compares to TSMC’s most advanced 3-nanometer process, which achieves a metal pitch as low as 23 nanometers in certain high-density configurations.

AlixLabs highlights this test silicon as a major milestone towards commercialization and announces that more updates will follow later in 2025. Additional details will be presented by CTO Dmitry Suyatin at SPIE Advanced Lithography + Patterning in San Jose, California, on February 27, from 9:00–9:20 AM (local time).

Sources:

AlixLabs demonsterar 3 nanometer på Intel-kisel – utan EUV – Semi14

AlixLabs to Showcase Latest APS™ Findings at SPIE Advanced Lithography + Patterning – AlixLabs

Browse the 2025 program for SPIE Advanced Lithography + Patterning


Friday, February 7, 2025

JSR Expands Global Semiconductor Material Capabilities with New Photoresist Facilities, Advanced MOR Variants, and Strategic Acquisition of CVD/ALD Precursor Firm

JSR Corporation is expanding its global development and production of advanced photoresists by establishing a new R&D center in Japan and constructing a semiconductor photoresist plant in Korea. Since acquiring Inpria Corporation in 2021, JSR has been commercializing Metal Oxide Resist (MOR) for EUV lithography. The new R&D center in Japan’s Kanto region will enhance collaboration with global customers and partners, while the Korean plant, expected to begin operations in 2026, will handle the final production process for MOR to support local adoption. JSR aims to drive innovation in photoresists and help customers establish commercial production processes worldwide.

JSR's MOR, developed through its 2021 acquisition of Inpria Corporation, is a next-generation photoresist designed for EUV lithography. MOR is based on metal oxide nanoparticles, offering superior etch resistance and improved pattern resolution compared to traditional chemically amplified resists (CARs). This allows for finer feature definition and reduced line-edge roughness, critical for advanced semiconductor manufacturing below 10 nm. JSR has been scaling MOR for commercial adoption, with major semiconductor manufacturers evaluating its use in high-volume production. The company is expanding its R&D and manufacturing capacity, including a new R&D center in Japan and a production facility in Korea, to support global adoption of MOR.



JSR have investigated different flavors of MOR for EUV lithography, primarily focusing on variations in metal cores and process optimizations. Initially, zirconium (Zr) and hafnium (Hf) based MORs were explored, but their relatively low EUV absorption led researchers to investigate alternative metal cores such as titanium (Ti), zinc (Zn), indium (In), and tin (Sn). These new metal cores exhibited improved lithographic performance, achieving higher EUV absorption, smaller particle size, and better scum reduction. Additionally, process optimizations such as using higher dissolution rate photoacid generators (PAGs), new organic solvent developers, and lower soft bake temperatures were tested to improve scum removal and resolution. The new metal core variants demonstrated resolutions down to 13 nm with reduced defects, suggesting their potential for advanced semiconductor manufacturing.

In August 2024, JSR Corporation completed the acquisition of Yamanaka Hutech Corporation (YHC), a Kyoto-based manufacturer specializing in high-purity chemicals for semiconductor manufacturing. This strategic move allows JSR to expand its product portfolio to include Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) precursors, which are essential for forming advanced and complex semiconductor device structures. YHC, established in 1960, has over 60 years of experience in advanced molecular design, synthesis technology, and quality control systems, supplying high-quality CVD/ALD precursors to leading-edge semiconductor device manufacturers. The acquisition aligns with JSR's strategy to strengthen its position as a global supplier of semiconductor materials, enhancing its capabilities in both miniaturization and device structure innovation.

Sources:

JSR Expands Global Development and Production Functions for Leading-Edge Photoresists | 2024 | News | JSR Corporation

tec125-4.pdf

High-Precision ALD and Etching Techniques Enable Sub-1nm EOT in Monolayer MoS₂ Transistors

Researchers from Stanford University and Yonsei University have investigated the role of silicon seed layers in enabling high-quality atomic layer deposition (ALD) of HfO₂ on monolayer MoS₂, achieving sub-nanometer equivalent oxide thickness (EOT) and precise threshold voltage control.

Researchers developed a method to achieve sub-1 nm equivalent oxide thickness (EOT) in monolayer MoS2 transistors using atomic layer deposition (ALD) of HfO2 with a silicon seed layer, enabling improved threshold voltage control and low hysteresis. They investigated six seed layer candidates (Si, Ge, Hf, La, Gd, Al2O3) and found that only Si and Ge preserved the integrity of MoS2. The Si seed provided the best interface, allowing for the fabrication of normally-off transistors with a well-behaved threshold voltage. The resulting devices demonstrated a low EOT of approximately 0.9 nm, minimal leakage current (<0.6 μA/cm²), and a subthreshold swing of ~80 mV/dec at room temperature. This method offers a simple and accessible approach to depositing high-quality top-gate dielectrics in common nanofabrication facilities.


The manufacturing process of monolayer MoS2 transistors in the study involves several key steps, including atomic layer deposition (ALD) and etching processes:

  1. MoS2 Growth and Device Preparation: Monolayer MoS2 is synthesized using chemical vapor deposition (CVD) at 750°C on a SiO2 (90 nm) / p++ Si substrate. Alignment markers are deposited, and large contact pads (SiO2/Ti/Pd) are patterned and lifted off.

  2. Channel Patterning and Etching: The transistor channels are defined via electron-beam lithography and etched using xenon difluoride (XeF2) chemistry. Gold source and drain contacts are then deposited using electron-beam evaporation.

  3. Seed Layer Deposition: For the top-gate structure, ultrathin Si and Ge seed layers (~1 nm) are deposited using e-beam evaporation under high vacuum (~10⁻⁷ Torr). These seed layers are exposed to air before undergoing characterization via Raman and XPS measurements.

  4. Atomic Layer Deposition (ALD) of HfO₂: The Si or Ge-seeded samples are placed in the ALD chamber at 200°C for 30 minutes before initiating the deposition process. HfO₂ is grown using tetrakis(dimethylamido)hafnium (TDMAH) and H₂O as precursors at 200°C. The ultrathin Si seed oxidizes into SiOx, forming a high-quality interface for dielectric growth.

  5. Top-Gate Metallization and Etching: The Pd top gate is patterned and deposited using e-beam evaporation. To expose the contact pads for probing, the top-gate oxide is selectively removed using inductively coupled plasma (ICP) etching with CF₄.

  6. Annealing: The top-gated devices undergo vacuum annealing at 150°C, while back-gated devices without top gates are annealed at 250°C for two hours to remove moisture and stabilize electrical characteristics.

This process enables the formation of high-quality MoS₂ transistors with sub-1 nm equivalent oxide thickness (EOT), low leakage, and precise threshold voltage control.



Sources:

Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS2 Transistors | Nano Letters

nl4c01775_si_001.pdf

Thursday, February 6, 2025

Accuron Acquires Trymax to Strengthen Plasma Etch Equipment Portfolio and Expand Global Reach

Accuron Technologies has acquired a controlling interest in Trymax Semiconductor Equipment, a specialist in plasma-based and UV-based process equipment for semiconductor manufacturing. This acquisition strengthens Accuron’s presence in the semiconductor equipment sector and enhances its portfolio in the Etch & Clean process segment. Trymax, headquartered in the Netherlands, will continue to be led by its existing management team, ensuring continuity and execution of its expansion strategy. With Accuron’s resources and network, Trymax aims to accelerate its growth, broaden its customer base, and enhance product development. This move marks a strategic step for both companies, leveraging synergies to drive innovation and global expansion in semiconductor manufacturing solutions.


Sources:

 

Wednesday, February 5, 2025

TU Eindhoven and LONGi Advance ALD ZnO Passivating Contacts, Achieving 24.3 Percent Efficiency in Silicon Solar Cells

Atomic layer deposition of ZnO for contact passivation in silicon solar cells has emerged as a promising alternative to TOPCon technology, with the recent breakthrough of zinc oxide passivating contacts achieving 24.3 percent efficiency in a LONGi solar cell. This development builds on research led by Bart Macco’s group at Eindhoven University of Technology, which pioneered the concept of ZnO passivating contacts. The breakthrough was further demonstrated by LONGi, which successfully integrated the technology into high-efficiency solar cells.


Key advancements include the use of an interfacial SiO2 layer for passivation, Al2O3 capping to retain hydrogen during annealing, and selective Al2O3 removal to enable electrical contact while preserving passivation. The integration of a low-work-function LiF layer has improved contact resistivity, reducing the need for heavy silicon doping.

ALD ZnO offers lower-temperature processing, thinner layers around five nanometers, and elimination of toxic dopants compared to doped poly-Si in TOPCon. With potential advantages in scalability, industrial feasibility, and initial efficiency gains, ZOPCon could surpass TOPCon, though further research is needed to enable bifacial designs, optimize lateral conductivity, and enhance stability for large-scale production.


Sources

Passivating Contacts for Silicon Solar Cells: A Zinc Oxide Breakthrough? – Atomic Limits

Tuesday, February 4, 2025

Jusung Engineering Records Strong Financial Performance and Expands ALD Equipment Shipments in 2024

Jusung Engineering Ltd. (KOSDAQ:036930) maintains a strong financial position with a net cash balance of ₩187.2 billion, as its cash reserves of ₩232.2 billion significantly exceed its ₩45.0 billion in debt. Despite total liabilities exceeding cash and receivables by ₩109.4 billion, the company's market capitalization of ₩1.37 trillion suggests that these obligations do not pose a substantial risk. Jusung Engineering's EBIT grew by an impressive 211% over the past year, further strengthening its ability to manage debt. Additionally, with free cash flow amounting to 80% of EBIT over the last three years, the company demonstrates solid cash flow management, reducing concerns over its debt burden. Given these factors, Jusung Engineering appears financially stable, with strong earnings and liquidity to support future growth.


Jusung Engineering shipped atomic layer deposition equipment for DTC silicon capacitor production on the 17th of last month.

In May 2024, Jusung Engineering unveiled plans to restructure its business by spinning off its semiconductor, solar, and display divisions into separate entities. The strategic move aimed to enhance operational efficiency and create greater shareholder value. However, by October 2024, the company decided to cancel the spin-off due to opposition from shareholders. The total stock purchase price for the stocks exercised in opposition exceeded KRW 50 billion, leading to the decision to maintain the company's current structure.

Beyond its financial success, Jusung Engineering made notable advancements in its technology offerings. In November 2024, the company shipped Atomic Layer Deposition (ALD) equipment for the production of Deep Trench Capacitor (DTC) Silicon Capacitors to Elspeth. 

Jusung Engineering's strong financial results, strategic decisions, and technological advancements reinforce its position as a key player in the global semiconductor industry. 

References:
https://www.mk.co.kr/en/business/11231493
https://www.businesskorea.co.kr/news/articleView.html?idxno=216376
https://www.marketscreener.com/quote/stock/JUSUNG-ENGINEERING-CO-LTD-6494704/news/JUSUNG-ENGINEERING-Co-Ltd-cancelled-the-Spin-Off-of-Semiconductor-equipment-research-and-developme-48189649/
https://www.mk.co.kr/en/business/11164246

Friday, January 31, 2025

Forge Nano Expands ALD Capabilities with New TEPHRA™ Cluster Tool and State-of-the-Art Cleanroom

Forge Nano has significantly expanded its semiconductor atomic layer deposition (ALD) capabilities with the completion of a new 2,000 sq ft cleanroom dedicated to manufacturing its TEPHRA™ ALD cluster tools. This expansion comes in response to increased demand for high-throughput ALD solutions in the 200mm wafer market, particularly for advanced packaging, power semiconductor, and microelectromechanical system (MEMS) applications. The new facility, featuring Class 10 (ISO 4) cleanroom space and a dedicated metrology lab, will enable Forge Nano to accelerate production, conduct customer demonstrations, and validate ALD process integration for commercial-scale adoption.



The TEPHRA™ cluster tool is designed to deliver ultrathin, uniform coatings with 10x the throughput of traditional ALD systems, supporting applications such as conformal metal barrier seed layers for through-silicon and through-glass vias (TSVs and TGVs). With customer tool deliveries expected in early 2025, Forge Nano is inviting industry partners to on-site demonstrations showcasing TEPHRA’s capabilities. This expansion reinforces Forge Nano’s position as a key enabler of next-generation semiconductor manufacturing, offering efficient and scalable ALD solutions for the growing demand in advanced node technologies.

Sources:

Thursday, January 30, 2025

Lam Research’s Dry Resist: A Breakthrough in EUV Lithography for Next-Generation Logic and Memory Manufacturing

Lam Research’s dry resist technology represents a major shift in EUV lithography and semiconductor patterning, addressing critical challenges such as stochastic defectivity, resolution limitations, and cost-efficiency. With recent qualifications for advanced DRAM and 2nm logic manufacturing, along with a growing ecosystem for high-volume production, dry resist is positioned to disrupt traditional chemically amplified resists (CARs) and enable future High-NA EUV adoption.

One of the most significant recent developments is Lam’s qualification of dry resist for 28nm pitch BEOL logic at 2nm and below in collaboration with imec. This qualification confirms that dry resist can eliminate multi-patterning steps, reducing complexity and improving EUV throughput. The process is designed to work with both low-NA and high-NA EUV scanners, ensuring its relevance for sub-2nm logic scaling. This represents a key milestone in extending direct EUV printing to future logic nodes, an approach that could significantly lower lithography costs while improving pattern fidelity.


In addition, a leading DRAM manufacturer has selected Lam’s Aether dry resist technology as its production tool of record for advanced DRAM nodes. This decision highlights dry resist’s low-defect, high-fidelity patterning capabilities, which are essential for scaling memory architectures. The technology enables lower exposure doses while reducing stochastic defects, which are a major concern in EUV-based DRAM production. Given that Samsung, SK Hynix, and Micron are all increasing their reliance on EUV for next-generation DRAM, Lam’s dry resist is well-positioned for widespread adoption in the memory sector.


To ensure a stable supply chain for dry resist materials, Lam Research has partnered with Entegris and Gelest, a Mitsubishi Chemical Group company. This collaboration ensures reliable dual-source precursor production, providing chipmakers with long-term process stability. The partnership also focuses on the development of next-generation high-NA EUV precursors, further strengthening dry resist’s role in future sub-2nm manufacturing.


SEM images of 28 nm pitch line/space patterns imaged with 0.33NA EUV in dry resist from Entegris precursor.

A critical enabler of dry resist technology is its atomic layer deposition (ALD) process, which replaces traditional spin-coating used in CARs. ALD-based vapor-phase deposition offers higher uniformity, eliminating polymer chain variations found in conventional resists. It also allows precise thickness control, which is essential for optimizing EUV photon absorption and etch selectivity. Unlike CARs, which rely on a complex mixture of polymers, dry resist materials are based on single-component metal-organic precursors such as organo-tin oxides. These materials provide higher EUV photon absorption, improving sensitivity and pattern resolution.

Another key advantage of dry resist is its anisotropic dry development process, which replaces wet solvent-based development. Traditional CAR-based EUV resists require organic solvents or aqueous bases, leading to stochastic defects, material loss, and waste. Dry resist, by contrast, is developed entirely in the gas phase, selectively removing unexposed regions and forming a negative-tone image. This eliminates line collapse and delamination issues, improving yield stability. Additionally, the elimination of wet chemistries significantly reduces chemical waste, making dry resist a more sustainable solution with five to ten times lower material consumption compared to traditional resists.

Lam’s dry resist technology is poised to disrupt traditional CAR-based EUV lithography, particularly as the industry moves toward High-NA EUV adoption. By reducing multi-patterning dependency, the technology enhances cost-effective EUV scaling, making it an attractive solution for both logic and memory manufacturers. This positions Lam as a key leader in next-generation EUV resist solutions, challenging conventional resist suppliers like JSR, TOK, and Inpria.

From a sustainability perspective, dry resist significantly lowers EUV exposure dose requirements, leading to higher scanner throughput and lower energy consumption. Its reduced defectivity translates to higher yield per wafer, further enhancing cost-efficiency. The collaboration with Entegris and Gelest ensures supply-chain stability, making dry resist a viable and scalable technology for sub-2nm nodes.

The patent US20220020584A1 mentions several Lam Research tools that play a role in the dry resist deposition, patterning, and development process for EUV lithography. The Altus system is referenced for deposition, likely for metal or dielectric films in the dry resist stack, while the Striker plasma-enhanced atomic layer deposition (PEALD) system may be used for precise resist or underlayer deposition. The Versys platform, known for plasma processing, is relevant to the dry development process, and the Syndion system, typically used for deep silicon etching, may have applications in pattern transfer. Additionally, the Reliant tool is designed for volume manufacturing, possibly adapted for integrating dry resist technology, and the Kiyo plasma etch system is likely involved in etching after the dry resist development stage. These tools collectively enable Lam’s dry resist process to achieve improved resolution, defect reduction, and cost efficiency in advanced EUV lithography.

The patent US20220020584A1, filed by Lam Research Corporation, describes an innovative dry development process for EUV photoresists, which eliminates the need for traditional wet chemical development methods. The patent details a dry resist system deposited via vapor-phase precursors, forming a highly uniform, single-component material that enhances EUV photon absorption and sensitivity. The dry development process selectively removes unexposed resist regions using plasma-based or plasma-free chemical methods, significantly reducing line collapse and defectivity while improving resolution at sub-2nm nodes. By integrating dry resist deposition, EUV exposure, and dry development into a single cluster tool, the patented technology enables scalable, high-volume EUV manufacturing with lower chemical consumption and improved process sustainability, positioning it as a key enabler for High-NA EUV lithography.

Lam Research’s dry resist technology represents a significant development in EUV lithography by addressing key challenges in stochastic defectivity, process cost, and sustainability. Its qualification for 2nm logic and advanced DRAM manufacturing confirms its readiness for high-volume production. By utilizing ALD for precise resist deposition and securing a stable precursor supply through partnerships with Entegris and Gelest, Lam has established a strong foundation for scaling the technology. 

Sources:

Lam Research Press Release on DRAM Adoption (Jan 2025): Lam Research
imec Qualification of Dry Resist for 2nm Logic (Jan 2025): imec
Entegris and Gelest Collaboration Announcement (July 2022): Entegris
Overview of Dry Resist ALD and Precursor Chemistry: SemiAnalysis
ASML High-NA EUV Roadmap and Implications for Dry Resist: ASML
Lam Reserach patent application US20220020584A1: US20220020584A1.pdf


Saturday, January 18, 2025

Revolutionizing Silicon Photonics: First Electrically Pumped Group IV Laser Achieved for Seamless Integration on Silicon Chips

Researchers have achieved a groundbreaking milestone in silicon photonics by developing the first electrically pumped Group IV laser, made from silicon-germanium-tin layers directly grown on silicon wafers. This innovation paves the way for cost-effective, energy-efficient photonic integrated circuits in next-gen silicon chips.


The breakthrough in silicon photonics achieved by an international research team marks a transformative step in the materials and manufacturability of photonic devices. By developing the first electrically pumped continuous-wave laser made entirely of Group IV materials—silicon, germanium, and tin—the researchers overcame a long-standing challenge in integrating efficient light sources directly into silicon-based technologies. This laser is built using ultrathin layers of silicon-germanium-tin and germanium-tin, grown directly on silicon wafers. Its compatibility with conventional CMOS processes promises seamless integration into existing silicon manufacturing workflows, reducing costs and enhancing scalability. Unlike traditional lasers based on III-V materials, which are costly and complex to integrate with silicon, this innovation makes use of widely available Group IV elements, providing an energy-efficient and manufacturable solution for on-chip photonics.

This laser not only operates with a low current of 5 milliamperes at 2 volts but also features a sophisticated multi-quantum well structure and ring geometry to minimize power consumption and heat generation. Though the device currently functions at cryogenic temperatures, its development path mirrors earlier advancements in germanium-tin lasers that achieved room-temperature operation within a few years. The laser’s manufacturability is further underscored by its growth on standard silicon wafers, aligning with industry-standard processes. This achievement is poised to catalyze the adoption of low-cost photonic integrated circuits (PICs) in microchips, meeting the growing demand for energy-efficient hardware in AI and IoT applications while paving the way for advances in optical data transmission and next-generation silicon photonics.

Sources:

Silicon Photonics Breakthrough: The “Last Missing Piece” Now a Reality

Friday, January 17, 2025

3D Vertical Ferroelectric Capacitors for Memory Scaling

3D vertical ferroelectric capacitors are revolutionizing memory technology, offering higher density and performance by leveraging vertical structures to overcome planar scaling limits. Using aluminum-doped hafnium oxide (Al:HfO₂), these capacitors achieve stable remnant charge, low voltage operation, and enhanced scalability, addressing advanced applications in AI and edge computing. Recent innovations, such as the TiN/Al:HfO₂/TiN configuration introduced by Dongguk University, South Korea, demonstrate improvements in endurance and integration. This progress builds on foundational work by Qimonda and Fraunhofer IPMS-CNT in Dresden Germany, including Tim Böscke's pioneering discovery of ferroelectricity in hafnium oxide and Johannes Müller's ALD advancements using ALD process developments FHR and ASM tools. These developments cement Al:HfO₂ as a DRAM and CMOS-compatible solution for next-generation non-volatile memory technologies.

3D vertical ferroelectric capacitors are transforming memory technology by providing higher density and performance in compact designs. Leveraging a vertical structure, they overcome planar scaling limits by using the third dimension to maximize storage capacity. Incorporating ferroelectric materials like aluminum-doped hafnium oxide (Al:HfO₂) enables these capacitors to achieve spontaneous polarization and stable remnant charge even at reduced dimensions. With features like low voltage, high-speed operation, and improved retention and endurance, they address critical challenges in advanced memory while remaining compatible with CMOS processes, facilitating their integration into existing manufacturing technologies. This innovation is key to meeting the demands of data-intensive applications such as AI and edge computing.

A recent study, 3D Vertical Ferroelectric Capacitors with Excellent Scalability (by Eunjin Lim et al Dongguk University, South Korea)), introduces a 3D vertical ferroelectric capacitor with a TiN/Al:HfO₂/TiN configuration. It employs a unique architecture with multiple small holes sharing a common pillar electrode, enhancing ferroelectric properties and scalability. Analyses using advanced microscopy confirm its structural integrity, while the device demonstrates high endurance, minimal variability, and excellent retention. This architecture also supports integration into one-transistor n-capacitor ferroelectric memory with vertical transistors.

Importantly, Earlier work by Fraunhofer IPMS-CNT, including the 2012 study Incipient Ferroelectricity in Al-Doped HfO₂ Thin Films, first demonstrated ferroelectric properties in HfO₂ thin films doped with aluminum. This research identified an antiferroelectric-to-ferroelectric phase transition, influenced by Al concentration and annealing conditions, and attributed ferroelectricity to a non-centrosymmetric orthorhombic phase (Pbc2₁). This foundational work highlighted the potential of Al:HfO₂ for applications in memory and sensing technologies.


The later paper High Endurance Strategies for Hafnium Oxide-Based Ferroelectric Field Effect Transistors further emphasized Al:HfO₂’s scalability and compatibility with CMOS technology. It explored strategies to improve endurance and reduce interfacial stress, including modifying interfacial materials and exploring MFS structures. These strategies balance performance, reliability, and scalability, supporting the broader adoption of ferroelectric memory.


In Johannes Müller's PhD thesis (2014, Fraunhofer IPMS-CNT), the Atomic Layer Deposition (ALD) processes for hafnium oxide (HfO₂) and aluminum-doped hafnium oxide (Al:HfO₂) utilized advanced deposition equipment to achieve precise doping and phase control. The processes were performed using a 300 mm FHR ALD 300 and an ASM PULSAR 3000®, both of which are designed for high-uniformity deposition on large substrates, such as 300 mm wafers. These tools facilitated the use of tetrakis(ethylmethylamino)hafnium (TEMAHf) and trimethylaluminum (TMA) as precursors for hafnium and aluminum, respectively, along with oxidants like water or ozone. By tailoring precursor ratios, deposition temperatures, and annealing conditions, the processes ensured the stabilization of the orthorhombic Pbc2₁ phase, critical for the ferroelectric properties of Al:HfO₂ films. These advancements highlight the scalability and compatibility of ALD-fabricated Al:HfO₂ films with CMOS technology.


Semiconductor Cleanroom Tools: Introducing ASM Eagle XP4 for ALD | Fraunhofer IPMS


Historic picture of the FHR ALD 300 mm tool, at the previous location of Fraunhofer IPMS-CNT. The FHR cluster was co-developed by Qimonda and Fraunhofer CNT and teh original discovery of ferroelectric hafnium oxide was by Qimonda and a PhD Student from TU Dresden, Tim Böscke. His groundbreaking work, published in 2011, demonstrated the ferroelectric properties of silicon-doped hafnium oxide (Si:HfO₂), marking a major milestone in the development of CMOS-compatible ferroelectric materials. This discovery laid the foundation for integrating ferroelectric properties into hafnium oxide-based systems, revolutionizing non-volatile memory technologies

The patent US 2009/0057737 A1, authored by Tim Böscke et al., describes a method for fabricating integrated circuits with a dielectric layer that exhibits enhanced properties, such as high dielectric constants and ferroelectricity. The process involves forming a preliminary dielectric layer, such as hafnium oxide or doped hafnium oxide (e.g., aluminum- or silicon-doped), using techniques like Atomic Layer Deposition (ALD). The dielectric layer is initially amorphous and undergoes a phase transition to a crystalline state upon heating above its crystallization temperature. The method includes precise doping of the dielectric layer to stabilize desirable phases, such as orthorhombic or tetragonal, which are essential for achieving ferroelectricity. A covering layer, often a conductive electrode material, is deposited before annealing to assist in crystallization and enhance material properties. The innovations outlined aim to improve memory applications, such as capacitors and transistors, by offering higher storage densities, lower leakage currents, and compatibility with advanced CMOS processes. This patent is foundational in the development of ferroelectric hafnium oxide-based technologies.

Sources:

Saturday, January 11, 2025

Integrating Metal-Oxide EUV Resists with Directed Self-Assembly for High-Resolution Chemical Patterning

Extreme ultraviolet (EUV) lithography struggles with resist materials that can deliver both high resolution and acceptable throughput, often resulting in rough patterns and printing defects that degrade semiconductor performance. To overcome this, researchers are exploring directed self-assembly (DSA) of block copolymers (BCPs), which can naturally rectify pattern defects when aligned to EUV-defined chemical guides. However, metal-oxide EUV resists (MORs), which provide high resolution, face challenges in converting their patterns into effective chemical guides for DSA integration.

This study presents a novel method using hydrogen silsesquioxane (HSQ), a negative tone resist, to create chemical patterns for integrating MORs with DSA. The process involves forming a sacrificial chromium pattern from HSQ, which is later replaced with a polyethylene oxide brush layer and a nonpolar polystyrene brush. These steps allow the successful assembly of polystyrene-block-poly(methyl methacrylate) BCPs, achieving 24 nm full-pitch resolution. This approach shows potential for producing sub-10 nm patterns by combining high-χ BCPs with MOR-based EUV lithography, advancing next-generation semiconductor fabrication.


DSA of BCPs is a promising nanofabrication technique that utilizes the phase separation properties of BCPs to create highly ordered nanoscale patterns with feature sizes below 10 nm. In DSA, BCPs self-organize into distinct microdomains, forming well-defined structures that can be guided using chemoepitaxy or graphoepitaxy. Chemoepitaxy involves chemically patterned surfaces that influence the alignment and orientation of BCP domains, while graphoepitaxy uses topographical features to achieve similar control. High-χ (chi) BCPs are often used to achieve finer pattern resolutions, and material optimizations such as selecting appropriate substrates and brush layers are crucial to improving pattern quality and reducing defects. DSA has been explored for various semiconductor applications, including the creation of dense line-space arrays, hole shrink patterns, and advanced memory devices, offering significant potential to enhance pattern fidelity, reduce defectivity, and lower manufacturing costs.

Sources:

High-resolution chemical patterns from negative tone resists for the integration of extreme ultraviolet patterns of metal-oxide resists with directed self-assembly of block copolymers | Journal of Vacuum Science & Technology B | AIP Publishing

https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12956/3010817/Material-and-process-optimization-for-EUV-pattern-rectification-by-DSA/10.1117/12.3010817.full


https://journals.spiedigitallibrary.org/conference-proceedings-of-spie/12497/124970K/EUV-lithography-line-space-pattern-rectification-using-block-copolymer-directed/10.1117/12.2657990.full
https://www.mdpi.com/2073-4360/12/10/2432


https://www.spiedigitallibrary.org/conference-proceedings-of-spie/PC12054/PC1205402/Exploring-the-synergy-between-EUV-lithography-and-directed-self-assembly/10.1117/12.2622565.full
https://journals.aps.org/prb/abstract/10.1103/PhysRevB.101.085407

Friday, January 10, 2025

Game-Changing ALD Breakthrough: KJLC Achieves First Scandium Nitride PEALD Process

Revolutionizing Atomic Layer Deposition: Kurt J. Lesker Company's Groundbreaking ALD Publication
January 08, 2025 | By KJLC Innovate 

In the ever-evolving world of semiconductor technology, innovation is the key to staying ahead. At Kurt J. Lesker Company, we are proud to announce a groundbreaking achievement that promises to revolutionize the field of Atomic Layer Deposition (ALD). Our latest publication, featuring the patented Precursor Focusing Technique (PFT) and Ultra-High Purity (UHP) process capability, marks a significant milestone in our commitment to advancing next-generation applications.


The First of Its Kind: Scandium Nitride by PEALD

For the first time, scandium nitride (ScN) has been successfully deposited using plasma-enhanced atomic layer deposition (PEALD) on silicon, sapphire, and magnesium oxide substrates under UHP conditions. This innovative process utilizes a new scandium precursor, bis(ethylcyclopentadienyl)scandium-chloride [ClSc(EtCp)2], combined with N2-H2 plasma species, allowing for the deposition of high-quality ScN films at relatively low temperatures (200−300°C).


Why This Publication is a Game-Changer

The significance of this publication lies in its potential to transform various advanced electronic applications. The ScN films produced by this process exhibit high crystalline quality and excellent electrical properties, with high mobility and low resistivity. These characteristics make them suitable for a wide range of applications, including thermoelectric devices and as an interlayer for epitaxial gallium nitride (GaN) growth.

Moreover, the ability to conformally coat high aspect ratio (HAR) structures is particularly valuable for applications in 3D embedded memory and piezoelectric microelectromechanical systems (piezoMEMS). Traditional sputtering techniques are not suitable for these applications involving complex 3D architectures, making this new ALD process a significant advancement.


The Commercial Relevance of ScN

Scandium nitride is commercially relevant primarily because it forms a solid solution with aluminum nitride (AlN), resulting in aluminum scandium nitride (Al1-xScxN), which enables ferroelectric switching. Al1-xScxN thin films are traditionally deposited via reactive magnetron sputtering, which yields highly c-axis oriented columnar grains. However, sputtering is not suitable for coating high-aspect ratio (HAR), vertically layered structures such as those desired for use in 3D embedded memory.

Recently, there have been several reports of piezoelectric AlN grown by atomic layer deposition (ALD) techniques that have shown promising crystalline quality and properties. However, there are no reports of ALD Al1-xScxN, principally because there are no reported ALD processes for ScN. This publication addresses this gap, providing a new method for depositing high-quality ScN films.
Looking Ahead

As KJLC continues to push the boundaries of ALD technology, we are excited about the possibilities our new research and development opens up. From thermoelectrics to applications involving high-aspect ratio (HAR) architectures such as 3D embedded memory and piezoMEMS technology, the high crystalline and electrical quality demonstrated here for ScN by PEALD techniques is just the beginning.

Sources:








Wednesday, January 8, 2025

SEMI World Fab Forecast Highlights Strong Fab Investments and New Fabs in 2025

The latest World Fab Forecast by SEMI, published on December 19, 2024, highlights strong growth in global semiconductor manufacturing from 2023 to 2025. Key takeaways from the report include increased investments in fab equipment and capacity expansions across both memory and foundry segments, indicating a resilient and growing industry.


SEMI’s latest World Fab Forecast report reveals that 18 new semiconductor fabs will begin construction in 2025, including three 200mm and fifteen 300mm facilities, primarily in the Americas, Japan, China, and Europe. These projects, set to start operations between 2026 and 2027, reflect the industry's focus on advanced nodes for AI and high-performance computing (HPC). Total semiconductor capacity is expected to grow at a 6.6% annual rate, driven by leading-edge logic technologies, while mainstream and mature nodes continue to support automotive, IoT, and power applications. Foundries remain key drivers of capacity growth, with generative AI demand boosting memory markets, particularly high-bandwidth memory (HBM). [Semiconductor Digest, LINK below]

For 2024, global fab equipment spending is projected to rise by 8% year-over-year to approximately 111 billion dollars, surpassing previous projections. The foundry segment is expected to account for 59 billion dollars of this investment, marking a 2% increase from 2023. The memory segment is set to see the most significant growth, with spending projected to jump by 50% to 34 billion dollars. This surge in memory investments reflects a rebound from the recent downturn and aligns with rising demand for advanced semiconductor technologies.

Looking ahead to 2025, fab equipment spending is expected to grow by an additional 4%, reaching approximately 116 billion dollars. The foundry segment will likely invest around 65 billion dollars, while the memory segment is forecasted to maintain robust spending at 33 billion dollars.

In terms of capacity expansion, the report predicts continued growth in both memory and foundry capacity. Memory capacity is expected to grow by 4% in 2024 and 3% in 2025, while foundry capacity, including pure-play foundries and IDM fabs, is projected to see 12% growth in 2024 and 11% in 2025. This reflects strong demand for advanced logic chips and specialty processes.

On the construction front, investments in new fab construction are expected to dip slightly in 2024, with a 5% decline to 39 billion dollars. However, SEMI anticipates 45 new construction projects for volume fabs, excluding R&D and pilot facilities, between 2025 and 2030. These projects are expected to support long-term demand growth across various segments, including AI chips, automotive semiconductors, and memory.

In 2025, the industry is expected to see the completion of several new fabs that are currently under construction. These new fabs will be crucial for meeting growing demand for advanced semiconductor technologies and are expected to bring significant additional capacity online. Many of these facilities will focus on next-generation nodes, particularly for applications in AI, high-performance computing, and automotive sectors. The report highlights that regions such as Taiwan, South Korea, and the US will see major investments in these new fabs, further strengthening their positions as key players in the global semiconductor supply chain.

Sources:

For more details, visit the official SEMI World Fab Forecast page:

Semiconductor Digest:

ALD for Industry | International Conference & Exhibition - March 11 - 12, 2025 | Dresden, Germany

ALD for Industry | International Conference & ExhibitionMarch 11 - 12, 2025 | Dresden, Germany
+++ Poster Submission, Early Bird Registration & Exhibition Booking +++
Deadline: January 31, 2025

Atomic Layer Deposition is an important technology for surface modification and structuring. Again we will discuss recent developents and applications of the technology in March in Dresden. Already 26 speakers confirmed their contributions. Check the first anounnced talks and use the earyl bird registration until January 31, 2025.



Also Poster Submissions and booking of exhibition places is possible until January 31, 2025. Present your services and products to the ALD Community and become visible to interested people.

More information you can find the the ALD Website: https://lnkd.in/eKt86GV7


Program Preview

We are pleased to announce first speakers of the upcoming event. A complete porgram will be published in January 2025Fundamentals of atomic layer deposition: a tutorial| Riikka Puurunen, Aalto University, Sweden

  • Industrial batch ALD for optical applications | Shuo Li, Afly Solution Oy, Finland
  • Direct Processing by µDALP™. Precision Coatings for Next Gen Devices | Maksym Plakhotnyuk, ATLANT 3D, Denmark
  • Nanoscale solid-state lithium-ion electrolytes enabled by atomic layer deposition | Messaoud Bedjaoui, CEA Leti, France
  • Fabrication of Surface Relief Gratings using ALD-based Technologies to Overcome the Challenges of Reactive Ion Etching of TiO2 | Mathias Franz, Fraunhofer ENAS, Germany
  • Monitoring and optimisation of ALD processes with Remote Plasma Optical Emission Spectroscopy | Erik Cox, Gencoa Ltd, UK
  • Optimizing Plasma-Assisted Atomic Layer Deposition using Impedans RFEAs | Angus McCarter, Impedans Ltd., UK
  • Improving atomic layer deposition process of silicon oxide (SiO2) and aluminum oxide (Al2O3) | Long Lei, Fraunhofer IMPS, Germany
  • Introducing a Surface Acoustic Wave-Based Miniaturized Aerosol Source for Controlled Liquid Precursor Delivery in ALD Processes | Mehrzad Roudini, Leibniz IFW, Germany
  • Challenges and Solutions in ALD of Thermal Budget Sensitive Ferroelectric Materials | Bart Vermeulen, Ferroelectric Memory Co GmbH, Germany
  • ALD for Nanoparticles: From Fundamentals to Industrial Applications | Rong Chen, University of Science and Technology HUST, China
  • Recent developments and emerging applications in atmospheric-pressure ALD on high-porosity membranes | Fred Roozeboom, University of Twente, Netherlands
  • Past, present and future of ALD from an industrial perspective | Jan Willem Maes, ASM, Belgium
  • Advanced in-situ QCM process monitoring | Martin Knaut, ALS Metrology UG, Germany
  • Cryogenic Atomic Layer Etching (Cryo-ALE) of low-k dielectrics like SiO2, and GaN etching. | Rémi Dussart, Université d´Orleans, France
  • ALD for Memory Applications: a matter of details | Laura Nyns, IMEC, Belgium
  • Spatial ALD of IrO2 and Pt films for green H2 production by PEM electrolysis | Paul Poodt, SparkNano B. V., The Netherlands
  • APECS Pilot Line – Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems | Wenke Weinreich, Fraunhofer IPMS, Germany
Program Committee
  • Sean Barry, Carleton University, Canada
  • Gloria Gottardi, Fondazione Bruno Kessler, Italy
  • Christoph Hossbach, Applied Materials / Picosun Europe, Germany
  • Martin Knaut, TU Dresden, Germany
  • Laura Nyns, IMEC, Belgium
  • Fred Roozeboom, University Twente, Netherlands
  • Jonas Sundqvist, Alixlabs, Sweden
POSTER Exhibition

The Poster Submission is open until January 31, 2025. Please send us an Abstract for your Poster Application. PO001 | Deposition of High Quality Aluminium Fluoride Layers through Optimization of a PEALD Process using Al(CH3)3 and SF6 | Fabian Steger, RhySearch, Buchs, Austria PO002 | Evaluating the Enhanced Fire Resistance of Polyamide Fabric through Dual-Layer Treatment with ALD-ZnO and DOPO-Based Silane | Sebastian Lehmann, Leibniz IFW, Germany

Surface Passivation: A Cornerstone for Advancing Semiconductor Technologies

Modern semiconductor devices like transistors, solar cells, microLEDs, and thin-film transistors all rely heavily on effective surface passivation to enhance performance. As devices continue to evolve toward 3D architectures and smaller form factors, managing surface defects becomes critical to maintaining efficiency. Surface passivation, achieved through thin films deposited by atomic layer deposition (ALD) or similar techniques, minimizes charge carrier recombination at surface sites, thereby boosting the overall performance of semiconductor devices. The latest review paper by Bart Macco, published in the Journal of Vacuum Science and Technology A, provides a comprehensive analysis of surface passivation techniques across silicon, germanium, and III–V materials. The study highlights the importance of atomic-scale processing methods, such as ALD and atomic layer etching (ALE), in meeting the demands of advanced semiconductor architectures. It also explores the emerging trends in high-volume manufacturing of ALD Al₂O₃ layers, novel passivation stacks tailored for different semiconductor materials, and the growing role of in-situ cleaning processes. This review underscores how advancements in passivation methods are shaping next-generation semiconductor devices, addressing both performance and reliability challenges. For more details, the paper is open access and licensed under Creative Commons Attribution and you can also check out the recent post in AtomicLimiuts.com (links below).




Sources: 
Macco, B., et al. "Surface passivation approaches for silicon, germanium, and III–V semiconductors." Journal of Vacuum Science and Technology A.: Surface passivation approaches for silicon, germanium, and III–V semiconductors | Journal of Vacuum Science & Technology A | AIP Publishing

Saturday, January 4, 2025

2025 Book - Emerging Atomic Layer Deposition for Hydrogen Energy

The book "Emerging Atomic Layer Deposition for Hydrogen Energy" highlights several key applications where Atomic Layer Deposition (ALD) will play a transformative role in advancing hydrogen energy systems. In hydrogen production, ALD is utilized to improve water-splitting catalysts, including both electrochemical and photoelectrochemical (PEC) methods. By coating electrodes with thin, uniform layers, ALD enhances the efficiency and stability of the catalytic process. ALD is also applied to photoelectrodes in solar-driven water splitting to improve light absorption, charge separation, and durability. Additionally, ALD is used to modify proton exchange membranes (PEMs), enhancing their chemical stability and proton conductivity in fuel cells and electrolyzers.



In hydrogen storage, ALD plays a significant role by coating hydrogen storage materials such as metal hydrides, preventing degradation and improving absorption-release cycles. It is also used to create nanostructured hydrogen storage systems, which increase surface area and improve hydrogen uptake capacity. In fuel cell technology, ALD is employed to create thin, dense electrolyte layers in solid oxide fuel cells (SOFCs) and to improve electrode interfaces, enhancing their long-term stability. For proton exchange membrane fuel cells (PEMFCs), ALD helps reduce the use of expensive platinum group metals (PGMs) by improving the performance and durability of non-PGM catalysts. Similarly, ALD enhances the efficiency of alkaline fuel cells by creating durable, high-performing catalyst layers.

ALD may be critical in improving the performance of catalysts and electrodes used in hydrogen energy systems. It enables the coating of non-precious metal catalysts, enhancing their activity and stability. ALD also provides protective layers on catalysts to prevent degradation in harsh chemical environments, ensuring longer device lifespans. In the development of gas diffusion electrodes (GDEs), ALD improves conductivity, hydrophobicity, and corrosion resistance, making them more efficient for fuel cell applications. Furthermore, ALD can be used to create defect-free membranes for hydrogen purification, which are essential for separating and purifying hydrogen in industrial processes.

Other notable applications include the use of ALD in hydrogen sensors, where thin films created by ALD increase the sensitivity and durability of sensing materials. ALD also plays a key role in corrosion protection for hydrogen infrastructure, such as pipelines and storage tanks, by providing thin, protective layers that resist chemical degradation. In solar-driven hydrogen production, ALD improves the stability and efficiency of photocatalysts and enhances the performance of light absorbers by adding anti-reflective and passivation layers. Additionally, ALD is being explored for use in hybrid energy systems that combine hydrogen storage with battery technologies, further demonstrating its versatility in hydrogen-related applications. Overall, ALD’s precise control over material properties makes it a critical enabling technology for advancing hydrogen energy solutions.

Source:
The authors of "Emerging Atomic Layer Deposition for Hydrogen Energy" are primarily affiliated with the University of Johannesburg, South Africa. Dr. Peter Ozaveshe Oviroh holds a PhD in Mechanical Engineering Science from the University of Johannesburg and focuses on advanced material synthesis and energy systems. Dr. Sunday Temitope Oyinbo is a Specially Appointed Researcher at Kyoto University of Advanced Science in Japan, with expertise in hydrogen energy and materials engineering. Dr. Sina Karimzadeh is a Postdoctoral Research Fellow at the University of Johannesburg, contributing to research on thin-film deposition and nanomaterials. Dr. Patrick Ehi Imoisili is a Senior Lecturer and Researcher at the same institution, specializing in materials science and renewable energy technologies. Professor Tien-Chien Jen, also affiliated with the University of Johannesburg, is an accomplished academic recognized as an ASME Fellow, ASSAf Fellow, and SARChI Chair, with extensive expertise in hydrogen energy systems, nanotechnology, and thermal-fluid sciences. Together, the authors bring a diverse range of expertise in materials engineering, hydrogen energy, and atomic layer deposition technologies.

Scalable ALD Process for High-Performance MoS₂ Films on Flexible Substrates Unlocks Advanced Electronics Applications

This study by researchers from the University of Southampton (UK), LMU Munich (Germany), and VTT Technical Research Centre of Finland, presents a scalable Atomic Layer Deposition (ALD) method to grow large-area, atomically thin molybdenum disulfide (MoS₂) films with high electrical performance, addressing a key challenge for Transition Metal Dichalcogenides (TMDCs) in commercial semiconductor applications. The ALD process enables precise control over film thickness, stoichiometry, and crystallinity, starting with a MoO₃ layer grown via ALD, followed by a sulfurization process to convert it into MoS₂. This two-step approach decouples film properties, ensuring uniform growth on substrates up to six inches in size. The MoS₂ films are then transferred to flexible substrates using a chemical-free transfer process, resulting in highly uniform films with low surface roughness. Field-effect transistors (FETs) fabricated with these MoS₂ films demonstrate impressive mobility values (up to 55 cm²/Vs), subthreshold slopes as low as 80 mV/dec, and on/off ratios of 10⁷, making them suitable for advanced flexible electronics.



The process begins with 6-inch p-type silicon wafers, onto which a 285 nm layer of thermal SiO₂ is grown at 1000°C using a tube furnace. To enhance the chemical termination of the surface oxide, the wafers are treated in a UV/O₃ reactor for 10 minutes. The subsequent step involves the deposition of MoO₃ via a thermal atomic layer deposition (ALD) process using a Cambridge Nanotech Savannah S200 system. The ALD process utilizes bis(tert-butylimido)bis(dimethylamido) molybdenum as the molybdenum precursor and ozone as the oxidant. By conducting 15 ALD cycles at 250°C, a uniform MoO₃ film with a thickness of 1.31 ± 0.13 nm is achieved across the entire 6-inch wafer, ensuring excellent consistency. This initial MoO₃ layer provides precise control over the number of MoS₂ layers that are subsequently formed, making it a critical step in the overall process.


The study further highlights the integration of MoS₂ in ferroelectric field-effect transistors (FeFETs), which show a memory window of 3 V at ±5 V operation and stable multi-state switching capabilities. These FeFETs, utilizing a thin P(VDF-TrFE) layer as a ferroelectric gate dielectric, offer superior performance compared to traditional flexible memory devices. Electrical measurements confirm the devices’ scalability and uniformity over a 5 × 5 mm² area, with minimal device-to-device variation. The ALD-grown MoS₂ films also retain high stability under repeated bias stress, demonstrating their potential for use in flexible memory and neuromorphic applications. This process provides a commercially viable pathway for integrating high-quality 2D materials into next-generation electronics.

Sources:
Aspiotis, N., Morgan, K., März, B. et al. Large-area synthesis of high electrical performance MoS2 by a commercially scalable atomic layer deposition process. npj 2D Mater Appl 7, 18 (2023). https://doi.org/10.1038/s41699-023-00379-z

Friday, January 3, 2025

Breakthrough in Semiconductor Technology: Amorphous ALD Deposited Nanometal Film Enhances Miniaturization Efficiency

A joint research team from Ajou University in Korea and Stanford University in the US has developed a groundbreaking semiconductor material using an amorphous semi-metallic thin film. Unlike traditional metals that suffer from increased resistivity as they get thinner, this newly discovered material exhibits decreased resistivity when its thickness is reduced. This characteristic addresses a critical challenge in semiconductor miniaturization, where the narrowing of circuit lines impedes electron movement and hampers performance. The material is created by layering niobium (Nb) crystals on a sapphire lattice and covering it with amorphous niobium phosphide (NbP). The research, published in Science, demonstrates that this new material outperforms existing metals like copper and tantalum when the thickness drops below 10 nm, providing a promising solution for next-generation semiconductors.

This amorphous thin film is notable for its compatibility with current semiconductor fabrication processes and its ability to enhance performance without requiring high-temperature treatments. The team plans to further optimize the process using atomic layer deposition (ALD), a method that ensures precise control over film thickness at the atomic scale, making it ideal for advanced semiconductor miniaturization. Professor Oh Il-gwon, who led the research, emphasized the material's potential to overcome existing limitations in semiconductor technologies and its role in securing future industry leadership. This discovery is expected to revolutionize semiconductor wiring processes, improving both efficiency and production costs in the race for smaller, faster, and more efficient chips.

Editor’s summary

Noncrystalline semimetal niobium phosphide has greater surface conductance as nanometer-scale films than the bulk material and could enable applications in nanoscale electronics. Khan et al. grew noncrystalline thin films of niobium phosphide—a material that is a topological semimetal as a crystalline material—as nanocrystals in an amorphous matrix. For films with 1.5-nanometer thickness, this material was more than twice as conductive as copper. —Phil Szuromi

Abstract

The electrical resistivity of conventional metals such as copper is known to increase in thin films as a result of electron-surface scattering, thus limiting the performance of metals in nanoscale electronics. Here, we find an unusual reduction of resistivity with decreasing film thickness in niobium phosphide (NbP) semimetal deposited at relatively low temperatures of 400°C. In films thinner than 5 nanometers, the room temperature resistivity (~34 microhm centimeters for 1.5-nanometer-thick NbP) is up to six times lower than the resistivity of our bulk NbP films, and lower than conventional metals at similar thickness (typically about 100 microhm centimeters). The NbP films are not crystalline but display local nanocrystalline, short-range order within an amorphous matrix. Our analysis suggests that the lower effective resistivity is caused by conduction through surface channels, together with high surface carrier density and sufficiently good mobility as the film thickness is reduced. These results and the fundamental insights obtained here could enable ultrathin, low-resistivity wires for nanoelectronics beyond the limitations of conventional metals.



Sources: 

Surface conduction and reduced electrical resistivity in ultrathin noncrystalline NbP semimetal | Science

Korean and American researchers develop new semiconductor material enhancing performance - CHOSUNBIZ