Revolutionizing CPU Memory: How ReRAM is Shaping the Future of High-Bandwidth Applications

In the Semi Engineering article by Brett Lowe, "Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications," the focus is on the burgeoning field of Resistive Random Access Memory (ReRAM) as a promising solution for the limitations of current on-chip CPU memory. The article highlights the inefficiencies in modern CPU operations, primarily due to the energy consumption and delays caused by data transfer between the CPU and off-chip memory. SRAM, the prevalent on-chip memory, falls short in meeting the requirements of advanced applications like AI and 8K video processing, which demand memory access bandwidths up to 10 terabytes per second. ReRAM emerges as a viable alternative, boasting a non-volatile memory cell structure that uses memristor materials to enable data storage. This technology facilitates significant improvements in storage density by employing a 3D stacking approach.

The article delves into the intricacies of ReRAM's structure and functionality, utilizing SEMulator3D Virtual Fabrication for process simulation and architectural visualization. The discussed 3D ReRAM model comprises multiple layers of wordlines and memristors, strategically organized for optimized storage density. The programming of memristors in ReRAM, requiring low current and voltage, aligns well with the integration into advanced logic devices. The piece concludes with the assertion that ReRAM stands as a robust contender to replace SRAM in on-chip memory, particularly for high-bandwidth CPU applications. Its potential to significantly reduce energy consumption and processing delays in data movement positions ReRAM as a pivotal innovation for future CPU developments.

Source: Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications (semiengineering.com)

Micron Unveils Breakthrough NVDRAM: A Dual-Layer 32Gbit Non-Volatile Ferroelectric Memory with Near-DRAM Performance

At the upcoming International Electron Devices Meeting (IEDM), Micron is set to present a paper on a novel 32Gbit non-volatile ferroelectric memory, termed NVDRAM. Authored by Nirmal Ramaswamy, the vice president of advanced DRAM and emerging memory at Micron, the paper is titled "NVDRAm: A 32Gbit Dual Layer 3D Stacked Non-Volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI Workloads". It introduces the world’s first dual-layer, high-performance, 32Gbit stackable ferroelectric memory technology. This technology, branded as non-volatile dynamic random access memory (NVDRAM), promises faster data movement and better energy efficiency than traditional DRAM, making it ideal for larger neural network models.

NVDRAM merges the benefits of ferroelectric memory cells – non-volatility and high endurance – with performance surpassing NAND flash memory retention and offering DRAM-like read/write speeds. The memory's architecture uses a 5.7nm ferroelectric capacitor for charge retention in a 1T1C DRAM structure, while dual-gated polycrystalline silicon transistors control access. The stacked double memory layer resides above a CMOS access circuit layer on a 48nm pitch. Despite the technological advancements, commercialization discussions remain speculative, potentially awaiting feedback from the IEDM presentation.

The images above show the final die layout (left) and SEM cross-section (center) of a 32Gb NVDRAM with 1T1C memory layers, fabricated over a CMOS array. On the right is a schematic diagram of NVDRAM memory arrays, showing polysilicon access device with orthogonal wordline (WL) and digitline (DL), and ferroelectric memory cells.

Abstract: Non-Volatile Ferroelectric w/DRAM-Like Performance, for AI & Machine Learning: Rapid growth in the size of the data models used in artificial intelligence (AI) and machine-learning (ML) applications is creating an urgent need for higher-bandwidth memory solutions. While new compute paradigms like near-memory-compute and processing-in-memory are being investigated, the best near-term opportunity is to outfit existing, traditional compute architectures with more efficient memory for faster data movement and to accommodate larger models. In this year’s Generative AI Focus Session, Micron researchers will unveil a memory technology for these uses which they call NVDRAM. It is the world’s first dual-layer, high-performance, high-density (32Gb), stackable and nonvolatile ferroelectric memory technology. It combines the non-volatile, high-endurance nature of ferroelectric memory cells with DRAM-like read/write speeds and endurance, and also surpasses the retention performance of NAND memory. NVDRAM uses an ultra-scaled (5.7nm) ferroelectric capacitor as the memory cell, and a dual-gated, stackable, polycrystalline silicon transistor as the access device. To achieve high memory density, two memory layers are fabricated above CMOS circuitry in a 48nm pitch, 4F2 architecture. Full package yield is demonstrated from -40°C to 95°C, along with reliability of 10 years (for both endurance and retention).

Sources:

eeNews: IEDM: Micron to present DRAM-like non-volatile memory for AI ... (eenewseurope.com)

IEDM Paper: 15.7_Non-Volatile Ferroelectric with DRAM-Like Performance, for AI & Machine Learning_Micron.docx (egnyte.com)

NEO Semiconductor Unveils Revolutionary 3D NAND and DRAM Innovations at Flash Memory Summit 2023

NEO Semiconductor, known for its expertise in 3D NAND flash and DRAM technologies, presented groundbreaking innovations at Flash Memory Summit 2023 in August. The full presentation can be seen on Youtube (below). CEO Andy Hsu's keynote introduced their latest creation, 3D X-DRAM™, designed to overcome DRAM's capacity limitations and replace 2D DRAM. This technology utilizes the existing 3D NAND flash process with minor modifications, streamlining development and reducing costs. Hsu also unveiled a new AI application, "Local Computing," promising a substantial enhancement in AI chip performance.

X-DRAM™ significantly reduces data latency and provides ultra-high data throughput to unleash the full potential of High-Bandwidth Memory (HBM). HBM uses many Through Silicon Via (TSV) to increase I/O bandwidth. However, the HBM data latency remains almost the same when using conventional DRAM because bit line lengths remain the same.

Furthermore, NEO Semiconductor showcased various novel memory structures derived from 3D X-DRAM™, tailored for applications like 3D NOR flash memory, 3D Ferroelectric RAM (FFRAM), 3D Resistive RAM (RRAM), 3D Magnetoresistive RAM (MRAM), and 3D Phase Change Memory (PCM). These innovations enable the transition from 2D to 3D memory cells.

Hsu underscored the significance of these technologies for the semiconductor industry, cloud providers, and enterprises, highlighting that 3D X-DRAM™ offers a high-speed, high-density, cost-effective, and high-yield solution.

The presentation addressed the challenges faced by DRAM and NAND flash memory in the context of AI applications and introduced two innovative solutions – 3D X-DRAM™ and 3D X-NAND™.

Being part of the prestigious Flash Memory Summit, NEO Semiconductor showcased its technologies at booth number 215, and interested parties had the opportunity to schedule meetings with the company at the event.

In summary, NEO Semiconductor unveiled groundbreaking advancements in 3D NAND flash and DRAM technologies at Flash Memory Summit 2023, offering solutions to critical challenges in memory performance and capacity.

Source: NEO Semiconductor to Present Its Ground-Breaking 3D NAND and 3D DRAM Architectures in Keynote Address at Flash Memory Summit 2023 - Neo Semiconductor | X-Nand

New Reconfigurable Logic System Achieved with Heterojunction Transistors using ALD

Korean scientists have created a new kind of logic system using special transistors called H-MTR (Link). These transistors can control negative transconductance (NTC) characteristics, allowing for precise logic operations. By programming the transistors, they can switch between different transfer curves, making them highly versatile.

Using the H-MTR transistors, researchers developed a reconfigurable logic inverter called R-inverter (Link). This inverter performed exceptionally well, with a high static noise margin of 85% for binary logic and 59% for ternary logic. It also showed long-term stability and endurance. This reconfigurable logic system opens up new possibilities for computing methods and can generate different output sequences for the same input signal.

The study also demonstrated a dynamic logic conversion-in-memory by connecting a chain of R-inverters. This method allowed for the generation of three different output sequences using a single input signal. This innovative approach to logic computing has never been seen before. The development of this reconfigurable logic system has great potential for applications in artificial intelligence, integrated circuits, and personalized IoT devices. It addresses the need for compatibility and improved information processing capabilities.

One of the key technologies employed in the development of these reconfigurable logic devices is Atomic Layer Deposition. ALD is a precise thin-film deposition technique that allows for the controlled deposition of atomic layers onto a substrate. In the case of the H-MTR transistors, ALD was used to create the necessary heterojunctions and floating gates with high precision. This enables the fine-tuning of the transistor characteristics and ensures reliable performance. The use of ALD in fabricating these devices highlights the significance of advanced manufacturing techniques in pushing the boundaries of electronic systems and opens up possibilities for further advancements in the field of reconfigurable logic.

A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

• Chungryeol Lee, 
• Changhyeon Lee, 
• Seungmin Lee, 
• Junhwan Choi, 
• Hocheon Yoo & 
• Sung Gap Im 

Nature Communications volume 14, Article number: 3757 (2023) 

Applied Materials MEMORY MASTER CLASS 2021 - slide deck

I missed this opportunity, however, I am grateful for Lita Shon-Roy just sending me the link to the slide deck - Tack så mycket. 

Slide deck for the Memory Class LINK

Next class up is Logic June 16, 2021 followed by more interesting topics in 2nd half 2021:

• Specialty semiconductors
• Heterogeneous design and advanced packaging
• Inspection and process control

Teaser slide (Credit Dr. Sony Varghese, Director of Strategic Marketing at at Applied Materials)

You are welcome to contact us at TECHCET (jsundqvist@techcet.com) to dig further into the future surge of materials to realize the data-driven economy:

• ALD/CVD precursors
• Metals/PVD Targets
• Photoresist
• Wet chemicals
• CMP pads & slurries
• Bulk, Rare and Speciality gases
• Wafers

Capacitorless DRAM using oxide semiconductors could be built in 3D layers above a processor’s silicon

One of the biggest problems in computing today is the “memory wall”—the difference between processing time and the time it takes to shuttle data over to the processor from separate DRAM memory chips. The increasingly popularity of AI applications has only made that problem more pronounced, because the huge networks that find faces, understand speech, and recommend consumer goods rarely fit in a processor’s on-board memory.

In December at IEEE International Electron Device Meeting (IEDM), separate research groups in the United States and in Belgium think a new kind of DRAM might be the solution. The new DRAM, made from oxide semiconductors and built in the layers above the processor, holds bits hundreds or thousands of times longer than commercial DRAM and could provide huge area and energy savings when running large neural nets, they say.

Continue reading: New Type of DRAM Could Accelerate AI (IEEE Spectrum)

The transistors in the capacitorless DRAM developed by U.S.-based researchers includes a tungsten-doped indium oxide [orange] semiconductor, palladium top and bottom gates [yellow], nickel source and drain electrodes [green] and hafnium oxide dielectrics [blue]. Image: University of Notre Dame

ALD Hafnium oxide as an enabler for competitive ferroelectric devices

Here is a new paper from NaMLab on ferroelectric hafnium oxide applications entitled "Hafnium oxide as an enabler for competitive ferroelectric devices"

Ferroelectric materials offer the promise to realize low power memory devices and show negative capacitance operation that could lead to novel electronic devices. Although intense research on realizing different memory device concepts based on three different readout schemes have been subject to intense research, the commercial success is limited to low density ferroelectric random access memories based on a direct capacitor readout. The complexity of integrating ferroelectric materials into CMOS processes has limited successful implementations. Ferroelectricity in hafnium oxide related material systems could overcome this limitations for memories and at the same time enable new devices based on negative capacitance.

IEEE: https://ieeexplore.ieee.org/document/9131618

Published in: 2020 IEEE Silicon Nanoelectronics Workshop (SNW)

Endura Impulse - Applied Materials’ New Memory Machines

Tools designed to rapidly build embedded MRAM, RRAM, and phase change memories on logic chips expand foundry options

Applied Materials unveiled Endura Impulse System incorporating nine physical vapor deposition reactors to rapidly build STT-MRAM, RRAM or PCRAM, on 9 July at Semicon West, in San Francisco.

Chip equipment giant Applied Materials wants foundry companies to know that it feels their pain. Continuing down the traditional Moore's Law path of increasing the density of transistors on a chip is too expensive for all but the three richest players—Intel, Samsung, and TSMC. So to keep the customers coming, other foundries can instead add new features, such as the ability to embed new non-volatile memories—RRAM, phase change memory, and MRAM—right on the processor. 

The trouble is, those are really hard things to make at scale. So, Applied has invented a pair of machines that boost throughput by more than an order of magnitude.

Applied Materials' Endura Impulse uses nine physical vapor deposition systems to rapidly build RRAM or PCRAM. Photo: Applied Materials 

Source: Applied Materials LINK

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By Abhishekkumkar Thakur 

TechInsights’ Logic, NAND, DRAM and Emerging Memory Process Roadmaps are here

TechInsights’ Logic Process Roadmap offers an assessment and the anticipatory timing of new innovations from key players within the Logic space including: TSMC, Global Foundries, Intel & others. Download the roadmap here http://bit.ly/2FipHHA 

TechInsights’ technology roadmaps show you the innovations we are monitoring

For over 30 years, TechInsights has been reverse engineering semiconductors and advanced technology products, developing the world’s largest library of technical analysis. We have built this library through two approaches: by conducting analysis in response to client requests, and by proactively analyzing disruptive or innovative technologies as they are released.

We constantly monitor the consumer electronics market to determine which manufacturers are planning to release new solutions, and when. We maintain and regularly update technology roadmaps in several different areas: Logic, NAND Flash Memory, DRAM, Emerging Memory, and Internet of Things Connectivity Systems on Chips, and more.

Updates to the roadmaps shown below are released throughout the year; check this page for updates. 

Applied Materials - The AI Era is Driving Innovations in Memory

[Applied Materials Blog] Industries from transportation and healthcare to retail and entertainment will be transformed by the Internet of Things, Big Data and Artificial Intelligence (AI), which Applied Materials collectively calls the AI Era of Computing.

The previous computing eras—Mainframe/Minicomputer, PC/Server and Smartphone/Tablet—all benefitted from advances in Moore’s Law whereby 2D scaling was accompanied by simultaneous improvements in performance, power and area/cost—also called “PPAC.”

While AI Era applications are booming, Moore’s Law is slowing; as a result, the industry needs breakthroughs beyond 2D scaling to drive PPAC in new ways. Specifically, we need new computing architectures, new materials, new structures—especially area-saving 3D structures—and advanced packaging for die stacking and heterogeneous designs.

 

The AI Era is Driving a Renaissance in Semiconductor Innovation (Applied Materials Blog)

 

AI Era architectural changes are influencing both logic and memory. Machine learning algorithms make heavy use of matrix multiplication operations that are cumbersome in general-purpose logic, and this is driving a move to accelerators and their memories. AI compute includes two distinct memory tasks: first, storing the intermediate results of calculations; and second, storing the weights associated with trained models.

Performance and power are important in the cloud and in the edge, and innovations in memory can help. One approach using existing memory technologies is “near memories” whereby large amounts of working memory are condensed, placed in close physical proximity to logic, and connected via high-speed interfaces. As examples, 3D stacking and through-silicon vias are gaining traction. One major drawback of SRAM and DRAM as “working memories” in these applications is that they are volatile and need a constant supply of power to retain data—such as weights.

To reduce power in the cloud and edge, designers are evaluating new memories that combine high performance with non-volatility so that power is only needed during active read and write operations. Three of the leading new memory candidates are magnetic random-access memory (MRAM), phase-change RAM (PCRAM) and resistive RAM (ReRAM). 

Full article: Applied Materials Blog LINK

 

Additional read: Manufacturing Requirements of New Memories LINK

Weebit Nano partners with Indian Institute of Technology Delhi on ReRAM Research

Resistive random access memory (ReRAM) and other emerging memory technologies have been getting a lot of attention in the past year as semiconductor companies look for ways to more efficiently deal with the requirements of artificial intelligence and neuromorphic computing. Neuromorphic applications are designed to specifically mimic how the human brain learns and processes information, and ReRAM devices show promise for enabling high-density and ultimately scaled neuromorphic architectures because they are significantly smaller and more energy-efficient than current AI data centers. They also mimic the brain’s biological computation at the neuron and synaptic level. 

 

 

Weebit Nano recently partnered with the Non-Volatile Memory Group of the Indian Institute of Technology Delhi (IITD) on a collaborative research project that will apply Weebit’s SiOx ReRAM technology to computer chips used for AI. 

 

Source: EETimes LINK

 

[RRAM-Info] Weebit Nano was established in Israel in 2014 with an aim to commercialize a Rice University's SiOx RRAM technology. The company aims to show a "commercially viable" product by the end of 2017. In August 2016 Weebit Nano performed a reverse-merger with an Australian miner to become a public company (ASK:WBT). In September 2018 Weebit raised $2.16 million USD via a share placement. 

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By Abhishekkumar Thakur, Jonas Sundqvist

CMC Conference Call for Papers, April 25-26, 2019 in Saratoga Springs, NY, USA

The Critical Materials Council (CMC) Conference Committee has issued a call for presentations for the 4th annual public CMC Conference to be held April 25-26, 2019 in Saratoga Springs, NY, USA, following the private CMC face-to-face meetings (April 23-24). The theme of this year’s conference is:

“Materials for Advancing Processes & Technologies”

Keynote: DR. JOHN PELLERIN, Deputy CTO & VP of Worldwide R&D, GlobalFoundries

Three sessions will cover:

I. Global supply-chain issues of economics and regulations,

II. Immediate challenges of materials & manufacturing, and

III. Emerging materials in R&D and pilot fabrication.

 

To encourage the free exchange of the most current pre-competitive information the CMC Conference only requires that speakers submit an abstract for review, and if accepted, presentation slides. No formal paper is required. To submit a 25 min. presentation for consideration, please send a 1-page abstract by January 15, 2019 to cmcinfo@techcet.com.

Attendees will include industry experts handling supply-chains, business-development, R&D, and product management, as well as academics and analysts. CMC member companies will be attending this meeting, as it is an important part of their membership.

On behalf of the CMC Conference Committee,

Jonas Sundqvist, Ph.D., Karey Holland, Ph.D. and Ed Korczynski

UMass Engineers Make Crossbar Arrays of the Smallest Memristors

[University of Massachusetts Amherst LINK] AMHERST, Mass. – A research team at the University of Massachusetts Amherst says it has developed a promising building block for the next generation of nonvolatile random-access memory, artificial neural networks and bio-inspired computing systems.

• "Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension" Nature Nanotechnology (2018) (LINK) 
• Supplemenary information - including details on ALD processing (Al2O3 and HfO2) as well as all other processes (LINK)

 

2-nm memristor crossbar array [University of Massachusetts Amherst]

The team, led by Qiangfei Xia of the electrical and computer engineering department, says the memristor crossbar arrays they have built are, “to the best of our knowledge, the first high-density electronic circuits with individually addressable components scaled down to 2 nanometers dimension built with foundry-compatible fabrication technologies.” The results appear in the journal Nature Nanotechnology.

“This work will lead to high-density memristor arrays with low power consumption for both memory and unconventional computing applications,” says Xia. “The working circuits have been made with technologies that are widely used to build a computer chip.”

Understanding the scale of this work is important, Xia says. One nanometer (nm) is one billionth of a meter. The diameter of a human hair is about 100 micrometers, or 100,000 nanometers. Two nanometers are just a few atoms wide. A crossbar is a matrix of tiny switches.

In the Nature Nanotechnology paper, Xia’s research team explains that organizing small memristors into high-density crossbar arrays is critical to meet the ever-growing demands in high-capacity and low-energy consumption, but is challenging because of difficulties in making highly ordered and highly conductive nanoelectrode arrays. The team has addressed this challenge by developing “nanofins,” metallic nanostructures with very high height-to-width ratio and hence vastly reduced resistance, as the electrodes.

This research is an outgrowth of Xia’s 2013, five-year, $400,000 grant from the National Science Foundation (NSF) Faculty Early Career Development (CAREER) Program to develop emerging nanoelectronic devices. Xia’s NSF research has been addressing the biggest obstacle for the continued operation of Moore’s Law, which states that the number of transistors on integrated circuits doubles approximately every two years.

“It (Moore’s Law) worked perfectly for more than 40 years, but now we’re reaching its fundamental limit, due to the quantum effects related to electron flow,” says Xia. “So, we absolutely need new devices that can do a better job.” In addition to Xia, the other authors of the Nature Nanotechnology paper are Shuang Pi, Can Li, Hao Jiang, Weiwei Xia, Joshua Yang and Huolin Xin

Researchers from University of Groningen, the Netherlands confirm ferroelectricity in nanosized HfO2 crystals

Since the finding of ferroelectricity in HfO2 films of sub 10 nm thickness by Tim Böscke*,  (US8304823B2 NaMLab gGmbH) more then 10 years ago many leading R&D teams and semiconductor companies has confirmed the findings. Now also ferroelectricity in nanosized HfO2 crystalsby has been confirmed by the "Hafnia team” within the Nanostructures of Functional Oxides group, Zernike Institute for Advanced Materials, University of Groningen (UG), the Netherlands (LINK). 

* then at the DRAM Company Qimonda

Figure shows inside view of vacuum chamber in which the process of 'pulsed laser deposition' takes place, used to create the hafnium oxide crystals in this study. On the left the glowing substrate on which the film is growing with atomic control; in the center the blue plasma of ions that is created by shooting a laser on a target with the right chemical composition (target visible on the right side of the figure). | Photo Henk Bonder, University of Groningen

Ferroelectric materials have a spontaneous dipole moment which can point up or down. This means that they can be used to store information, just like magnetic bits on a hard disk. The advantage of ferroelectric bits is that they can be written at a low voltage and power. Magnetic bits require large currents to create a magnetic field for switching, and thus more power. However, according to the scientific community, the aligned dipoles in ferroelectric materials are only stable in fairly large groups; thus, shrinking the crystals results into the loss of dipole moment obstructing ferroelectricity based storage devices.

Nevertheless, eight years ago, the first publication by ex-Qimonda experts and researchers from Fraunhofer and RWTH Aachen (Appl. Phys. Lett. 99, 102903 (2011); https://doi.org/10.1063/1.3634052) announced that hafnium oxide thin films were ferroelectric when thinner than ten nanometres and that thicker films actually lost their ferroelectric properties. This triggered many groups across the globe to dig deeper and confirm the claim of researchers from NamLab. Noheda and her group at University of Groningen was also one of them. Since the ferroelectric hafnium oxide samples used in the study carried out at NaMLab were polycrystalline and showed multiple phases, obscuring any clear fundamental understanding of such an unconventional phenomenon, Noheda and her group decided to study these crystals by growing clean (single-phase) films on a substrate.

Using X-ray scattering and high-resolution electron microscopy techniques, the group observed that very thin films (under ten nanometres) grow in an entirely unexpected and previously unknown polar structure, which is necessary for ferroelectricity. Combining these observations with meticulous transport measurements, they confirmed that the material was indeed ferroelectric. Surprisingly, they noticed that the crystal structure changed when the layers exceeded 10 nm, thus reaching the same conclusion as of the Namlab.

In the substrate that UG researchers used, the atoms were a little bit closer than those in hafnium oxide which strained hafnium oxide crystals a little. Moreover, at a very small size, particles have a very large surface energy, creating pressures of up to 5 GPa in the crystal. This altogether forces a different crystal arrangement and in turn polar phase in the HfO2 film.

One contradicting finding of the UG researchers is that the HfO2 crystals do not need a ‘wake-up’ cycle to become ferroelectric. The thin films investigated at NamLab turned ferroelectric only after going through a number of switching cycles (wake-up cycles) needed to align the dipoles in “uncleaned” samples grown via other techniques. In case of the pulsed laser deposition setup and the substrate used at UG, the alignment is already present in the crystals.

Meanwhile, NaMLab has explored ferroelectric properties in atomic layer deposition (ALD) based thin-films of doped HfO2, and has achieved revolutionary results (LINK). A variety of dopant materials (Si, Al, Ge, Y, Gd, La and Sr) with a crystal radius ranging from 50 to 130 pm has been studied in addition to a mixed Hf1-xZrxO2. The aim is to develop a memory concept with the HfO2 based ferroelectric transistors (FeFET) as building blocks. The FeFET is a long-term contender for an ultra-fast, low-power and non-volatile memory technology. In these devices the information is stored as a polarization state of the gate dielectric and can be read non-destructively as a shift of the threshold voltage. The advantage of a FeFET memory compared to the Flash memory is its faster access times and much lower power consumption at high data rates. In the framework of a project together with GLOBALFOUNDRIES and Fraunhofer IPMS, which was funded by the Free State of Saxony, a one-transistor (1T) FeFET eNVM was successfully implemented at NaMLab in a 28 nm gate-first super low power (28SLP) CMOS technology platform using only two additional structural masks (LINK). The electrical baseline properties remain the same for the FeFET integration, demonstrating the feasibility of FeFET as low-cost eNVM.

Guest Blog by: Abhishekkumar Thakur, Fraunhofer IKTS / TU Dresden
Location: Dresden, Germany

LinkedIn: www.linkedin.com/in/abhishekkumar-thakur-16081991