Showing posts with label RRAM. Show all posts
Showing posts with label RRAM. Show all posts

Saturday, January 20, 2024

Revolutionizing CPU Memory: How ReRAM is Shaping the Future of High-Bandwidth Applications

In the Semi Engineering article by Brett Lowe, "Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications," the focus is on the burgeoning field of Resistive Random Access Memory (ReRAM) as a promising solution for the limitations of current on-chip CPU memory. The article highlights the inefficiencies in modern CPU operations, primarily due to the energy consumption and delays caused by data transfer between the CPU and off-chip memory. SRAM, the prevalent on-chip memory, falls short in meeting the requirements of advanced applications like AI and 8K video processing, which demand memory access bandwidths up to 10 terabytes per second. ReRAM emerges as a viable alternative, boasting a non-volatile memory cell structure that uses memristor materials to enable data storage. This technology facilitates significant improvements in storage density by employing a 3D stacking approach.

The article delves into the intricacies of ReRAM's structure and functionality, utilizing SEMulator3D Virtual Fabrication for process simulation and architectural visualization. The discussed 3D ReRAM model comprises multiple layers of wordlines and memristors, strategically organized for optimized storage density. The programming of memristors in ReRAM, requiring low current and voltage, aligns well with the integration into advanced logic devices. The piece concludes with the assertion that ReRAM stands as a robust contender to replace SRAM in on-chip memory, particularly for high-bandwidth CPU applications. Its potential to significantly reduce energy consumption and processing delays in data movement positions ReRAM as a pivotal innovation for future CPU developments.

Sunday, June 18, 2017

New prospects for universal memory from MIPT Russia using Picosun ALD

MIPT Reports: Researchers from MIPT’s Center of Shared Research Facilities have found a way to control oxygen concentration in tantalum oxide films produced by atomic layer deposition. These thin films could be the basis for creating new forms of nonvolatile memory.

The MIPT non-volatile ReRAM memory cell is based on ALD deposited tantalum oxide using tantalum ethoxide and water.

“The hardest part in depositing oxygen-deficient films was finding the right reactants that would make it possible to both eliminate the ligands contained in the metallic precursor and control oxygen content in the resulting coating,” says Andrey Markeev, who holds a PhD in physics and mathematics and is a leading researcher at MIPT. “We achieved this by using a tantalum precursor, which by itself contains oxygen, and a reactant in the form of plasma-activated hydrogen.”

Experimental cluster, including a Picosun ALD reactor, for growing and studying thin films in a vacuum at the Center of Shared Research Facilities, MIPT

Sunday, November 22, 2015

SK Hynix & SNU demonstrate 28nm RRAM cell with ultra thin ALD Ta/Ta2O5 stack

Here is a impressive report by SK Hynix & Prof. Hwang and co-workers SNU on a RRAM device with Ta/Ta2O5 stacked RS layers with ultra-thin Ta2O5 thicknesses (0.5–2.0 nm) deposited by ALD. Woah that´s thin  - like the same order of thickness like native oxide, which makes me wonder if teh extra couple of ALD cycles was needed --> I need to study the paper more carefully!

Thickness effect of ultra-thin Ta2O5 resistance switching layer in 28 nm-diameter memory cell 

C.S. Hwang et al

Scientific Reports 5, Article number: 15965 (2015)
(a) Schematic diagram and (b) TEM image of the TiN/Ta2O5/Ta/TaN device. Ta2O5 (0.5 nm) device, and (d) Ta2O5 (1.5 nm) device. Insets show the linear I-V plot. Scanning transmission electron microscopy (STEM) high angle annular dark field (HAADF) images of (c) 0.5 nm-thick device and (d) 2.0nm-thick device. 

Resistance switching (RS) devices with ultra-thin Ta2O5 switching layer (0.5–2.0 nm) with a cell diameter of 28 nm were fabricated. The performance of the devices was tested by voltage-driven current—voltage (I-V) sweep and closed-loop pulse switching (CLPS) tests. A Ta layer was placed beneath the Ta2O5 switching layer to act as an oxygen vacancy reservoir. The device with the smallest Ta2O5 thickness (0.5 nm) showed normal switching properties with gradual change in resistance in I-V sweep or CLPS and high reliability. By contrast, other devices with higher Ta2O5 thickness (1.0–2.0 nm) showed abrupt switching with several abnormal behaviours, degraded resistance distribution, especially in high resistance state, and much lower reliability performance. A single conical or hour-glass shaped double conical conducting filament shape was conceived to explain these behavioural differences that depended on the Ta2O5 switching layer thickness. Loss of oxygen via lateral diffusion to the encapsulating Si3N4/SiO2 layer was suggested as the main degradation mechanism for reliability, and a method to improve reliability was also proposed.

Wednesday, August 12, 2015

Rice U. discovery may boost ReRAM memory technology

My favorite high-k metal oxide Ta2O5 is used again for a resistive RAM memory - this time with my least favorite material - Grrrraphene. Just can´t stand the hype I guess. Anyhow considering recent developments in cross bar Memory cell technology by Intel and Micron this could prove to be a future prospect.

A schematic shows the layered structure of tantalum oxide, multilayer graphene and platinum used for a new type of memory developed at Rice University. The memory device overcomes crosstalk problems that cause read errors in other devices. 
(Tour Group/Rice University)

PUBLIC RELEASE: 10-AUG-2015Rice U. discovery may boost memory technology
Rice University scientists make tantalum oxide practical for high-density devices

Scientists at Rice University have created a solid-state memory technology that allows for high-density storage with a minimum incidence of computer errors.

The memories are based on tantalum oxide, a common insulator in electronics. Applying voltage to a 250-nanometer-thick sandwich of graphene, tantalum, nanoporous tantalum oxide and platinum creates addressable bits where the layers meet. Control voltages that shift oxygen ions and vacancies switch the bits between ones and zeroes.

The discovery by the Rice lab of chemist James Tour could allow for crossbar array memories that store up to 162 gigabits, much higher than other oxide-based memory systems under investigation by scientists. (Eight bits equal one byte; a 162-gigabit unit would store about 20 gigabytes of information.)

Details appear online in the American Chemical Society journal Nano Letters. More details can be found here:

Tuesday, July 14, 2015

Imec and Panasonic Demonstrate Breakthrough RRAM Cell

Imec and Panasonic Corp. announced today that they have fabricated a 40nm TaOx-based RRAM (resistive RAM) technology with precise filament positioning and high thermal stability. This breakthrough result paves the way to realizing 28nm embedded applications. The results were presented at this year’s VLSI technology symposium (Kyoto, June 15-19 2015).

Cross-sectional TEM of 40-nm Ir(TE)/Ta2O5/TaOx/TaN (BE) RRAM

One of today’s most promising concepts for scaled memory is RRAM which is based on the electronic (current-or voltage-induced) switching of a resistor element material between two metals. Imec and Panasonic developed a method that overcomes filament instability in RRAM, one of the critical parameters that impacts the memory state during read operation in resistive memory. 

The method was realized using a combination of process technologies such as low-damage etching, cell side oxidation, and an innovative encapsulated cell structure with an Ir/Ta2O5/TaOx/TaN stacked film structure featuring a filament at the cell center. With these methods, a 2-Mbit 40nm TaOx-based RRAM cell with precise filament positioning and high thermal stability was achieved. The memory array showed excellent reliability of 100k cycles and 10 years’ retention at 85°C. Additionally, the filament control and thermal stability technologies offer the potential to realize 28nm cell sizes.

Gosia Jurczak, director of imec’s research program on RRAM devices stated: “With these breakthrough results, we have proven the potential of this promising memory concept as embedded nonvolatile memory in 28nm technology node where conventional NOR Flash shows scaling limitations. This result is a confirmation of our leadership position in research and development on resistive memory.”

Sunday, May 18, 2014

ITRS 2013 Emerging Research Devices on HfO2 based ferroelectric devices

ITRS 2013 Emerging Research Devices (ERD) Chapter has been updated on ferroelectric devices (page 13) referring to recent development using ferroelectric hafnium oxide.

From Page 12 : Notably, since 2011, ferroelectricity in a variety of doped and polycrystalline HfO2 has been reported. The HfO2 based FeFETs show promising write speed (down to a few ns), retention (projected to 10 years), and endurance (up to 1012), which all match the best performances of its perovskite counterparts (refer to ERD4a). [65,66,67,68,69], and HfO2-based FeFETs have been fabricated using standard high-k metal gate (HKMG) processes. The use of HfO2-based ferroelectrics significantly reduces the physical thickness of the gate stack, and in turn scales down the channel length to the current technology node [70]. Follow the typical HKMG process, SiO2 serves as the buffer layer between HfO2 and Si with a sub-nanometer thickness, yielding low depolarization field.

"In Ferroelectric FET memory, a ferroelectric dielectric forms the gate insulator of an FET. The main concern on FeFET memory lies in operation reliability. Operational reliability of the FeFET RAM is limited by the time dependant remnant polarization of the ferroelectric gate dielectric reflected in retention loss. Control of the ferroelectric-semiconductor interface is critical for FeFET properties. The scalability of FeFET memory beyond the 22nm generation is uncertain"

As a comparasion to RRAM, one of the main contenders for emerging memory technologies:

"RRAM include multiple device types and mechanisms with varying level of maturity. The survey is based on rating of the general field rather than specific types. Some recent breakthrough in RRAM significantly enhanced perceived potential of this technology, e.g., 32Gb array demonstration726. Overall RRAM assessment is similar or better than existing CMOS-based nonvolatile memories (Flash). A clear advantage of RRAM is scalability owing to the filamentary conduction and switching mechanisms. The simple device structure and fab-friendly materials also contribute to high rating in CMOS compatibility. One of the major concerns of RRAM is the operation reliability due to the stochastic nature and the defect-related mechanisms. Large variation of RRAM switching parameters has been commonly observed and is considered an intrinsic feature of RRAM mechanisms."
Refernces on FeFET:

[65] T. S. Boscke, J. Muller, D. Brauhaus, U. Schroder, and U. Bottger, "Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors," IEDM 2011, pp. 24.5.1–24.5.4.
[66] M. Hyuk Park, H. Joon Kim, Y. Jin Kim, W. Lee, H. Kyeom Kim, and C. Seong Hwang, "Effect of forming gas annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films with and without Pt electrodes," Appl. Phys. Lett., vol. 102, no. 11, p. 112914, 2013.
[67] J. Muller, et al, "Ferroelectricity in yttrium-doped hafnium oxide," J. Appl. Phys., vol. 110, no. 11, p. 114113, 2011.
[68] J. Muller, et al, "Ferroelectric Zr0.5Hf0.5O2 thin films for nonvolatile memory applications," Appl. Phys. Lett., vol. 99, no. 11, p. 112901, 2011.
[69] S. Mueller, J. Mueller, A. Singh, S. Riedel, J. Sundqvist, U. Schroeder, and T. Mikolajick, "Incipient Ferroelectricity in Al-Doped HfO2 Thin Films," Adv. Funct. Mater., vol. 22, no. 11, pp. 2412–2417, Jun. 2012.
[70] J. Muller, E. Yurchuk, T. Schlosser, J. Paul, R. Hoffmann, S. Muller, D. Martin, S. Slesazeck, P. Polakowski, J. Sundqvist, M. Czernohorsky, K. Seidel, P. Kucher, R. Boschke, M. Trentzsch, K. Gebauer, U. Schroder, and T. Mikolajick, "Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG," 2012 Symp. VLSI Tech., pp. 25–26, 2012


Emerging memory taxonomy according to ITRS 2013

For all of you working on emerging memory technologies such as ReRAM, FeRAM, PCM, MRAM etc. this classification scheme in the latest ITRS roadmap should be very useful. Please check out the  ERD - Emerging Research Devices Chapter.

"Figure ERD3 [inserted below] provides a simple visual method of categorizing memory technologies. At the highest level, memory technologies are separated by the ability to retain data without power. Nonvolatile memory offers essential use advantages, and the degree to which non-volatility exists is measured in terms of the length of time that data can be expected to be retained. Volatile memories also have a characteristic retention time that can vary from milliseconds to (for practical purposes) the length of time that power remains on. Nonvolatile memory technologies are further categorized by their maturity. Flash memory is considered the baseline nonvolatile memory because it is highly mature, well optimized, and has a significant commercial presence. Flash memory is the benchmark against which prototypical and emerging nonvolatile memory technologies are measured. Prototypical memory technologies are at a point of maturity where they are commercially available (generally for niche applications), and have a large scientific, technological, and systematic knowledge base available in the literature. These prototypical technologies are covered in Table ERD2 and in the PIDS Chapter. The focus of this section is Emerging Memory Technologies. These are the least mature memory technologies in Fig. ERD4, but have been shown to offer significant potential benefits if various scientific and technological hurdles can be overcome. This section provides an overview of these emerging technologies, their potential benefits, and the key research challenges that will allow them to become viable commercial technologies."

Figure ERD3, from the ERD Chapter 2013 - Emerging memory taxonomy (ITRS 2013, Chapter ERD
If you continue to read from page 8 on you will find a short description of all emerging memory technologies that are being considered by he ITRS. If you´re saturated on resistive technologies you can fast forward to page 12 and read about the new contender FeFET :-)