Showing posts with label FRAM. Show all posts
Showing posts with label FRAM. Show all posts

Thursday, November 25, 2021

Watch again - Material development for MRAM and FRAM stacks at Fraunhofer IPMS-CNT

Material development for MRAM and FRAM stacks

Dr. Lukas Gerlich & Konrad Seidel (Fraunhofer IPMS - Center Nanoelectronic Technologies)

Today, data is the lifeblood disrupting many industries. The vast majority of this data is stored in the form of non-volatile magnetic bits in hard disk drives. This technology was developed more than half a century ago and has reached fundamental scaling limits that prevent further increases in storage capacity. New approaches are needed.

In the webinar, FRAM (Ferroelectric Random Access Memory) and MRAM (Magnetoresistive Random Access Memory) will be presented as two promising concepts for future ultra-low power memory technologies. Special attention will be paid to material development and fabrication on state-of-the-art industrial equipment for 300 mm wafers.

Previous Webinar: Fe- FET - A Memory Device for Maximum Integration, Konrad Seidel (IoT Components and Systems) Webinars - Fraunhofer IPMS

Sunday, March 22, 2015

Ferroelectric HfO2 Based Materials and Devices: Current Status and Future Prospects

Ferroelectric Hafnium Oxide Based Materials and Devices: Assessment of Current Status and Future Prospects [OPEN ACCESS]

J. Müller, P. Polakowski, S. Mueller and T. Mikolajick
ECS J. Solid State Sci. Technol. volume 4, issue 5, N30-N35


Bound to complex perovskite systems, ferroelectric random access memory (FRAM) suffers from limited CMOS-compatibility and faces severe scaling issues in today's and future technology nodes. Nevertheless, compared to its current-driven non-volatile memory contenders, the field-driven FRAM excels in terms of low voltage operation and power consumption and therewith has managed to claim embedded as well as stand-alone niche markets. However, in order to overcome this restricted field of application, a material innovation is needed. With the ability to engineer ferroelectricity in HfO2, a high-k dielectric well established in memory and logic devices, a new material choice for improved manufacturability and scalability of future 1T and 1T-1C ferroelectric memories has emerged. This paper reviews the recent progress in this emerging field and critically assesses its current and future potential. Suitable memory concepts as well as new applications will be proposed accordingly. Moreover, an empirical description of the ferroelectric stabilization in HfO2 will be given, from which additional dopants as well as alternative stabilization mechanism for this phenomenon can be derived. 

Figure 4.

Comparison of the two major flavors of FRAM. 1T-1C: (a) Working principle illustrating the sensing margin / switched polarization Psw derived from switched charge Qsw and non-switched polarization Pnsw in the P-E-hysteresis. (b) DRAM-like architecture of FRAM adding a plateline to word- and bitline for bipolar ferroelectric switching. (c) TEM-micrograph and related P-E-hysteresis of a FE-HfO2 based deep trench capacitor array proving the concept of 3D-integration capability. To illustrate the advantage of this area enhancement, the polarization density is calculated with respect to the lateral footprint of a comparable planar capacitor. 1T: (d) Illustration of the working principle by a graphical representation of the charge neutrality condition in a MFIS stack. Position 1 and 2 of the insulator-semiconductor loadline represents the transition from the ON-state to the OFF-state of the FeFET or vice versa. Accordingly, the gate voltage difference to turn on/off the FeFET can be approximated by 2 · VC = 2 · Ec · dFE, i.e. the memory window MW. (e) Disturb resilient AND architecture of the FeFET. (f) TEM-micrograph and related ID-VG-hysteresis of a FE-HfO2 based 28 nm high-k metal gate transistors proving the concept of advanced 1T FRAM scalability

The recent success of smartphones and tablet computers has accelerated the R&D of fast and energy efficient non-volatile semiconductor memories, capable of replacing the conventional SRAM-DRAM-Flash memory hierarchy. These so called emerging memories usually leverage on the fact that certain materials possess the capacity for remembering their electric, magnetic or caloric history. For the extensively investigated ferroelectrics this ability to memorize manifests in atomic dipoles switchable in an external electric field. This unique property renders them the perfect electric switch for semiconductor memories. Consequently, only a few years after the realization of a working transistor the first ferroelectric memory concepts were proposed.

However, more than 60 years and several iterations later it is now clear that the success or failure of FRAM is mainly determined by the proper choice and engineering of the ferroelectric material. Perovskite ferroelectrics and related electrode systems underwent an extensive optimization process to meet the requirements of CMOS integration and are now considered the front up solution in FRAM manufacturing. Nevertheless, those perovskite systems require complex integration schemes and pose scaling limitations on 1T and 1T-1C memory cells that until now remain unsolved. This creates an unbalance between memory performance on the one side and manufacturing and R&D costs on the other side. This dilemma has ever since restricted FRAM to niche markets. 

With the recent demonstration of ferroelectricity in HfO2-based systems (FE-HfO2) a CMOS-compatible, highly scalable and manufacturable contender has emerged, that significantly expands the material choice for 1T and 1T-1C ferroelectric memory solutions as well as nanoscale ferroelectric devices. 

In this paper we will review and expand the current understanding of ferroelectricity in HfO2, as well as discuss future prospects of ferroelectric HfO2-based devices with respect to scaling, reliability and manufacturability. Opportunities and drawbacks of this disruptive development in ferroelectric material science will be critically examined. 

Continue reading in the full paper with Open Access here.

Thursday, March 19, 2015

Qimonda’s late legacy: 28nm FeRAM using ALD Ferroelectric HfO2

Qimonda’s late legacy: 28nm FeRAM
By Julien Happich
Electronic Engineering Times Europe January 2015 27
CMOS-COMPATIBLE 28 NM FERAM could become commercially available within three to five years, according to research from a collaborative project between NaMLab at TU Dresden, the Fraunhofer Institute for Photonic Micro Systems (IPMS) and GlobalFoundries. Indeed, smashing all prior research claims on FeRAM and scalable to geometries an order of magnitude smaller than today’s 130nm FeRAM commercial offerings, the results are so promising that they are being included in the current version of the International Technology Roadmap for Semiconductors (ITRS).
A result of a sub-project called ‘Cool Memory’ at Saxonys’ cluster Cool Silicon, the technology relies on newly found ferroelectric effects in doped Hafnium oxide (HfO2). Considering that Hafnium oxide is already commonly used as a high-k gate dielectric in CMOS transistors, the processes are pretty much already in place for its ferroelectric variant, readily scalable with CMOS transistors. So why look at doped Hafnium oxide in the first place? We asked Dr. Thomas Mikolajiick, Professor for Nanoelectronic Materials and Director of the NaMLab, coordinator for Cool Silicon.
“This research goes back to 2007 at DRAM maker Qimonda, when a PhD candidate Tim Böscke was doing research to improve HfO2 as a high-k dielectric for capacitors in dynamic random access memories, using dopants to stabilize the material”, explained Mikolajiick. “At certain dopant concentrations and under specific treatments, Böscke noticed that strange peaks occurred in the CV characteristic of the material, and that it behaved as a ferroelectric. This was totally unexpected!

Full story as a PDF can be downloaded here.

Sunday, July 13, 2014

Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications

P. Polakowski, S. Riedel, W. Weinreich, M. Rudolf, J. Sundqvist, K. Seidel, J. Muller
Memory Workshop (IMW), 2014 IEEE 6th International
Date of Conference: 18-21 May 2014 Page(s): 1 - 4 Print ISBN: 978-1-4799-3594-9 Conference Location : Taipei, Taiwan DOI:10.1109/IMW.2014.6849367
Aiming for future nonvolatile memory applications the fabrication and electrical characterization of 3-dimensional trench capacitors based on ferroelectric HfO2 is reported. It will be shown that the ferroelectric properties of Al-doped HfO2 ultrathin films are preserved when integrated into 3-dimensional geometries. The Al:HfO2 thin films were deposited by ALD and electrical data were collected on trench capacitor arrays with a trench count up to 100k. Stable ferroelectric switching behavior was observed for all trench arrays fabricated and only minimal remanent polarization loss with increasing 3-dimensional area gain was observed. In addition these arrays were found to withstand 2∗109 endurance cycles at saturated hysteresis loops. With these report the 3D capability of ferroelectric HfO2 is confirmed and for the first time a feasible solution for the vertical integration of ferroelectric 1T/1C as well as 1T memories is presented.

Process flow scheme for the fabricated ferroelectric deep trench capacitors with high aspect ratio of 13:1 and the accordingly measured hysteresis loop of a 3D deep trench capacitor

Sunday, May 18, 2014

Emerging memory taxonomy according to ITRS 2013

For all of you working on emerging memory technologies such as ReRAM, FeRAM, PCM, MRAM etc. this classification scheme in the latest ITRS roadmap should be very useful. Please check out the  ERD - Emerging Research Devices Chapter.

"Figure ERD3 [inserted below] provides a simple visual method of categorizing memory technologies. At the highest level, memory technologies are separated by the ability to retain data without power. Nonvolatile memory offers essential use advantages, and the degree to which non-volatility exists is measured in terms of the length of time that data can be expected to be retained. Volatile memories also have a characteristic retention time that can vary from milliseconds to (for practical purposes) the length of time that power remains on. Nonvolatile memory technologies are further categorized by their maturity. Flash memory is considered the baseline nonvolatile memory because it is highly mature, well optimized, and has a significant commercial presence. Flash memory is the benchmark against which prototypical and emerging nonvolatile memory technologies are measured. Prototypical memory technologies are at a point of maturity where they are commercially available (generally for niche applications), and have a large scientific, technological, and systematic knowledge base available in the literature. These prototypical technologies are covered in Table ERD2 and in the PIDS Chapter. The focus of this section is Emerging Memory Technologies. These are the least mature memory technologies in Fig. ERD4, but have been shown to offer significant potential benefits if various scientific and technological hurdles can be overcome. This section provides an overview of these emerging technologies, their potential benefits, and the key research challenges that will allow them to become viable commercial technologies."

Figure ERD3, from the ERD Chapter 2013 - Emerging memory taxonomy (ITRS 2013, Chapter ERD
If you continue to read from page 8 on you will find a short description of all emerging memory technologies that are being considered by he ITRS. If you´re saturated on resistive technologies you can fast forward to page 12 and read about the new contender FeFET :-)