Tuesday, October 29, 2024
Intel Sets Record with 2D TMD Transistors for Next-Gen Electronics
Seiichi Iwamatsu, the Inventor of Atomic Layer Etching: The Conception of Cycled Exposures of Silicon to Halogens and Pulses of Heat, Ions, and More
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Acknowledgement
The authors would like to thank Dr. Masanobu Honda (Tokyo Electron Miyagi Ltd., Japan) for his support in retrieving some of the historic facts mentioned herewith about Dr. Iwamatsu.
References
[1] R.L. Puurunen, Chem. Vap. Deposition 20, pp. 332–344 (2014); doi:10.1002/cvde.201402012.
[2] V.B. Alekskovski and S. I. Kol'tsov, Some characteristics of molecular layering reactions, Abstract of Scientific and Technical Conference, Goskhimizdat, Leningrad, 1965, p. 67 (in Russian).
[3] T. Suntola and J. Antson, FIN 52359, priority Nov. 29, 1974, US Patent 4,058,430, Nov. 15, 1977.
[4] K.J. Kanarik, et al., J. Vac. Sci. Technol. A 33, 020802 (2015); doi/10.1116/1.4913379.
[5] W.M.M. Kessels, www.atomiclimits.com/ March 2, 2020.
[6] M.N. Yoder, Atomic Layer Etching, US Patent 4,756,794, July 12, 1988; assigned to US Navy.
[7] S. Iwamatsu, Atomic Layer Etching Method, JPS5898929A / JPH0379862B2; priority Dec. 9, 1981, published June 13, 1983; assigned to Seiko Epson Corp.
[8] https://worldwide.espacenet.com/patent/search/family/016189802/publication/JPH0472726A?q=iwamatsu%20seiichi%20atomic%20layer%20etching
[9] S. Iwamatsu, Digital Etching Process, JPH0472726A, priority: July 13, 1990, published March 6, 1992; assigned to Seiko Epson Corp.
[10] https://corporate.epson/en/technology/search-by-products/wearable/quartz-watch.html
Monday, October 28, 2024
Lam Research Sees Growth Opportunities in Etch and Deposition Technologies Despite NAND Downturn
In its Q1 2025 earnings call, Lam Research reported strong performance and emphasized growth opportunities, particularly in etch and deposition technology. CEO Tim Archer highlighted optimism for NAND spending recovery in 2025, supported by technology upgrades and a transition to molybdenum through Lam’s advanced Atomic Layer Deposition (ALD). Lam is positioned to capture opportunities in advanced semiconductor nodes like gate-all-around and EUV patterning, while its expanded offerings in high-bandwidth memory (HBM) and advanced packaging align with growing demand in AI and high-performance computing. Despite regulatory challenges in China, Lam continues to serve this market by focusing on upgrades and services. Looking ahead, Lam expects to outpace industry growth, driven by its strategic positioning across advanced technologies.
In its Q1 2025 earnings call, Lam Research Corporation (NASDAQ: LRCX) reported solid performance and reiterated optimism for growth in 2025, largely driven by demand for etch and deposition technologies. CEO Tim Archer emphasized Lam’s strategic positioning in an industry experiencing technological shifts, despite a prolonged downturn in NAND spending.
Lam anticipates a recovery in NAND spending in 2025, largely driven by technology upgrades rather than new capacity expansions. Key factors include a transition from tungsten to molybdenum in NAND structures, which improves performance by reducing resistivity. Lam is well-positioned in this area due to its extensive installed base and production wins, projecting an advantageous position as these upgrades scale into 2025.
NAND Technology Upgrades Set to Drive Etch and Deposition Demand in 2025
While the NAND segment has been in a prolonged downturn, Lam anticipates a recovery in 2025 as manufacturers upgrade to advanced nodes. The push toward 3D NAND layers exceeding 200 is essential to meet the growing demand for high-speed, high-capacity storage in data centers and client devices. Currently, about two-thirds of NAND capacity remains at older technology nodes, highlighting significant room for technology upgrades. Lam’s extensive installed base of NAND equipment positions it well to benefit as customers look to improve efficiency and performance.
Furthermore, Archer highlighted a shift from tungsten to molybdenum as a key materials change in NAND, addressing word line resistance challenges. This transition is particularly favorable for Lam, as it has already secured production wins in molybdenum deposition, which will scale up throughout 2025. These advancements are expected to enhance Lam's leadership position in NAND technology transitions.
Lam's product offerings mentioned in the reporting, along with their primary applications and strategic impacts.
Advanced Logic and Foundry Nodes: Key Growth Segments for Lam
Lam is also poised to benefit from shifts in advanced logic and foundry nodes, which are increasingly adopting gate-all-around architectures, backside power distribution, and advanced EUV patterning. These cutting-edge technologies require more intensive use of etch and deposition processes, aligning with Lam’s expertise and product offerings.
Archer noted the company's recent wins in selective etch tools and other innovations that support these advanced nodes, positioning Lam favorably as customers transition to architectures with greater power and performance needs. This expanding demand from foundry and logic customers offers a substantial growth opportunity for Lam’s advanced etch and deposition technologies.
Advanced Packaging Driven by AI Fuels Revenue Growth
The AI and high-performance computing boom has intensified demand for advanced packaging, particularly for high-bandwidth memory (HBM). Lam’s copper plating technology, SABRE 3D, has experienced substantial adoption, doubling its market share this year. This growth has been fueled by the rising complexity of 2.5D and 3D packages, which require high-performance interconnections to support AI-driven systems.
Lam anticipates this trend will continue into 2025 as the industry moves toward more advanced and intricate packaging solutions. According to Archer, advanced packaging will play a critical role in the semiconductor ecosystem for the foreseeable future, and Lam’s early investment in this technology has positioned it for continued market share gains.
Supporting Installed Base and Productivity in Memory Markets
Lam’s Customer Support Business Group (CSBG) has also shown growth, focusing on productivity enhancements and tool reuse. With Lam’s extensive tool installations in both DRAM and NAND, customers are prioritizing upgrades over entirely new systems, especially as they look to improve cost efficiency during NAND’s down cycle. This focus on tool reuse has led to recent market share gains for Lam, as existing tools are upgraded for better value than new installations.
As DRAM and NAND customers intensify efforts to reduce costs, Lam’s service-oriented model and productivity solutions, including equipment intelligence services, have seen greater adoption. This trend underscores Lam's ability to support its customers' evolving needs in an era of increased etch and deposition intensity.
Lam Research Leverages ALD for Moly Transition in NAND, Driving Next-Gen Semiconductor Performance
Lam Research's perspective on ALD is optimistic, particularly as it becomes increasingly essential in NAND technology upgrades. The company highlighted the industry's ongoing shift from tungsten to molybdenum (moly) for improved resistivity in 3D NAND structures, a transition that Lam’s ALD technology is well-positioned to support. Lam has already secured production wins for ALD applications with molybdenum, expected to ramp up significantly in 2025. This capability extends beyond NAND, with potential applications in DRAM and advanced logic/foundry nodes, underscoring ALD’s growing importance in meeting next-generation semiconductor demands.
Lam Research Adapts to Regulatory Challenges as China Revenue Set to Decline in 2025
In its Q1 2025 earnings presentation, Lam Research highlighted key developments and expectations for the China market. China accounted for roughly 37% of Lam's revenue in the September quarter, but the company anticipates this share will decrease to around 30% by December and potentially decline further in 2025. This projected downturn reflects both anticipated shifts in demand and the impact of U.S. export restrictions on advanced semiconductor equipment sales to China. Lam acknowledged the challenges posed by ongoing and potential new U.S. export controls, which could limit its ability to sell to certain advanced technology segments in China. Nevertheless, Lam remains committed to supporting its domestic Chinese customers within the boundaries of regulatory compliance, expecting demand in restricted segments to normalize as global WFE (wafer fabrication equipment) spending adjusts.
Much of Lam's business in China now focuses on servicing domestic fabs with tools for trailing-edge and specialty node processes, areas that generally remain unaffected by export controls. Through its Reliant product line, Lam continues to support these nodes, emphasizing upgrades and maintenance services as primary offerings in a market constrained by new advanced technology sales. Despite potential reductions in advanced equipment sales, the company is confident that its service and support model will help stabilize revenue in the region. By prioritizing productivity solutions and customer support, Lam is adapting to a complex regulatory environment while anticipating that China’s share of its revenue will gradually normalize amid a broader decline in WFE spending in the country.
Strategic Positioning in 2025 and Beyond
In summary, Lam Research is set to capitalize on a growing demand for etch and deposition technology driven by the industry’s shift to advanced architectures. Archer concluded the call with optimism, stating that the company is well-positioned to capture market share as the semiconductor industry increasingly relies on complex, three-dimensional structures. With its advanced product offerings, Lam expects to outperform overall wafer fabrication equipment (WFE) growth in 2025, strengthening its leadership across multiple semiconductor sectors.
Sunday, October 27, 2024
3D Ferroelectric NAND for Ultra-High Efficiency Analog Computing-in-Memory by SK hynix
3D FeNAND with Ultra-High Computing-in-Memory Efficiency: AI models containing up to trillions of parameters require substantial memory resources to handle the vast amounts of data. Energy-efficient analog computing-in-memory (CIM) devices such as 3D vertical NAND architectures are emerging as potential solutions because they offer high areal density and are non-volatile. SK hynix researchers will detail how they achieved analog computation in ultra-high-density 3D vertical ferroelectric NAND (FeNAND) devices for the first time. They used gate stack engineering techniques to improve the analog switching properties of 3D FeNAND cells, and achieved an unprecedented ≥256-conductance-weight levels/cell. The 3D FeNAND arrays improved analog CIM density by 4,000x versus 2D arrays, and demonstrated stable multiply-accumulate (MAC) operations with high accuracy (87.8%) and 1,000x higher computing efficiency (TOPS/mm2) versus 2D arrays. This work provides an efficient method to implement the processing of hyperscale AI models in analog CIM chips for edge computing applications, where speed and low power operation are the critical requirements, not extreme accuracy.
Above:
(1) is a comparison of 2D and 3D
arrays for analog-CIM applications.
(2) is a TEM analysis of the 3D FeNAND, showing (a) a top-down view
of the device; (b) a cross-sectional view at low magnification; (c) a cross-sectional
view at high magnification; and (d) a schematic illustration of the FeFET cells
in the 3D FeNAND array.
IEDM 2024 Paper #38.1, “Analog Computation in Ultra-High Density 3D FeNAND for TB-Level Hyperscale AI Models,” J.-G. Lee and W.-T. Koo et all, SK hynix https://www.ieee-iedm.org/press-kit
4F² DRAM developed by a Kioxia using ALD IGZO
The new 4F² DRAM developed by a Kioxia-led team combines gate-all-around (GAA) IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) with a unique design that places transistors above high-aspect-ratio capacitors to reduce thermal stress and suppress electrical interference like "row hammer." This structure increases memory density and efficiency, providing a high on/off current ratio essential for low-power operation. The team demonstrated a 275Mbit array with this technology, indicating its potential to enable high-density, low-power DRAM for advanced computing applications.
Kioxia is traditionally known for its expertise in NAND flash memory rather than DRAM. They are one of the leading companies in the NAND space, focusing primarily on storage solutions. However, this new venture into DRAM with innovative 4F² cell structures signals an expansion of their research and development scope, possibly to leverage their materials and process expertise in a closely related area. It suggests Kioxia may be exploring ways to diversify its technology portfolio, potentially addressing high-density memory needs beyond traditional NAND storage
ALD offers atomic-level precision and is beneficial for creating uniform, conformal layers of IGZO in complex, high-aspect-ratio surfaces demonstrated here, which is particularly advantageous in advanced semiconductor applications. ALD works by exposing the substrate to alternating pulses of indium, gallium, and zinc precursors, separated by purges to prevent unwanted reactions. This controlled process achieves a smooth and consistent IGZO layer with excellent thickness control, crucial for sensitive electronic applications like DRAM devices.
New Type of 4F2 DRAM: DRAM is the workhorse memory of electronic systems, but patterning the extremely small features of conventional silicon 6F2 DRAM memory cells and suppressing “row hammer” electrical interference from nearby cells are major challenges. To overcome them, the industry has been actively developing denser 4F2 DRAM designs made with different materials. A Kioxia-led team will describe a new type of 4F2 DRAM, comprising GAA IGZO (indium-gallium-zinc oxide) vertical channel transistors (VCTs) and a new integration scheme, where the heat-sensitive transistors are placed on the top of high aspect-ratio capacitors instead of on the bottom, to reduce the thermal impact from BEOL processing below. The vertical architecture also fully suppresses row hammer interference, because the active region isn’t shared with adjacent cells. The InGaZnO VCT achieved more than 15µA/cell ON current and 1aA/cell OFF current. The researchers demonstrated the technology by successfully building a 275Mbit array with it, demonstrating its potential for future high-density, low-power DRAM technologies.
Above:
(a) is a schematic of the oxide-semiconductor
channel transistor DRAM. The InGaZnO VCT was integrated on a capacitor array, a
different architectural scheme from silicon-based 4F2 DRAM devices.
(b) is a cross-sectional TEM image of
the InGaZnO VCT test structure, with the key technologies needed for DRAM
applications described on the right nearby. The gate oxide and InGaZnO were
formed in a 26nm-diameter vertical hole.
(c) is a cross-sectional TEM showing
the InGaZnO VCTs on high-aspect-ratio capacitors.
IEDM2024 Paper #6.1, “Oxide-Semiconductor Channel Transistor DRAM (OCTRAM) with 4F2 Architecture,” S. Fujii et al, Kioxia Corp./Nanya Technology Corp. https://www.ieee-iedm.org/press-kit
Saturday, October 26, 2024
Intel's Breakthrough in RibbonFET Transistor Scaling Demonstrates Silicon Viability for Future Nodes
TSMC 2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects
TSMC’s New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will unveil the world’s most advanced logic technology. It is the company’s forthcoming 2nm CMOS (i.e., N2), platform, designed for energy-efficient computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or 30% power reduction) at >1.15x chip density versus the most advanced logic technology currently in production, TSMC’s own 3nm CMOS (N3) platform, introduced in late 2022.
The new N2 platform features GAA nanosheet transistors; middle-/back-end-of-line interconnects with the densest SRAM macro ever reported (~38Mb/mm2); and a holistic, system-technology co-optimized (STCO) architecture offering great design flexibility. That architecture includes a scalable copper-based redistribution layer and a flat passivation layer (for better performance, robust CPI, and seamless 3D integration); and through-silicon vias, or TSVs (for power/signal with F2F/F2B stacking). The researchers say the N2 platform is currently in risk production and scheduled for mass production in 2H’ 25. N2P (5% speed enhanced version of N2) targets to complete qualification in 2025 and mass production in 2026.
Key Improvements:
- When shifting from 0.6V to 0.55V in the N3E architecture, there's a 15% reduction in speed but a 24% reduction in power.
- For N2, at 0.85V, there's a 14% reduction in speed and a 35% reduction in power compared to similar performance points in N3E.
- These efficiency improvements are essential for high-performance applications in power-sensitive environments.
Sources:
Tuesday, October 22, 2024
GM Ventures Invests $10 Million in Forge Nano to Boost EV Battery Technology with Atomic Armor
GM Ventures, the venture arm of General Motors, recently invested $10 million in Forge Nano, a materials science company known for its advanced battery technology. Forge Nano specializes in Atomic Layer Deposition (ALD), particularly its "Atomic Armor" technology, which enhances battery materials by applying ultra-thin coatings. This innovation improves the performance, lifespan, and charging speed of electric vehicle (EV) batteries.
“GM Ventures’ primary goal is to bring disruptive technology into the GM ecosystem to improve products and processes,” said Anirvan Coomer, managing director of GM Ventures. “Forge Nano’s Atomic Armor technology has game-changing potential for our battery materials at significant scale. They have already demonstrated the ability to expand cathode capabilities, which is the most expensive battery cell component. This could unlock benefits for customers and the business.”
The investment is part of GM's broader strategy to secure a robust supply chain for its EVs, and the partnership will focus on optimizing battery cathode materials to improve energy density and reduce costs. With this funding, Forge Nano aims to expand its battery coating operations and develop lithium-ion battery prototypes at its Colorado facility. This collaboration is expected to boost the range and fast-charging capabilities of GM’s future EV batteries.
About Forge Nano:
Forge Nano is a materials science company specializing in advanced surface engineering technology, particularly Atomic Layer Deposition (ALD). Its proprietary technology, "Atomic Armor," applies ultra-thin coatings at the atomic scale to improve the performance and durability of materials, particularly for energy storage applications like electric vehicle (EV) batteries. Forge Nano's coatings help enhance battery life, efficiency, and fast-charging capabilities by preventing corrosion and boosting cathode material performance.
Founded in Colorado, Forge Nano has attracted significant investment from major corporations, including General Motors, Volkswagen, LG, and others. The company's solutions extend beyond the automotive industry, targeting sectors such as electronics, aerospace, and defense. With ongoing innovation, Forge Nano aims to revolutionize how materials perform in critical technologies such as semiconductors and batteries.
Sources:
Tuesday, October 1, 2024
ASM launches 200 mm PE2O8 silicon carbide epitaxy system
Wednesday, September 25, 2024
Smoltek and SparkNano Unveil Breakthrough ALD Technology to Slash Iridium Usage in Green Hydrogen Production by 95%
“With our carbon nanofibers and their ALD coating technology, we can together lower costs and reduce the use of rare precious metals and make green hydrogen available on a large scale”, says Fabian Wenger, Head of R&D at Smoltek Hydrogen.
Tuesday, September 17, 2024
Technological Innovations in Semiconductor Manufacturing: Insights from Tokyo Electron's 2024 Integrated Report
Friday, September 13, 2024
Material Export Restrictions Poised to Strain Semiconductors
AlixLabs Qualifies APS™ for Use In 300-millimeter Silicon Wafer Designs
AlixLabs' patented and wordmarked APS™ IP – short for Atomic Layer Etch (ALE) Pitch Splitting, here demonstrated in a simple animation.
“Proving that APS™ works on lithography designs on 300-millimeter wafers, is what we’ve all worked on since we founded AlixLabs in 2019,” says CEO and co-founder Dr. Jonas Sundqvist. “Not only do we aim to provide chip manufacturers wafer processing equipment that can create 20-nanometer half-pitch lines and critical dimension below 15 nanometers on silicon, we aim to do that at a lower cost and a more sustainable way than other technologies”
“We are also able to provide record breaking 3-nanometer critical dimension features on gallium phosphide (GaP) wafers today showing that APS™ can scale far into the future beyond what is needed today,” adds CTO and co-founder Dmitry Suyatin.
Monday, September 9, 2024
New Export Controls on ALD, ALE and ASD Technologies Effective September 2024 to Safeguard National Security
The US Bureau of Industry and Security (BIS) is introducing* stringent export controls targeting advanced technologies essential to national security, particularly within the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new and revised Export Control Classification Numbers (ECCNs) and specific restrictions on critical equipment and materials, such as those involved in Gate-All-Around Field-Effect Transistor (GAAFET) technology, Atomic Layer Etching (ALE), and Atomic Layer Deposition (ALD). The controls aim to safeguard U.S. technological leadership while harmonizing with international export control standards. Specific restrictions apply to high-precision wafer processing equipment and isotopically enriched materials used in quantum computing, reflecting the critical importance of these technologies. These measures ensure that while international collaboration continues, sensitive technologies remain protected under national security protocols.
BIS has introduced new export controls focused on advanced technologies, particularly in the semiconductor, quantum computing, and additive manufacturing sectors. These controls include new Export Control Classification Numbers (ECCNs), revisions to existing ones, and the addition of new license exceptions for countries with similar technical controls. This rule aims to protect national security and advance foreign policy objectives by aligning U.S. export controls with those of international partners. The controls cover a wide range of items, including quantum computing technologies and semiconductor manufacturing equipment, reflecting the critical importance of these technologies to national security. The rule is effective immediately, though there are delayed compliance dates for certain items, allowing businesses time to adjust to the new requirements.
BIS has also established a framework to differentiate between items controlled multilaterally and those controlled through Implemented Export Controls (IEC), which are harmonized with international partners. The new regulations include provisions for annual reporting, particularly concerning the deemed export of quantum technology and software, highlighting the global nature of innovation in these fields. The rule is designed to support U.S. technology leadership while ensuring that export controls do not impede international collaboration, particularly in areas like quantum computing, where global expertise is crucial. Comments on the rule and its potential impact on supply chains and compliance programs are invited, with a focus on refining the scope and clarity of the new ECCNs and license exceptions.
BIS specifies that the restrictions on GAAFET (Gate-All-Around Field-Effect Transistor) technology primarily focus on the "technology" required for the "development" or "production" of GAAFET structures. This includes process recipes and other detailed specifications necessary for fabricating these advanced semiconductor devices. These restrictions are captured under ECCN 3E905, which applies to the "technology" for GAAFETs but does not extend to vertical GAAFET architectures used in 3D NAND. The export, reexport, or transfer of this technology to certain countries requires a license due to its national security and regional stability implications. However, the rules include specific exceptions for existing collaborations and provisions for continued access under certain conditions.
The specific wafer processing technologies restricted for export include:
Dry Etching Equipment:
Equipment designed for isotropic dry etching, as well as anisotropic etching of dielectric materials. These include technologies that enable the fabrication of high aspect ratio features, with aspect ratios greater than 30:1 and a lateral dimension on the top surface of less than 100 nn.
The specific restrictions on Atomic Layer Etching (ALE) equipment are detailed under the export control regulations. The BIS has imposed controls on equipment designed or modified for anisotropic dry etching, which includes certain types of ALE equipment. These tools, particularly those using RF pulse-excited plasma, pulsed duty cycle excited plasma, and other advanced techniques, are now restricted due to their critical role in the precise fabrication of high-performance semiconductor devices. The restrictions apply to ALE equipment that is capable of producing high aspect ratio features, which are essential for advanced semiconductor manufacturing, making these tools subject to national security and regional stability controls .
Deposition Technologies:
Equipment designed for the selective bottom-up chemical vapor deposition (CVD) of tungsten fill metal, and other deposition processes such as those for tungsten nitride, tungsten, and cobalt layers. This also includes atomic layer deposition (ALD) equipment designed for area selective deposition of barriers or liners.
The restrictions on Atomic Layer Deposition (ALD) equipment are focused on several key types of equipment essential for advanced semiconductor manufacturing. Specifically, ALD equipment designed for area-selective deposition of barriers or liners using organometallic compounds is controlled. This includes equipment capable of area-selective deposition (ASD) that enables fill metal contact to an underlying electrical conductor without a barrier layer at the fill metal via interface to the conductor. Additionally, ALD equipment designed for depositing tungsten (W) to fill interconnects or channels less than 40 nm wide is also restricted. These restrictions are imposed due to the critical role these technologies play in the precision required for the fabrication of next-generation semiconductor devices.
These technologies are controlled under ECCNs (Export Control Classification Numbers) such as 3B001 and related classifications, and are subject to national security (NS) and regional stability (RS) controls.
The specific materials, chemicals, or precursors that are being restricted under the new export controls include:
These restrictions reflect the importance of controlling advanced materials that play a crucial role in emerging technologies, particularly those with significant national security implications, i.e., quantum technologies.
Epitaxial Materials: This includes materials with at least one epitaxially grown layer of silicon or germanium containing a specified percentage of isotopically enriched silicon or germanium. These materials are controlled due to their critical role in developing spin-based quantum computers.
Fluorides, Hydrides, Chlorides: Specific chemicals of silicon or germanium that contain a certain isotopic composition are also restricted. These chemicals are essential in semiconductor manufacturing processes, particularly in the development of quantum technologies.
Silicon, Silicon Oxides, Germanium, or Germanium Oxides: These materials, when isotopically enriched, are restricted due to their applications in quantum computing and other advanced technologies. The control extends to various forms such as substrates, lumps, ingots, boules, and preforms .
* The new export controls introduced by the Bureau of Industry and Security (BIS) are effective as of September 6, 2024. However, there are delayed compliance dates for certain items, allowing businesses until November 5, 2024, to comply with the new requirements, particularly for specific quantum technologies and related equipment. This delayed compliance is intended to give affected parties time to adjust to the new regulations.
Source:
Monday, September 2, 2024
Rising Prices of Critical Metals Highlight Their Importance in Semiconductor Manufacturing Amid Global Supply Challenges
Germanium, gallium, and antimony are crucial to the semiconductor industry due to their unique electrical properties that make them essential for producing advanced electronic components. Germanium is used as a semiconductor material, particularly in high-speed electronics and fiber optics, due to its excellent ability to efficiently transmit electrical signals. Gallium, often used in the form of gallium arsenide, is vital for producing high-performance chips, LEDs, and solar cells because it can operate at higher frequencies and temperatures than silicon. Antimony is used in creating semiconducting alloys and compounds that improve the efficiency and performance of devices like diodes and infrared detectors. These materials are key to advancing the capabilities of modern electronics, making them indispensable in the production of next-generation technologies.
The prices of rare earth metals, essential for semiconductor manufacturing, have more than doubled in the past year following China's retaliation against U.S. semiconductor restrictions. Notably, China's export restrictions on metals like germanium and gallium have caused significant price hikes, with germanium seeing a 115% increase to $2,600 per kilogram, up from $1,200 in the first quarter of 2023. Gallium prices have also surged by 75%, rising from around $300 per kilogram at the beginning of 2024 to approximately $530 today. These price increases reflect China's strategic control over these critical materials in response to global trade tensions.
The situation is expected to worsen, with no signs of price relief on the horizon. Starting October 1, 2024, all rare earth metals in China will be effectively under state control, and the export of gallium and germanium has required a license since August 2023. China's tightening grip on these minerals is seen as a powerful tool to counter U.S. efforts to impede its advancement in semiconductor production. Currently, China dominates the global supply of these materials, producing 94% of the world's gallium and 73% of germanium in 2023, and its export volumes have reportedly dropped by up to 50% since the restrictions were imposed.
China's export restrictions on critical metals may impact US and European industries by causing supply shortages and driving up costs in the semiconductor and electronics sectors. These disruptions can slow production and raise consumer prices. Additionally, the restrictions may force companies to seek alternative, potentially more expensive, sources, straining global supply chains and weakening the competitive position of US and European industries.
Sources:
China Warns Japan Over Semiconductor Export Curbs as US Pressure and Economic Tensions Mount
China has issued strong warnings to Japan against imposing new restrictions on the sale and servicing of chipmaking equipment to Chinese firms, in response to pressure from the United States. The US is seeking to align Japan with its own restrictive measures aimed at curbing China’s semiconductor advancements. Japan is concerned about potential retaliation from China, particularly the possibility that China might cut off access to critical minerals essential for its automotive industry, which could severely impact companies like Toyota. This echoes past instances where China restricted exports of rare earths to Japan during diplomatic tensions.
The US is also considering more stringent restrictions on chipmaking tools and high-bandwidth memory chips, crucial for AI development, as part of its broader strategy to limit China's technological progress. However, the US has so far refrained from using the foreign direct product rule (FDPR) against Japan, a powerful measure that could control sales of products worldwide if they use any American technology. While diplomatic efforts continue, the situation is complicated by upcoming political changes in Japan and the US, with Japan seeking to ensure its supply chain security while managing pressure from both China and the US.
China's heavy reliance on Japan for crucial semiconductor materials and equipment, such as high-end photoresists and wafer processing tools, significantly complicates its stance in the ongoing tech war with the US and Japan. Four Japanese companies—JSR, Tokyo Ohka Kogyo, Shin-Etsu Chemical, and Fujifilm Electronic Materials—dominate the global market for advanced photoresists, holding about 70% of the market share, making China highly dependent on them despite efforts to develop its own production capabilities. Additionally, Japan's Tokyo Electron, Screen Holdings, Nikon, Kokusai, and Lasertec are key suppliers of semiconductor wafer processing equipment to China. Japanese chemical companies, such as ADEKA Corporation, JSR Corporation, and Mitsui Chemicals, are key suppliers of CVD and ALD precursors. These companies produce a range of specialized chemicals used in semiconductor manufacturing, including organometallic precursors, silanes, and other complex compounds essential for deposition processes.
Japan's exports rose 5.4% year-on-year in June, cooling from 13.5% growth in May and underscoring concerns that a slowdown in China may hamper Japan's trade-reliant economy. The trade balance came to a surplus of 224.04 billion yen.
This dependency on Japanese technology and materials puts China in a vulnerable position as Japan faces increasing pressure from the US to align with stricter export controls, further raising the stakes in the ongoing geopolitical and economic tensions.
Sources
China Warns Japan of Retaliation for Possible New Chip Curbs - Bloomberg
Japan export growth cools amid worries about China slowdown | ReutersSaturday, August 31, 2024
Breakthrough by Japanese Researchers - Block Copolymer Enables Ultra-Fine Semiconductor Patterns with 7.6 nm Half-Pitch
Scientists at Tokyo Institute of Technology and Tokyo Ohka Kogyo have developed a novel block copolymer (BCP) that could significantly advance semiconductor manufacturing by enabling finer circuit patterns through directed self-assembly (DSA). This new BCP, derived from a chemically tailored version of polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA), self-assembles into lamellar structures with a half-pitch size of just 7.6 nanometers. This surpasses the capabilities of conventional BCPs, which struggle to achieve sub-10 nm features, and represents one of the smallest reported half-pitch sizes in the world for thin-film lamellar structures.
a Schematic of the DSA process using a PS-b-PGFM on a chemically patterned Si substrate. AFM phase images of a b PS-b-PGFM19-23 film on an NL35-modified DSA substrate (Ls = 90 nm) after annealing at 240 °C for 5 min, c PS-b-PGFM19-10 film on an NL38-modified DSA substrate (Ls = 84 nm) after annealing at 230 °C for 5 min, and d PS-b-PGFM18-11 film on an NL38-modified DSA substrate (Ls = 90 nm) after annealing at 230 °C for 5 min. All thin films are 19-nm thick and were etched using O2 plasma for 10 s prior to AFM.
The research, published in *Nature Communications*, highlights the potential of this new BCP to push the boundaries of miniaturization in electronics, which is crucial for the continued advancement of semiconductor technology. The tailored copolymer, PS-b-PGFM, exhibits reliable and reproducible self-assembly into extremely small nanometric patterns, making it a promising template for lithographic processes. As the demand for smaller feature sizes in semiconductor devices grows, this breakthrough could pave the way for next-generation Logic and Memory components that all need to continuously scale to smaller critical dimensions.
Sources: