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At its 2024 Investor Day, ASML projected annual revenue of €44 billion to €60 billion with gross margins of 56% to 60% by 2030, driven by double-digit growth in EUV lithography spending for Logic and DRAM, AI-driven semiconductor demand, and scalable EUV technology enabling cost-effective solutions for advanced nodes.
(Full video available here: Investor Day 2024)
DRAM scaling is undergoing a transformation fueled by the adoption of EUV lithography and the architectural shift to 3D DRAM, spearheaded by industry leaders Samsung, SK Hynix, and Micron. EUV lithography extends traditional DRAM scaling, enabling smaller cell sizes and higher densities. Micron plans to integrate EUV into DRAM production by 2025, marking a significant step toward cost-effective scaling. Samsung and SK Hynix are pioneering 3D DRAM architectures, which stack memory cells vertically to enhance density, performance, and energy efficiency. Samsung aims to commercialize 3D DRAM by 2030, while SK Hynix is targeting 2027-2028 for the introduction of vertical channel transistors (VCTs) with compact 4F² cell designs. These advancements represent a leap forward, with EUV lithography ensuring 2D scaling and 3D DRAM addressing physical and economic scaling limitations, paving the way for higher capacities and improved performance.
The progress and benefits of High-NA EUV lithography, with over 10,000 wafers exposed, including 1,300 DRAM and foundry customer wafers, and a target of 2,000 wafers by the end of 2024. Leading semiconductor companies like Micron, Intel, Samsung, SK Hynix, TSMC, and IBM are leveraging High-NA systems to enhance precision and scaling. Mark Philips from Intel highlights the readiness of High-NA EUV with robust tool availability and ecosystem support, enabling advancements like RibbonFETs, PowerVia, and "6x12" masks, which offer 23-50% productivity improvements over previous platforms. These developments underscore the role of High-NA EUV in enabling cost-effective scaling for DRAM and logic manufacturing.
ASML is pivotal in advancing EUV lithography for DRAM manufacturing. By 2024, memory manufacturers such as Samsung and SK Hynix had begun integrating EUV into production to enhance patterning precision and enable further scaling. ASML’s High-NA EUV systems, like the TWINSCAN EXE:5000, are expected to be production-ready by 2025, meeting stringent requirements for higher density and performance in memory technologies. Collaborations like the High-NA EUV Lithography Lab with imec have successfully demonstrated patterning for DRAM and logic structures, showcasing readiness for high-volume manufacturing by 2025-2026.
EUV lithography spending for DRAM is projected to grow at a CAGR of 15-25% through 2030. This growth is driven by the adoption of EUV for enhancing patterning precision and enabling further scaling in DRAM manufacturing. Key advancements include the integration of High-NA EUV systems, like ASML’s TWINSCAN EXE:5000, which is expected to be production-ready by 2025. These technologies support the development of 2D scaling and the transition to 3D DRAM architectures, addressing the physical and economic scaling challenges. Industry leaders Samsung, SK Hynix, and Micron are at the forefront of these efforts, incorporating EUV to achieve smaller cell sizes, higher densities, and improved energy efficiency.
Obviously, advanced logic drives EUV adoption. Spending in this sector is expected to grow at a CAGR of 10-20% through 2030, with High-NA systems playing a critical role in scaling logic nodes. Meanwhile, NAND benefits from advanced lithography solutions addressing the complexity of 3D NAND structures. Though it relies heavily on deposition and etch technologies, advanced DUV and EUV systems provide critical support for these applications.
The global semiconductor market is expected to grow significantly, driven by factors such as AI, high-performance computing, and 5G, which are fueling demand for advanced chips. Semiconductor sales are projected to reach $1 trillion by 2030, supported by the rapid adoption of AI technologies, growing automotive semiconductor needs for electric and autonomous vehicles, and the expansion of 5G networks and connected devices. Additionally, exponential growth in data generation is driving demand for robust data storage solutions, while continuous innovations in manufacturing, such as EUV lithography, enable smaller and more efficient chips.
The global semiconductor market is expected to grow significantly, driven by AI, high-performance computing, and 5G. Sales are projected to reach $1 trillion by 2030, with wafer demand growing by 780,000 wafer starts per month annually. Strategic considerations, including geopolitical factors, are adding 5-8% extra wafer capacity by 2030. China’s role in the semiconductor industry remains vital, as the country invests heavily in advanced technologies to strengthen its manufacturing capabilities. However, due to export restrictions, China does not have access to ASML's EUV lithography tools. Instead, Chinese manufacturers focus on DUV technology and other innovative approaches to enhance their capabilities in advanced logic and DRAM production. Despite these limitations, China’s expanding wafer capacity contributes significantly to global growth projections, ensuring its relevance in the industry. The region’s efforts to integrate cutting-edge technologies, supported by partnerships with global leaders, highlight its ambitions to remain competitive and innovative in the semiconductor market.
ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030. Holistic lithography also plays a critical role in supporting front-end 3D integration by ensuring overlay control throughout pre-bonding, bonding, and post-bonding processes. Pre-bonding achieves <5 nm overlay error using scanner and offline metrology for correction and control, while bonding addresses large wafer deformation with extensive metrology (50-100 nm overlay error with over 5000 measurements per wafer). Post-bonding refines overlay error to <5 nm with over 2000 measurements per wafer, leveraging scanner actuators and lithography adjustments to bring errors within specifications.
ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030.
In conclusion, ASML’s strategy leverages its installed base, drives EUV and DUV advancements, and capitalizes on AI-driven demand. With projected annual revenue of €44-60 billion by 2030 and gross margins between 56% and 60%, ASML remains at the forefront of semiconductor innovation, enabling transformative progress in DRAM, logic, and NAND technologies.
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