In the first 10 days of August 2024, South Korea's exports increased by 16.7% year-on-year, reaching $15.5 billion, driven primarily by a significant 42.1% surge in semiconductor exports. Other sectors like petroleum products and automobiles also saw growth, with automobile exports rising sharply by 63.9%. However, machinery product exports declined by 10.6%. Imports grew by 13.4% to $18.4 billion, resulting in a trade deficit of $2.9 billion. Notably, exports to major trading partners China and the United States increased by 10.7% and 27.7%, respectively. This continues a trend of export growth, marking the tenth consecutive month of gains as of July.
SK hynix has announced it will begin mass production of its 6th generation (1c) 10nm class DRAM in the third quarter of 2024, ahead of Samsung Electronics, which plans to start production by the end of the year. SK hynix has already established an internal road map to achieve customer certification and start production, potentially positioning itself to capture significant demand from major tech companies like Amazon and Microsoft once Intel certifies its DRAM for server use. The 6th generation DRAM, utilizing advanced Extreme Ultraviolet (EUV) lithography, promises higher chip yields and improved power efficiency compared to previous generations.
Samsung has confirmed its investment in the Pyeongtaek P4 plant for the production of 6th-generation 1c DRAM, with plans to begin mass production in June 2025. This next-generation DRAM, which uses 10nm-class technology, is still not commercialized globally, but Samsung and SK hynix are preparing for its mass production. Despite initial delays due to a downturn in the semiconductor market, Samsung is now expanding its P4 facility, initially installing NAND flash equipment and confirming plans for 1c DRAM production. The company also anticipates launching HBM4 using 1c DRAM by the second half of 2025, aligning with forecasts of significant growth in the memory industry's revenues.
Both Samsung and K Hynix plans to adopt Inpria's metal oxide resist (MOR) technology in the production of 1c DRAM, utilizing MOR to draw the finest lines on one of the five to six EUV layers in the 1c DRAM. This adoption aims to enhance performance and reduce costs in future DRAMs. MOR is seen as a next-generation alternative to the chemically amplified resist (CAR) currently used in advanced chip lithography, addressing CAR's limitations in resolution, etching resistance, and line edge roughness.
In 2021, JSR Corporation announced its acquisition of Inpria Corporation, the leading innovator in metal oxide photoresist technology for EUV lithography, solidifying its focus on advancing semiconductor materials.
Samsung is considering multiple suppliers for its EUV MOR photoresist needs beyond Inpria, including companies like Dupont, Dongjin Semichem, and Samsung SDI. These alternatives are currently being tested as the company explores the best options for its 1c DRAM production.
Lam Research refers to its inorganic photoresist technology as "dry resist," which reportedly is expected to be supplied for Gen 7 10nm (1d) DRAM production, anticipated to launch next year. This dry resist is deposited by ALD and represents a further evolution in PR technology, potentially offering enhanced performance for the next generation of DRAM manufacturing.
PFAS elimination efforts expected to drive migration to photoresist alternatives
San Diego, CA, August 8, 2024: TECHCET— the electronic materials advisory firm providing business and technology information —is forecasting semiconductor photoresist revenues to increase by nearly 11% in 2024. Overall semiconductor market recovery is expected in 2024, particularly in the second half, which should drive increased demand for all resists. In parallel, photoresist ancillaries are expected to increase by around 10%, and extensions by around 9%. More details on photoresist volume and revenue forecast by material can be found in TECHCET's new Lithography Materials Critical Materials Report™.
Recent pushes in the EU and US to eliminate PFAS-related chemicals are expected to gradually impact future photoresist material compounds. Photoresists that use photoacid generating (PAG) compounds have been qualified and used for many years, making it challenging to switch away to alternatives. While numerous companies and universities are working to develop non-PFAS-related PAGs, current performance is not yet meeting all process requirements. Consequently, defining suitable non-PFAS PAG alternatives and transitioning effectively is expected to take 5-10 years.
The newly released TECHCET Critical Materials Reports™ on Lithography Materials contains details on market and technology trends and supplier profiles. For the full table of contents or to request a sample report, visit https://lnkd.in/esXU6SW
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In an era of significant technological and geopolitical changes, ASML, the number one player in the semiconductor industry, stands at a crossroads. The forthcoming retirement of Martin van den Brink and Peter Wennink, who have jointly steered ASML for over a decade, signals the end of a dynamic period. Van den Brink's leadership in technology development propelled ASML to unparalleled heights in the lithography sector, while Wennink’s diplomatic and financial acumen solidified its market dominance. ASML's impact extends beyond technology; it has become a geopolitical force, enhancing the Netherlands and Europe's strategic significance in global politics.
The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law.
As ASML approaches its 40th anniversary in April 2024, it confronts a changing landscape. The company has weathered various phases – from early struggles to market leadership, marked by innovations like the PAS 5500 and immersion lithography. Under Van den Brink, ASML prioritized technological advancement, often at the expense of other factors like reliability.
The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. The shift in focus from chip performance to system-level advancements requires a nuanced approach. Additionally, as technology matures, reliability and predictability become crucial for maintaining ASML's competitive edge.
The transition from a "firefighter" engineering culture to one emphasizing process and reliability won't be easy. Fouquet must balance innovation with operational efficiency, ensuring ASML remains responsive to market and geopolitical dynamics. This requires a departure from the legacy of Van den Brink, focusing instead on a holistic, structured approach to development and engineering.
Fouquet's tenure will be pivotal in shaping ASML's future. His leadership must navigate the complexities of a highly competitive industry, geopolitical pressures, and the evolving technological landscape. The challenge lies in fostering a culture that values reliability and process without stifling the innovative spirit that has been ASML's hallmark. As the company moves into its fifth decade, its ability to adapt and evolve under Fouquet's guidance will determine its continued success in a rapidly changing world.
Advancing the Microchip Revolution: EUV Lithography's Challenges and Future Outlook
Extreme Ultraviolet (EUV) lithography represents a significant advancement in semiconductor manufacturing, enabling the production of more compact and efficient integrated circuits, particularly for 7 nm Logic process nodes and below and leading edge DRAM. This technology, developed and marketed primarily by ASML Holding, uses a highly specialized process involving laser-pulsed tin droplet plasma to etch patterns onto substrates at the 13.5 nm wavelength scale. The progression from early prototypes to more efficient models has been remarkable, with modern EUV systems capable of handling 200 wafers per hour, a substantial improvement from initial prototypes.
Looking into the future, EUV lithography is expected to play a critical role in advancing semiconductor technology, especially as the demand for smaller and more powerful chips increases. However, several technological challenges need addressing continiously to fully harness EUV's potential:
1. Optical Component Durability: The EUV process requires highly specialized and sensitive optical components, including mirrors and photomasks. These components are prone to degradation from exposure to high-energy photons and contaminants. Improving their durability and developing efficient cleaning and maintenance processes are crucial.
2. Throughput Efficiency: While significant improvements have been made, further enhancing the throughput of EUV systems is vital. This includes reducing setup times, increasing the speed of the lithography process, and minimizing downtime due to maintenance or component replacement.
3. Pattern Fidelity and Defect Reduction: As circuit patterns become increasingly smaller, maintaining pattern fidelity and reducing defects is challenging. This involves improving the resolution of EUV systems, enhancing photoresist materials to better respond to EUV exposure, and developing more effective methods to mitigate the impact of secondary electrons generated during the lithography process.
EUV Lithography - Balancing Technological Advancements with Energy Challenges
EUV lithography, pivotal in advanced semiconductor manufacturing, faces significant energy consumption challenges. The generation of EUV light, typically via laser-pulsed tin plasma, is inherently energy-intensive. Additionally, maintaining the necessary vacuum environment and cooling systems for these high-precision machines further escalates energy use. As EUV technology becomes more prevalent, especially for producing smaller, more efficient chips, optimizing energy efficiency is critical. Future developments are expected to focus on more efficient light sources, improved system design for energy conservation, and advanced thermal management, aiming to reduce the overall energy footprint of EUV lithography processes.
The semiconductor industry, traditionally known for its high environmental impact, is increasingly embracing sustainability. With the global demand for semiconductors rising, manufacturers face the challenge of scaling up production while addressing substantial water and electricity usage and managing hazardous waste from gases used in manufacturing. Historically, the focus has been on balancing power, performance, and cost. Recently, however, sustainability has emerged as a crucial consideration, with many facilities actively working to decarbonize their supply chains and reduce overall environmental impact (data from imec)
EUV Lithography's Hydrogen Demand: A Growing Concern in Chip Manufacturing
EUV Lithography, also raises concerns regarding its significant hydrogen consumption. The EUV process relies heavily on hydrogen gas to maintain the cleanliness of the optical elements, particularly for preventing tin deposition on the mirrors. The need for a continuous supply of hydrogen to facilitate this cleaning process contributes to the overall operational costs and resource demands of EUV systems. As EUV technology becomes more widespread in chip manufacturing, addressing the sustainability and efficiency of hydrogen usage will be essential, both from an environmental and economic perspective.
In EUV lithography, managing hydrogen usage presents distinct challenges. The technology requires hydrogen for removing contaminants from critical mirrors, demanding systems capable of handling high volumes while maintaining vacuum integrity. This necessity places a premium on innovative system designs that minimize the footprint and energy consumption associated with hydrogen management, directly impacting the cost and efficiency of semiconductor manufacturing. Safety considerations, given hydrogen's flammability, are paramount. Advanced, fuel-free hydrogen management strategies are employed to ensure safety and environmental compliance. These strategies focus on reducing flammability risks and eliminating the need for additional fuels, thereby minimizing carbon emissions and contributing to sustainable manufacturing practices.
Continued research and development in these areas are essential for the advancement of EUV lithography, ensuring it meets the rapidly evolving demands of the semiconductor industry.
2023 update to IRDS roadmap reminds key EUV issues.
1. EUV dose triples every four nodes => increasing electron blur? 2. EUV cannot replace multiple patterning, even with higher NA.https://t.co/hZzkfKGfyr
Ushio, Inc. have announced a significant strategic partnership, marking a new era in digital lithography technology. This collaboration aims to spearhead the transition to heterogeneous chiplet integration on large substrates like glass, a move crucial for advancing Artificial Intelligence (AI) computing capabilities.
This new digital lithography system, pioneered by Applied Materials and Ushio, is tailor-made for patterning advanced substrates vital in the AI era. With the growing demand for AI workloads, there's an increased need for larger, more functional chips. Traditional methods can't keep up with AI's performance requirements, hence the shift to heterogeneous integration (HI) techniques. These involve combining multiple chiplets in an advanced package, offering performance and bandwidth comparable to monolithic chips.
The partnership leverages Applied Materials' expertise in large substrate processing and Ushio's experience in lithography for packaging. Dr. Sundar Ramamurthy from Applied Materials highlights the new Digital Lithography Technology (DLT) as a game-changer for customers' advanced substrate roadmaps. William F. Mackenzie of Ushio emphasizes their long-standing experience in lithography systems and their commitment to this new venture.
The DLT system stands out as the only technology capable of achieving the necessary resolution for advanced substrate applications while maintaining high-volume production throughput. It can pattern line widths less than 2-microns, allowing unprecedented area density for chiplet architectures on various substrates, including glass.
Applied Materials is responsible for R&D and creating a scalable roadmap for the DLT system, aiming to push innovation in advanced packaging to 1-micron line widths and beyond. Ushio will use its established manufacturing and customer infrastructure to facilitate the technology's adoption.
While this announcement is forward-looking and subject to the usual risks and uncertainties of the tech industry, it heralds a new chapter in computing technology, potentially transforming the landscape of high-performance computing in the AI era.
- Applied Materials, Inc. is a leader in materials engineering solutions, essential in producing new chips and advanced displays worldwide.
- Ushio, Inc., established in 1964, specializes in manufacturing and selling various light sources and optical equipment, with a significant presence in industrial processes and visual imaging.
For more information or media inquiries, contact Ricky Gradwohl for Applied Materials and the Corporate Communication Department for Ushio.
In 2023, ASML, the leading semiconductor lithography equipment supplier, is set to achieve remarkable success, outpacing its rivals and emerging as the number 1 provider of Wafer Fabrication Equipment. Boasting an impressive 30% revenue growth forecast for the year, ASML is thriving amidst an industry landscape marked by its consistent performance. With a substantial backlog of cutting-edge Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems and surging demand from China, ASML's growth continues despite hurdles like supply chain disruptions and regulatory changes, ASML remains a beacon of innovation and resilience in the semiconductor sector.
By Abhishek Kumar Thakur and Jonas Sundqvist
ASML, a leading supplier of semiconductor equipment, is poised for a significant year in 2023, projected to surpass Applied Materials (AMAT) as the top provider of Wafer Fabrication Equipment. This achievement is attributed to ASML's robust revenue growth, expected to reach a remarkable 30% increase in 2023, while Applied Materials faces a decline of 20% according to Seeking Alpha*. ASML's success can be attributed to a substantial backlog of Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems, driven by heightened demand in China.
* Fact check: Due to strong DUV revenue and despite the increased uncertainties, ASML expects strong growth for 2023 with a net sales increase towards 30% and a slight improvement in gross margin, relative to 2022. ASML Holding revenue for the twelve months ending June 30, 2023 was $27.293B, a 25.97% increase year-over-year. AMAT revenue is estimated to increase by 2.6% to 26.33 B.Meaning ASML would pass bu end of 2023.
Despite facing challenges like supply chain disruptions and a factory fire, ASML has consistently ranked among the top three semiconductor equipment suppliers since 2017. Their backlog of EUV systems, combined with growing acceptance of DUV tools, contributes to their strong performance.
However, potential headwinds include supply chain concerns, past issues like the Berlin factory fire, and looming sanctions affecting exports to China. While ASML has addressed some challenges, the possibility of US sanctions in 2024 poses a threat to its growth.
Furthermore, ASML now faces new export controls imposed by the Netherlands, impacting shipments to China. While the company downplays these controls' immediate financial impact, they are expected to affect specific DUV systems, adding to global efforts to limit China's semiconductor advancements.
In this volatile landscape, ASML's ability to adapt to evolving regulations and maintain its technological leadership will be crucial. The impact of these restrictions, especially on shipments to China, could influence the company's growth trajectory in the semiconductor industry. Despite these challenges, ASML remains a prominent player with significant potential in the semiconductor equipment market.
ASML is set to deliver the industry's first High-NA extreme ultraviolet (EUV) lithography scanner by the end of 2023, marking a significant development for advanced chip manufacturing. The Twinscan EXE:5000 pilot scanner with a 0.55 numerical aperture (NA) will enable chipmakers to explore High-NA EUV technology. This innovation is crucial for achieving an 8nm resolution, suitable for manufacturing technologies beyond 5nm nodes. Intel is expected to be the first customer, but integration and adoption details are still uncertain. This advancement requires substantial investments, with reports suggesting costs of $300-400 million per unit.
To add some colour, initially, Intel had plans to employ ASML's High-NA tools for its 18A (1.8 nm) production node, scheduled for high-volume manufacturing in 2025, aligning with ASML's Twinscan EXE:5200 delivery. However, Intel accelerated its 18A production, moving it to the latter part of 2024. This change in strategy involved the use of ASML's Twinscan NXE:3600D/3800E with two exposures and Applied Material's Endura Sculpta pattern-shaping system. The objective was to reduce reliance on EUV double patterning techniques. Applied Materials' Centura Sculpta is a pattern-shaping machine equipped with a unique algorithm that can manipulate patterns produced by an EUV scanner. It has the capability to stretch these patterns in a user-defined direction along the X-axis. This process effectively reduces the space between features and enhances pattern density. This means that moving ahead ASML and Applied Materials are entering an interesting competitive space previously not encountered.
ASMLs Products
As an background, ASML specializes in the production of cutting-edge lithography systems crucial for semiconductor manufacturing. Their product portfolio includes the following key offerings:
Extreme Ultraviolet (EUV) Lithography Machines: ASML's EUV lithography machines are at the forefront of semiconductor manufacturing technology. These machines use extremely short wavelengths of light to create intricate patterns on silicon wafers, enabling the production of advanced and smaller semiconductor chips. EUV technology is essential for next-generation processors and memory chips.
Deep Ultraviolet (DUV) Lithography Machines: DUV lithography systems are another vital component of ASML's product lineup. They use longer wavelengths of light compared to EUV and are employed for a wide range of semiconductor applications, including memory and logic chip production. ASML's DUV systems are known for their precision and reliability.
TWINSCAN Series: Within the DUV lithography category, ASML offers the TWINSCAN series, which includes machines like the TWINSCAN NXT:2000i, NXT:2050i, and NXT:2100i. These systems are designed for immersion lithography, where the wafer and the lens are submerged in a liquid, enhancing precision and resolution.
EUV High Numerical Aperture (NA) Systems: ASML has been advancing its lithography machines by increasing the numerical aperture (NA), a key parameter that affects resolution. High-NA systems are capable of printing even smaller features on semiconductor wafers, enabling the production of highly advanced chips.
ASML's lithography machines are considered critical infrastructure for semiconductor manufacturing, and the company's technological leadership in this area has positioned it as a dominant player in the industry. The company's ability to innovate and adapt its lithography systems to meet the ever-increasing demands of semiconductor manufacturers has been a key factor in its success and growth prospects. However, the recent export controls and geopolitical pressures, particularly concerning shipments to China, introduce additional challenges and uncertainties for ASML and its specialized products.
Revolutionizing fabrication, Directed Self-Assembly (DSA) innovates micro to nano devices and materials. It leverages block co-polymer morphology for precise patterns and guides micro/nano particles, enhancing manufacturing. In semiconductors, DSA addresses lithography challenges, while Imec's research showcases DSA-EUV synergy for defect-free outcomes. Complex rectification processes, illustrated by Imec, spotlight improved Critical Dimension Uniformity and Pattern Placement Error control. As DSA advances, its collaboration with EUV promises precision, efficiency, and innovation across industries.
DSA has emerged as a groundbreaking technique for mass-producing micro to nano devices and materials with precision and efficiency. This method harnesses the inherent properties of materials to assemble them into intricate structures, revolutionizing manufacturing processes across various industries.
DSA leverages block co-polymer morphology to create patterns, enhancing feature control and shape accuracy. This involves guiding the assembly of micro and nano particles to achieve desired structures, made possible by the precise control of surface interactions and polymer thermodynamics. The key advantage of DSA is its ability to create structures at remarkably small scales, enabling advancements in diverse fields.
In the semiconductor industry, DSA offers a new perspective on lithography challenges. Despite initial setbacks, DSA is being revisited to address critical issues such as stochastic defects in extreme ultraviolet (EUV) lithography. These defects, which can contribute significantly to patterning errors, have led semiconductor manufacturers to explore DSA as a solution to rectify these problems. Notably, DSA is not replacing traditional methods but rather enhancing them. It is being integrated with existing manufacturing processes to enable increased resolution and precision, all while reducing costs.
However, challenges persist in integrating DSA into high-volume manufacturing. Defect control remains a primary concern, as the technology strives to meet industry standards of minimal defectivity. Common defects include line bridging, collapse, bubbles, and dislocations. Efforts are ongoing to optimize annealing temperature, etching methods, and film thickness to reduce these defects. Another challenge is the complexity of pattern inspection, which demands accurate metrology methods. Researchers are exploring machine learning-based approaches to automate the inspection process and achieve higher throughput.
Despite these challenges, DSA is being applied to various applications beyond semiconductors. Tissue engineering benefits from the precision of directed assembly, enabling the controlled organization of cells into desired micro-structures. In nanotechnology, DSA facilitates the creation of precise nanostructures, leading to advancements in areas such as graphene nanoribbon arrays and thin-film quantum materials.
Revolutionizing EUV Lithography with Directed Self-Assembly (DSA)
EUV lithography has revolutionized semiconductor manufacturing but comes with its share of challenges, particularly in addressing line roughness and stochastic defects. DSA has now gained attention as a potential game-changer to tackle these issues in EUV lithography.
Recent research from Imec sheds light on the promising synergy between EUV and DSA in overcoming lithography challenges. In the study titled "EUV Lithography Line Space Pattern Rectification Using Block Copolymer Directed Self-Assembly: A Roughness and Defectivity Study," led by Julie Van Bel and team, the researchers explored the combination of DSA with EUV. Their findings indicate that this integration surpasses DSA processes based on Immersion lithography, offering lower line width roughness and freedom from dislocation defects.
Another study, "Mitigating Stochastics in EUV Lithography by Directed Self-Assembly," led by Lander Verstraete and collaborators, delved into the application of DSA to mitigate stochastic defects in EUV processing.
Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in Figures below. In the top Figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using DSA. Meanwhile, the lower Figure details the rectification process for defects in EUV Contact Patterns.
Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in the figures below. In the top figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using Directed Self-Assembly (DSA). Meanwhile, the lower figure details the rectification process for defects in EUV Contact Patterns. These illustrations highlight the potential of DSA in enhancing lithographic precision, addressing challenges related to line roughness and stochastic defects, and achieving improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error control in semiconductor manufacturing.
The results are particularly promising for line/spaces at a 28nm pitch, primarily addressing bridge defects. However, at a 24nm pitch, further improvement is necessary due to an excess of bridge defects. Notably, the type and frequency of defects correlate with the formulation of the block copolymer and the duration of the annealing process.
For contact arrays, the combination of EUV and DSA demonstrates improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error. This advancement also enables the use of a lower dose, contributing to enhanced precision and efficiency in semiconductor manufacturing.
Imec's research underscores the potential of DSA to revolutionize EUV lithography by addressing line roughness and stochastic defects. The successful integration of EUV and DSA holds the promise of enhancing semiconductor manufacturing processes, achieving higher precision, and enabling the production of advanced devices with improved quality. As researchers continue to refine these methods, the collaboration between EUV and DSA is set to shape the future of lithography and microfabrication.
In conclusion, DSA is revitalizing micro and nano fabrication by offering accurate and efficient methods for mass production. While challenges like defect control and metrology persist, DSA's potential to shape the future of industries such as semiconductors, biomedicine, and nanotechnology is undeniable. As research continues to refine DSA processes and overcome hurdles, its role in advancing technology and innovation is set to expand further.
Canon has partnered with Tokyo Electron and Screen Semiconductor Solutions to develop advanced chipmaking production technology with support from the Japanese government according to a report by Nikkei Asia.
♦ The $386mil USD funding from the Japanese government is through the National Institute of Advanced Industrial Science and Technology, along with the Ministry of Economy, Trade and Industry (METI).
♦ Japans semiconductor production industry has lost ground in recent years to Taiwanese chipmakers and companies like Intel.
The goal is to develop and implement a 2-nanometer or smaller process for chips by the mid-2020s.
Come and join us in Lund Sweden for an exciting Master Thesis in Atomic Level Fragmentation - the new option for extending optical lithography cheaper, greener, and faster than any advanced multi-patterning scheme!
Operating within Lind Nano Lab we guarantee a safe & flexible workplace under ISO 5 and ISO 7 Cleanroom conditions, 24/7 operation, and remote working from wherever you need to be when outside the cleanroom.
View across The Science City of Lund in South Sweden direction Copenhagen in Denmark across the straight of Öresend connected by the longest bridge in Europe.
Here we have it, probably the most beautiful Journal Cover 2021 for the coming cover of the January 2021 issue of Nature Materials, by researchers from KU Leuven in Belgium, TU Munich, Vrije Universiteit Brussel, Graz University of Technology and University of Adelaide.
Nanoscale lithography of metal–organic frameworks
The low dielectric constants and high porosity of MOFs are of interest for applications in electronics and sensors, but patterning techniques for these materials are in their infancy. Here, direct X-ray and electron-beam lithography at sub-50-nm resolution are reported that leave porosity and crystallinity intact.
Tu, M., Xia, B., Kravchenko, D.E. et al. Direct X-ray and electron-beam lithography of halogenated zeolitic imidazolate frameworks. Nat. Mater. 20, 93–99 (2021). https://doi.org/10.1038/s41563-020-00827-x
Image: Rob Ameloot. Cover Design: Thomas Phillips.
LEUVEN (Belgium, LINK) October 6, 2020 — Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, announced today promising results in extreme ultraviolet (EUV) reticle protection. Multiple CNT-based pellicles were mounted on reticles and exposed in the NXE:3300 EUV scanner at imec, demonstrating the successful fabrication and scanner handling of full-field CNT-based pellicles. The tested pellicles had a single-pass EUV transmission up to 97%. The impact on imaging was found to be low and correctable based on critical dimension (CD), dose, and transmission measurements.
A pellicle is a membrane used to protect the photomask from contamination during high-volume semiconductor manufacturing. It is mounted a few millimeters above the surface of the photomask so that if particles land on the pellicle, they will be too far out of focus to print. Developing such an EUV pellicle is very challenging, since 13.5nm light is absorbed by most materials. In addition, stringent thermal, chemical, and mechanical requirements must be achieved. Such highly transparent pellicle is critical to enable high yield and throughput in advanced semiconductor manufacturing.
Imec demonstrates a CNT Pelicle (photo Imec.be)
Imec has leveraged partners in the semiconductor industry, materials companies and fundamental research to develop an innovative EUV pellicle design with potential to survive scanner powers beyond 600 Watts
“Imec has leveraged partners in the semiconductor industry, materials companies and fundamental research to develop an innovative EUV pellicle design with potential to survive scanner powers beyond 600 Watts,” said Emily Gallagher, principal member of technical staff at imec. “We have seen tremendous progress in carbon nanotube membrane development in the past year and, based on strong collaborations with our partners, are confident it will result in a high-performance pellicle solution in the near future.”
CNTs are one-atom-thick carbon sheets rolled into tubes. The CNTs can be single-, double- or multi-walled and can vary in diameter and in length. These engineered CNTs can be arranged in different configurations to form membranes of different densities. Since 2015, imec has been working with selected CNT suppliers (Canatu Oy and Lintec of America, Inc., Nano-Science & Technology Center) to develop membranes that meet the EUV pellicle targets for properties like transmittance, thermal durability, permeability, and strength and to enable the imaging results reported today. Future work will focus on achieving acceptable lifetimes for high volume manufacturing of these pellicles in scanners.
LU Holding invests in newly started AlixLabs, which have developed a method to manufacture electronic circuits for the semiconductor industry in a very cost-effective way.
[Published on September 27, 2019: Original in Swedish: LINK]
Researchers from NanoLund have developed and patented the method and all three, Jonas Sundqvist, Dmitry Suyatin, and Sabbir Kahn, are part of the newly started company (AlixLabs AB), and Co-founder Stefan Svedberg joins as CEO. Svedberg was previously Director of Corporate Development at Ericsson.
Displaying the Edge Effect: This is a new method of nanostructure fabrication using the atomic layer etching process, which is inherently a damage-free etch process. The recently discovered etching process selectivity to inclined surfaces, can be used as a mask and in this way walls of tapered structures. The inclined surfaces can be readily fabricated by e.g. dry etching or epitaxial growth, and will provide masking during the atomic layer etching process. This process therefore provides access to fabrication of extremely small structures in a very precise and efficient way.
Electronic circuits are needed in all types of hardware, but the cost of producing them has increased as the electronics become smaller. With the AlixLab method, which is based on a recently identified physical phenomenon, the manufacturing process of the electronic circuits becomes both faster and significantly cheaper.
Dr. Dmitry Suyatin, Co-founder and CTO and Dr. Jonas Sundqvist, Co-founder and Senior Technical Adviser at AlixLabs inspecting the new Atomic Layer Etching Equipment at Lund Nano Lab from PlasmaTherm.
"AlixLabs has an exciting technology, and now we have a good team in place," says Erik Larsson, portfolio manager at LU Holding.
Alixlabs plans to implement an expanded proof of concept in 2020 as the basis for continued customer discussions.
A manufacturing technique that could help the semiconductor industry make more powerful computer chips began in the humblest of places — at a lunch table at the U.S. Department of Energy’s (DOE) Argonne National Laboratory.
The materials synthesis method known as sequential infiltration synthesis, or SIS, has the potential to improve not only chip manufacturing but also things like hard drive storage, solar cell efficiency, anti-reflective surfaces on optics and water-repellant car windshields. Invented in 2010 during a lunchtime conversation between Argonne scientists Seth Darling and Jeffrey Elam and two of their postdoctoral researchers, use of the method has grown in recent years.
Top: Jeff Elam and Anil Mane, co-inventor on the SIS for lithography method and Principal Materials Science Engineer in Argonne’s Applied Materials Division. Bottom: Silicon wafers, ranging in size from 4” to 12” diameter, that have been treated using Argonne’s sequential infiltration synthesis method (Credit : Argonne National Laboratory).
The method was based on the group’s discussion of atomic layer deposition, or ALD, a thin film deposition technique that uses alternating chemical vapors to grow materials one atomic layer at a time. Darling, director of the Institute for Molecular Engineering at Argonne and the Advanced Materials for Energy-Water Systems Energy Frontier Research Center, recently used that technique to add a water-loving metal oxide coating to filters used in the oil and gas industry which prevents the filters from clogging.
“It worked beautifully on the first try.” — Seth Darling, director of Argonne’s Institute for Molecular Engineering and the Advanced Materials for Energy-Water Systems Energy Frontier Research Center
But as the group talked, they started speculating about taking ALD to a new level, said Darling.
“We said ‘Wouldn’t it be neat if we could grow one material inside another material like a polymer (a string of many combined molecules) instead of on top of it?’” Darling said. “We first thought ‘This isn’t going to work,’ but, surprisingly, it worked beautifully on the first try. Then we began imagining all of the different applications it could be used for.”
The research was funded by the DOE Office of Science, Basic Energy Sciences Program as well as the Argonne-Northwestern Solar Energy Research Center, a DOE Office of Science-funded Energy Frontier Research Center.
Anil Mane unloding wafers processed in a BENEQ TFS 500 ALD reactor at Argonne’s Applied Materials Division. (Credit : Argonne National Laboratory).
SIS is similar to ALD on a polymer surface, but in SIS the vapor is diffused into the polymer rather than on top of it, where it chemically binds with the polymer and eventually grows to create inorganic structures throughout the entire polymer bulk.
Using this technique, scientists can create robust coatings that can help the semiconductor manufacturing industry etch more intricate features on computer chips, allowing them to become even smaller or to add extra storage and other capabilities. They can also tailor the shape of various metals, oxides and other inorganic materials by applying them to a polymer with SIS and then removing the remains of the polymer.
“You can take a pattern in a polymer, expose it to vapors and transform it from an organic material to an inorganic material,” said Elam, director of Argonne’s ALD research program, referring to the way the method can use polymers and a vapor to basically mold a new material with specific properties. “It’s a way to use a polymer pattern, and convert that pattern into virtually any inorganic material.”
The technology’s potential spans beyond semiconductors. It could be used to advance products in different industries, and Argonne would be delighted to work with commercialization partners who can take the invention and incorporate it in existing products - or invent new applications to benefit U.S. economy, said Hemant Bhimnathwala, a business development executive at Argonne.
“You can use SIS to create a film, you can put it on a metal, you can create this on glass or put it on a glass windshield to make it water repelling to the point where you don’t need wipers,” Bhimnathwala said.
The way the scientists invented the technique — through that lunch meeting — was also a bit unusual. New discoveries often come about by accident, but not usually by spitballing ideas over lunch, Elam said.
“Occasionally, if you’re watching intently, you can see something else there and discover something new and unexpected,” Elam said. “That doesn’t happen very often, but when it does, it’s great.”
The technique also addresses a specific concern in the semiconductor manufacturing industry, pattern collapse, which means the collapse of tiny features used to create electrical components on a computer chip, rendering it useless.
When a pattern is etched on a silicon chip in the chip-making process, an etch-resistant surface is used as a protective coating to mask those regions you do not want to remove. But the etch-resistant coatings commonly used today wear away very quickly, which has prevented chip manufacturers from making components with deeply etched features, Darling said.
With SIS, inorganic vapor coatings can be engineered to provide greater protection of vertical features, allowing deeper etches and the integration of more components on each chip.
“Features on chips have gotten extremely small laterally, but sometimes you also want to make them tall,” Darling said. “You can’t make a tall feature if your resist etches away quickly, but with SIS it’s easy.”
Similarly, the technique can be used to manipulate magnetic recording on hard drives or other storage devices, allowing them to increase storage while also getting smaller, Darling said.
Another possibility for the technology is to control how much light bounces off a glass or plastic surface. Using SIS, scientists can engineer surfaces to be almost entirely non-reflective. Using this strategy, scientists can improve performance of solar cells, LEDs and even eyeglasses.
“There are also a lot of applications in electronics,” Elam said. “You can use it to squeeze more memory in a smaller space, or to build faster microprocessors. SIS lithography is a promising strategy to maintain the technological progression and scaling of Moore’s Law.”
Argonne is looking for commercial partners interested in licensing and developing the technology for more specific uses. Companies interested in leveraging Argonne’s expertise in SIS should contact partners@anl.gov to learn more and discuss possible collaborations.
Top: Seth Darling, Scientist and Director of the Institute for Molecular Engineering at Argonne National Laboratory. Bottom: Jeff Elam, Senior Chemist in Argonne’ Applied Materials Division (bottom). Picture Credit : Argonne National Laboratory.
We have entered the era of atomic level processing by the introduction of atomic layer deposition (ALD), etching (ALE), cleaning (ALC) and so on in semiconductor manufacturing for advanced CMOS and Memory devices. Especially because of the delay of EUV Lithography ALD has proven to save continued device scaling by implementation in multiple patterning techniques so that scaliong can go on.
Here is yet another interesting technique where ALD is used in a sense to create extremely narrow channels with atomic precision governed by ALD - Atomic Layer Lithography.
Researchers at the University of Minnesota in Minneapolis have invented a
new ultralow power technique to trap nanoparticles in the sub-10 nm
gaps between two gold electrodes. The technique, which overcomes many of
the problems encountered in traditional dielectrophoresis experiments,
could help make portable biosensors.
(a) Fabrication scheme using atomic layer lithography. An Al2O3
layer of desired thickness (that is, gap size) is deposited using ALD
on a patterned gold film. A second layer of gold is evaporated, such
that the first and second metal layers are not in contact. The top gold
layer is then peeled off using adhesive tape, exposing the Al2O3-filled
nanogap between the two gold electrodes. (b) An array of nanogap
electrodes of desirable length is patterned by photolithography and ion
milling on a 1 cm long nanogap. Courtesy: Nanotechweb & Nano Lett.
Nanotechweb reports that in 2011, a student (Xiaoshu Chen) figured out how to make vertically-oriented gaps as small as 1 nm
over a centimeter length scale, which accordingly is not possible by any other method.
“As a result, we were able to make long and narrow gaps using atomic
layer deposition (ALD), which is a robust manufacturing technique for
coating ultra-thin films to construct insulating gaps in the sidewalls
of patterned metals (see figure above). Thanks to the nature of ALD, we can
precisely control the width of the gap, and after depositing metals on
the other side of the ALD coating, nanogaps naturally form."
“What makes this atomic layer lithography technique so unique and
appealing is that we can expose the nanogaps using just Scotch tape, he
tells nanotechweb.org. “This was a rather surprising discovery
that Chen made. Since many labs around the world have access to ALD
tools (and indeed Scotch tape!), this means that other researchers could
practise our technique, easily and inexpensively.”
As feautured in TG Techno: Professor Shin-Hyun Kim and his research team in the Department of Chemical and Biomolecular Engineering at KAIST have developed a novel photolithographic technology enabling control over the functional shapes of micropatterns using oxygen diffusion.
Professor Kim’s research team discovered that: 1) the areas exposed to UV light lowered the concentration of oxygen and thus resulted in oxygen diffusion; and 2) manipulation of the diffusion speed and direction allowed control of the growth, shape and size of the polymers. Based on these findings, the team developed a new photolithographic technology that enabled the production of micropatterns with three-dimensional structures in various shapes and sizes.
Polymers with various shapes and sizes produced with the new photolithographic technology developed by Professor Kim
According to a report in Solid State Technology researchers at aBeam Technologies, Lawrence Berkeley National Laboratory and Argonne National Laboratory have developed a technology to fabricate test patterns with a minimum linewidth down to 1.5nm. The fabricated nanostructures are used to test metrological equipment. The designed patterns involve thousands of lines with precisely designed linewidths; these lines are combined in such a way that the distribution of linewidths appears to be random at any location. This pseudo- random test pattern allows nanometrological systems to be characterized over their entire dynamic range.
TEM images of the test pattern with linewidths down to 1.5nm. The
width of the lines was designed to form a pseudo-random test pattern;
the pattern is used to characterize metrological instrumentation. The
scale bar on the top image is 50nm.
Dr. Sergey Babin, president of aBeam Technologies said, “The semiconductor industry
is moving toward a half-pitch of 11nm and 7nm. Therefore, metrology
equipment should be very accurate, at least one order of magnitude more
accurate than that. The characterization of metrology
systems requires test patterns at a scale one order smaller than the
measured features. The fabrication was a challenge, especially for such a
complex pattern as a pseudo-random design, but we succeeded.”
A team led by Sang-Hyun Oh of the University of Minnesota is now saying that it has produced SEIRA (surface-enhanced infrared absorption) enhancements as high as 105 for nanogaps just 3 nm across arranged in a dense array of millimetre-long hotspots.
“In our scheme, we create the nanogaps by depositing thin layers of aluminium oxide on the sidewalls of metal patterns using a well known technique called atomic layer deposition,” Oh tells nanotechweb.org. “We can use this technique to control the thickness of the film, which then defines the gap width on the Angstrom scale. And since thin-film deposition is a fast batch process, we can also make dense arrays of nanogaps over an entire wafer in a quick and easy way.”
The researchers use standard photolithography to pattern gold films on a 4 inch silicon wafer. These patterns are conformally encapsulated with a thin alumina spacer using atomic layer deposition (ALD). Next, a silver film is deposited conformally on the pattern, and the whole structure is stripped off from the silicon substrate using UV cured epoxy and a glass slide. f) Cross-sectional schematic of a buried nanocavity. g) Contact mode AFM line scan across a 5 nm nanogap cavity showing a height difference between the gold and silver films due to the 5 nm thick Al2O3 film. h) Photograph of a 4 inch wafer-containing metal stripes after lift-off. Each square is approximately 1.5 by 1.5 mm. i) SEM image of an array of buried nanogaps on a chip. Further zoomed-in images show a single cavity and a 5 nm nanogap on one side of the cavity. j and k) SEM of buried disks and wedges. Pictures from: Nano Lett.
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