Showing posts with label lithography. Show all posts
Showing posts with label lithography. Show all posts

Wednesday, March 24, 2021

Canon, SCREEN and Tokyo Electron to join Japan advanced chipmaking project for 2nm

Canon has partnered with Tokyo Electron and Screen Semiconductor Solutions to develop advanced chipmaking production technology with support from the Japanese government according to a report by Nikkei Asia.

♦ The $386mil USD funding from the Japanese government is through the National Institute of Advanced Industrial Science and Technology, along with the Ministry of Economy, Trade and Industry (METI).
♦ Japans semiconductor production industry has lost ground in recent years to Taiwanese chipmakers and companies like Intel.
The goal is to develop and implement a 2-nanometer or smaller process for chips by the mid-2020s.

Source (Paywall): LINK


Tokyo Electron semiconductor fab professionals shuffling wafers (credit: Tokyo Electron)

Thursday, January 21, 2021

Master Thesis in Nanotechnology with Alixlabs in Sweden on Atomic Level Fragmentation

Come and join us in Lund Sweden for an exciting Master Thesis in Atomic Level Fragmentation - the new option for extending optical lithography cheaper, greener, and faster than any advanced multi-patterning scheme!

Operating within Lind Nano Lab we guarantee a safe & flexible workplace under ISO 5 and ISO 7 Cleanroom conditions, 24/7 operation, and remote working from wherever you need to be when outside the cleanroom.


Lund Nano Lab : LINK

Thesis description and application : LINK


View across The Science City of Lund in South Sweden direction Copenhagen in Denmark across the straight of Öresend connected by the longest bridge in Europe.


Tuesday, December 22, 2020

Nanoscale lithography of metal–organic frameworks (MOFs)

Here we have it, probably the most beautiful Journal Cover 2021 for the coming cover of the January 2021 issue of Nature Materials, by researchers from KU Leuven in Belgium, TU Munich, Vrije Universiteit Brussel, Graz University of Technology and University of Adelaide.

Nanoscale lithography of metal–organic frameworks

The low dielectric constants and high porosity of MOFs are of interest for applications in electronics and sensors, but patterning techniques for these materials are in their infancy. Here, direct X-ray and electron-beam lithography at sub-50-nm resolution are reported that leave porosity and crystallinity intact.

Tu, M., Xia, B., Kravchenko, D.E. et al. Direct X-ray and electron-beam lithography of halogenated zeolitic imidazolate frameworks. Nat. Mater. 20, 93–99 (2021). https://doi.org/10.1038/s41563-020-00827-x



Image: Rob Ameloot. Cover Design: Thomas Phillips.




Tuesday, October 6, 2020

Imec demonstrates CNT pellicle utilization on EUV scanner

LEUVEN (Belgium, LINK) October 6, 2020 — Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, announced today promising results in extreme ultraviolet (EUV) reticle protection. Multiple CNT-based pellicles were mounted on reticles and exposed in the NXE:3300 EUV scanner at imec, demonstrating the successful fabrication and scanner handling of full-field CNT-based pellicles. The tested pellicles had a single-pass EUV transmission up to 97%. The impact on imaging was found to be low and correctable based on critical dimension (CD), dose, and transmission measurements.

A pellicle is a membrane used to protect the photomask from contamination during high-volume semiconductor manufacturing. It is mounted a few millimeters above the surface of the photomask so that if particles land on the pellicle, they will be too far out of focus to print. Developing such an EUV pellicle is very challenging, since 13.5nm light is absorbed by most materials. In addition, stringent thermal, chemical, and mechanical requirements must be achieved. Such highly transparent pellicle is critical to enable high yield and throughput in advanced semiconductor manufacturing. 

Imec demonstrates a CNT Pelicle (photo Imec.be)

Imec has leveraged partners in the semiconductor industry, materials companies and fundamental research to develop an innovative EUV pellicle design with potential to survive scanner powers beyond 600 Watts

“Imec has leveraged partners in the semiconductor industry, materials companies and fundamental research to develop an innovative EUV pellicle design with potential to survive scanner powers beyond 600 Watts,” said Emily Gallagher, principal member of technical staff at imec. “We have seen tremendous progress in carbon nanotube membrane development in the past year and, based on strong collaborations with our partners, are confident it will result in a high-performance pellicle solution in the near future.”

CNTs are one-atom-thick carbon sheets rolled into tubes. The CNTs can be single-, double- or multi-walled and can vary in diameter and in length. These engineered CNTs can be arranged in different configurations to form membranes of different densities. Since 2015, imec has been working with selected CNT suppliers (Canatu Oy and Lintec of America, Inc., Nano-Science & Technology Center) to develop membranes that meet the EUV pellicle targets for properties like transmittance, thermal durability, permeability, and strength and to enable the imaging results reported today. Future work will focus on achieving acceptable lifetimes for high volume manufacturing of these pellicles in scanners.

Tuesday, October 15, 2019

Lund University Holding invests in newly started AlixLabs

LU Holding invests in newly started AlixLabs, which have developed a method to manufacture electronic circuits for the semiconductor industry in a very cost-effective way.

[Published on September 27, 2019: Original in Swedish: LINK]

Researchers from NanoLund have developed and patented the method and all three, Jonas Sundqvist, Dmitry Suyatin, and Sabbir Kahn, are part of the newly started company (AlixLabs AB), and Co-founder Stefan Svedberg joins as CEO. Svedberg was previously Director of Corporate Development at Ericsson.

Displaying the Edge Effect: This is a new method of nanostructure fabrication using the atomic layer etching process, which is inherently a damage-free etch process. The recently discovered etching process selectivity to inclined surfaces, can be used as a mask and in this way walls of tapered structures. The inclined surfaces can be readily fabricated by e.g. dry etching or epitaxial growth, and will provide masking during the atomic layer etching process. This process therefore provides access to fabrication of extremely small structures in a very precise and efficient way.

Electronic circuits are needed in all types of hardware, but the cost of producing them has increased as the electronics become smaller. With the AlixLab method, which is based on a recently identified physical phenomenon, the manufacturing process of the electronic circuits becomes both faster and significantly cheaper.

Dr. Dmitry Suyatin, Co-founder and CTO and Dr. Jonas Sundqvist, Co-founder and Senior Technical Adviser at AlixLabs inspecting the new Atomic Layer Etching Equipment at Lund Nano Lab from PlasmaTherm.
 
"AlixLabs has an exciting technology, and now we have a good team in place," says Erik Larsson, portfolio manager at LU Holding.

Alixlabs plans to implement an expanded proof of concept in 2020 as the basis for continued customer discussions.
AlixLabs Team : LINK

Sunday, December 9, 2018

Argonne develops SIS lithography to maintain the technological progression and scaling of Moore’s Law

A manufacturing technique that could help the semiconductor industry make more powerful computer chips began in the humblest of places — at a lunch table at the U.S. Department of Energy’s (DOE) Argonne National Laboratory. 

The materials synthesis method known as sequential infiltration synthesis, or SIS, has the potential to improve not only chip manufacturing but also things like hard drive storage, solar cell efficiency, anti-reflective surfaces on optics and water-repellant car windshields. Invented in 2010 during a lunchtime conversation between Argonne scientists Seth Darling and Jeffrey Elam and two of their postdoctoral researchers, use of the method has grown in recent years.



Top: Jeff Elam and Anil Mane, co-inventor on the SIS for lithography method and Principal Materials Science Engineer in Argonne’s Applied Materials Division. Bottom: Silicon wafers, ranging in size from 4” to 12” diameter, that have been treated using Argonne’s sequential infiltration synthesis method (Credit : Argonne National Laboratory).

The method was based on the group’s discussion of atomic layer deposition, or ALD, a thin film deposition technique that uses alternating chemical vapors to grow materials one atomic layer at a time. Darling, director of the Institute for Molecular Engineering at Argonne and the Advanced Materials for Energy-Water Systems Energy Frontier Research Center, recently used that technique to add a water-loving metal oxide coating to filters used in the oil and gas industry which prevents the filters from clogging.

“It worked beautifully on the first try.” — Seth Darling, director of Argonne’s Institute for Molecular Engineering and the Advanced Materials for Energy-Water Systems Energy Frontier Research Center

But as the group talked, they started speculating about taking ALD to a new level, said Darling.

“We said ​‘Wouldn’t it be neat if we could grow one material inside another material like a polymer (a string of many combined molecules) instead of on top of it?’” Darling said. ​“We first thought ​‘This isn’t going to work,’ but, surprisingly, it worked beautifully on the first try. Then we began imagining all of the different applications it could be used for.”

The research was funded by the DOE Office of Science, Basic Energy Sciences Program as well as the Argonne-Northwestern Solar Energy Research Center, a DOE Office of Science-funded Energy Frontier Research Center.


Anil Mane unloding wafers processed in a BENEQ TFS 500 ALD reactor at Argonne’s Applied Materials Division. (Credit : Argonne National Laboratory).

SIS is similar to ALD on a polymer surface, but in SIS the vapor is diffused into the polymer rather than on top of it, where it chemically binds with the polymer and eventually grows to create inorganic structures throughout the entire polymer bulk.

Using this technique, scientists can create robust coatings that can help the semiconductor manufacturing industry etch more intricate features on computer chips, allowing them to become even smaller or to add extra storage and other capabilities. They can also tailor the shape of various metals, oxides and other inorganic materials by applying them to a polymer with SIS and then removing the remains of the polymer.

“You can take a pattern in a polymer, expose it to vapors and transform it from an organic material to an inorganic material,” said Elam, director of Argonne’s ALD research program, referring to the way the method can use polymers and a vapor to basically mold a new material with specific properties. ​“It’s a way to use a polymer pattern, and convert that pattern into virtually any inorganic material.”

The technology’s potential spans beyond semiconductors. It could be used to advance products in different industries, and Argonne would be delighted to work with commercialization partners who can take the invention and incorporate it in existing products - or invent new applications to benefit U.S. economy, said Hemant Bhimnathwala, a business development executive at Argonne.

“You can use SIS to create a film, you can put it on a metal, you can create this on glass or put it on a glass windshield to make it water repelling to the point where you don’t need wipers,” Bhimnathwala said.

The way the scientists invented the technique — through that lunch meeting — was also a bit unusual. New discoveries often come about by accident, but not usually by spitballing ideas over lunch, Elam said.

“Occasionally, if you’re watching intently, you can see something else there and discover something new and unexpected,” Elam said. ​“That doesn’t happen very often, but when it does, it’s great.”

The technique also addresses a specific concern in the semiconductor manufacturing industry, pattern collapse, which means the collapse of tiny features used to create electrical components on a computer chip, rendering it useless.

When a pattern is etched on a silicon chip in the chip-making process, an etch-resistant surface is used as a protective coating to mask those regions you do not want to remove. But the etch-resistant coatings commonly used today wear away very quickly, which has prevented chip manufacturers from making components with deeply etched features, Darling said.

With SIS, inorganic vapor coatings can be engineered to provide greater protection of vertical features, allowing deeper etches and the integration of more components on each chip.

“Features on chips have gotten extremely small laterally, but sometimes you also want to make them tall,” Darling said. ​“You can’t make a tall feature if your resist etches away quickly, but with SIS it’s easy.”

Similarly, the technique can be used to manipulate magnetic recording on hard drives or other storage devices, allowing them to increase storage while also getting smaller, Darling said.

Another possibility for the technology is to control how much light bounces off a glass or plastic surface. Using SIS, scientists can engineer surfaces to be almost entirely non-reflective. Using this strategy, scientists can improve performance of solar cells, LEDs and even eyeglasses.

“There are also a lot of applications in electronics,” Elam said. ​“You can use it to squeeze more memory in a smaller space, or to build faster microprocessors. SIS lithography is a promising strategy to maintain the technological progression and scaling of Moore’s Law.”

The team’s research on the technology has been published in The Journal of Materials Chemistry, The Journal of Physical Chemistry, Advanced Materials and The Journal of Vacuum Science & Technology B.

Argonne is looking for commercial partners interested in licensing and developing the technology for more specific uses. Companies interested in leveraging Argonne’s expertise in SIS should contact partners@​anl.​gov to learn more and discuss possible collaborations.



Top: Seth Darling, Scientist and Director of the Institute for Molecular Engineering at Argonne National Laboratory. Bottom: Jeff Elam, Senior Chemist in Argonne’ Applied Materials Division (bottom). Picture Credit : Argonne National Laboratory.

Thursday, March 2, 2017

IBM present progress in Lithography for beyond 7 nm chips at SPIE Litho

This week IBM present progress in Lithography for beyond 7 nm chips at SPIE Litho in San Diego.



Thursday, October 13, 2016

University of Minnesota has developed Atomic Layer Lithography by ALD to create long narrow nano gaps

We have entered the era of atomic level processing by the introduction of atomic layer deposition (ALD), etching (ALE), cleaning (ALC) and so on in semiconductor manufacturing for advanced CMOS and Memory devices. Especially because of the delay of EUV Lithography ALD has proven to save continued device scaling by implementation in multiple patterning techniques so that scaliong can go on.

Here is yet another interesting technique where ALD is used in a sense to create extremely narrow channels with atomic precision governed by ALD - Atomic Layer Lithography.

As reported by Nanotechweb - Gold nanogap electrodes trap tiny particles

Researchers at the University of Minnesota in Minneapolis have invented a new ultralow power technique to trap nanoparticles in the sub-10 nm gaps between two gold electrodes. The technique, which overcomes many of the problems encountered in traditional dielectrophoresis experiments, could help make portable biosensors.

(a) Fabrication scheme using atomic layer lithography. An Al2O3 layer of desired thickness (that is, gap size) is deposited using ALD on a patterned gold film. A second layer of gold is evaporated, such that the first and second metal layers are not in contact. The top gold layer is then peeled off using adhesive tape, exposing the Al2O3-filled nanogap between the two gold electrodes. (b) An array of nanogap electrodes of desirable length is patterned by photolithography and ion milling on a 1 cm long nanogap. Courtesy: Nanotechweb & Nano Lett.

Nanotechweb reports that in 2011, a student (Xiaoshu Chen) figured out how to make vertically-oriented gaps as small as 1 nm over a centimeter length scale, which accordingly is not possible by any other method.

“As a result, we were able to make long and narrow gaps using atomic layer deposition (ALD), which is a robust manufacturing technique for coating ultra-thin films to construct insulating gaps in the sidewalls of patterned metals (see figure above). Thanks to the nature of ALD, we can precisely control the width of the gap, and after depositing metals on the other side of the ALD coating, nanogaps naturally form."

“What makes this atomic layer lithography technique so unique and appealing is that we can expose the nanogaps using just Scotch tape, he tells nanotechweb.org. “This was a rather surprising discovery that Chen made. Since many labs around the world have access to ALD tools (and indeed Scotch tape!), this means that other researchers could practise our technique, easily and inexpensively.” 

Full article:  Gold nanogap electrodes trap tiny particles

Thursday, April 9, 2015

KAIST develops a photolithographic technology that enables 3D control over functional shapes of microstructures

As feautured in TG Techno: Professor Shin-Hyun Kim and his research team in the Department of Chemical and Biomolecular Engineering at KAIST have developed a novel photolithographic technology enabling control over the functional shapes of micropatterns using oxygen diffusion.

Professor Kim’s research team discovered that: 1) the areas exposed to UV light lowered the concentration of oxygen and thus resulted in oxygen diffusion; and 2) manipulation of the diffusion speed and direction allowed control of the growth, shape and size of the polymers. Based on these findings, the team developed a new photolithographic technology that enabled the production of micropatterns with three-dimensional structures in various shapes and sizes. 
 
Polymers with various shapes and sizes produced with the new photolithographic technology developed by Professor Kim

Thursday, February 5, 2015

aBeam fabricates patterns with linewidths down to 1.5nm

According to a report in Solid State Technology researchers at aBeam Technologies, Lawrence Berkeley National Laboratory and Argonne National Laboratory have developed a technology to fabricate test patterns with a minimum linewidth down to 1.5nm. The fabricated nanostructures are used to test metrological equipment. The designed patterns involve thousands of lines with precisely designed linewidths; these lines are combined in such a way that the distribution of linewidths appears to be random at any location. This pseudo- random test pattern allows nanometrological systems to be characterized over their entire dynamic range.
 
lawrence berk micro2 
lawrence berk micro1

TEM images of the test pattern with linewidths down to 1.5nm. The width of the lines was designed to form a pseudo-random test pattern; the pattern is used to characterize metrological instrumentation. The scale bar on the top image is 50nm. 


aBeam Technologies

Dr. Sergey Babin, president of aBeam Technologies said, “The semiconductor industry is moving toward a half-pitch of 11nm and 7nm. Therefore, metrology equipment should be very accurate, at least one order of magnitude more accurate than that. The characterization of metrology systems requires test patterns at a scale one order smaller than the measured features. The fabrication was a challenge, especially for such a complex pattern as a pseudo-random design, but we succeeded.”
 
 

Thursday, December 11, 2014

Atomic Layer Lithography - Creation of nanogaps by ALD

A team led by Sang-Hyun Oh of the University of Minnesota is now saying that it has produced SEIRA (surface-enhanced infrared absorption) enhancements as high as 105 for nanogaps just 3 nm across arranged in a dense array of millimetre-long hotspots.

“In our scheme, we create the nanogaps by depositing thin layers of aluminium oxide on the sidewalls of metal patterns using a well known technique called atomic layer deposition,” Oh tells nanotechweb.org. “We can use this technique to control the thickness of the film, which then defines the gap width on the Angstrom scale. And since thin-film deposition is a fast batch process, we can also make dense arrays of nanogaps over an entire wafer in a quick and easy way.”

The researchers use standard photolithography to pattern gold films on a 4 inch silicon wafer. These patterns are conformally encapsulated with a thin alumina spacer using atomic layer deposition (ALD). Next, a silver film is deposited conformally on the pattern, and the whole structure is stripped off from the silicon substrate using UV cured epoxy and a glass slide. f) Cross-sectional schematic of a buried nanocavity. g) Contact mode AFM line scan across a 5 nm nanogap cavity showing a height difference between the gold and silver films due to the 5 nm thick Al<sub>2</sub>O<sub>3</sub> film. h) Photograph of a 4 inch wafer-containing metal stripes after lift-off. Each square is approximately 1.5 by 1.5 mm. i) SEM image of an array of buried nanogaps on a chip. Further zoomed-in images show a single cavity and a 5 nm nanogap on one side of the cavity. j and k) SEM of buried disks and wedges. Courtesy: <i>Nano Lett.</i>

The researchers use standard photolithography to pattern gold films on a 4 inch silicon wafer. These patterns are conformally encapsulated with a thin alumina spacer using atomic layer deposition (ALD). Next, a silver film is deposited conformally on the pattern, and the whole structure is stripped off from the silicon substrate using UV cured epoxy and a glass slide. f) Cross-sectional schematic of a buried nanocavity. g) Contact mode AFM line scan across a 5 nm nanogap cavity showing a height difference between the gold and silver films due to the 5 nm thick Al2O3 film. h) Photograph of a 4 inch wafer-containing metal stripes after lift-off. Each square is approximately 1.5 by 1.5 mm. i) SEM image of an array of buried nanogaps on a chip. Further zoomed-in images show a single cavity and a 5 nm nanogap on one side of the cavity. j and k) SEM of buried disks and wedges. Pictures from: Nano Lett.