Showing posts with label self-assembly. Show all posts
Showing posts with label self-assembly. Show all posts

Thursday, August 24, 2023

An Update on Directed Self-Assembly (DSA) for Advancing Micro and Nano Fabrication

Revolutionizing fabrication, Directed Self-Assembly (DSA) innovates micro to nano devices and materials. It leverages block co-polymer morphology for precise patterns and guides micro/nano particles, enhancing manufacturing. In semiconductors, DSA addresses lithography challenges, while Imec's research showcases DSA-EUV synergy for defect-free outcomes. Complex rectification processes, illustrated by Imec, spotlight improved Critical Dimension Uniformity and Pattern Placement Error control. As DSA advances, its collaboration with EUV promises precision, efficiency, and innovation across industries.

DSA has emerged as a groundbreaking technique for mass-producing micro to nano devices and materials with precision and efficiency. This method harnesses the inherent properties of materials to assemble them into intricate structures, revolutionizing manufacturing processes across various industries.

DSA leverages block co-polymer morphology to create patterns, enhancing feature control and shape accuracy. This involves guiding the assembly of micro and nano particles to achieve desired structures, made possible by the precise control of surface interactions and polymer thermodynamics. The key advantage of DSA is its ability to create structures at remarkably small scales, enabling advancements in diverse fields.

In the semiconductor industry, DSA offers a new perspective on lithography challenges. Despite initial setbacks, DSA is being revisited to address critical issues such as stochastic defects in extreme ultraviolet (EUV) lithography. These defects, which can contribute significantly to patterning errors, have led semiconductor manufacturers to explore DSA as a solution to rectify these problems. Notably, DSA is not replacing traditional methods but rather enhancing them. It is being integrated with existing manufacturing processes to enable increased resolution and precision, all while reducing costs.

However, challenges persist in integrating DSA into high-volume manufacturing. Defect control remains a primary concern, as the technology strives to meet industry standards of minimal defectivity. Common defects include line bridging, collapse, bubbles, and dislocations. Efforts are ongoing to optimize annealing temperature, etching methods, and film thickness to reduce these defects. Another challenge is the complexity of pattern inspection, which demands accurate metrology methods. Researchers are exploring machine learning-based approaches to automate the inspection process and achieve higher throughput.

Despite these challenges, DSA is being applied to various applications beyond semiconductors. Tissue engineering benefits from the precision of directed assembly, enabling the controlled organization of cells into desired micro-structures. In nanotechnology, DSA facilitates the creation of precise nanostructures, leading to advancements in areas such as graphene nanoribbon arrays and thin-film quantum materials.

Revolutionizing EUV Lithography with Directed Self-Assembly (DSA)

EUV lithography has revolutionized semiconductor manufacturing but comes with its share of challenges, particularly in addressing line roughness and stochastic defects. DSA has now gained attention as a potential game-changer to tackle these issues in EUV lithography.

Recent research from Imec sheds light on the promising synergy between EUV and DSA in overcoming lithography challenges. In the study titled "EUV Lithography Line Space Pattern Rectification Using Block Copolymer Directed Self-Assembly: A Roughness and Defectivity Study," led by Julie Van Bel and team, the researchers explored the combination of DSA with EUV. Their findings indicate that this integration surpasses DSA processes based on Immersion lithography, offering lower line width roughness and freedom from dislocation defects.

Another study, "Mitigating Stochastics in EUV Lithography by Directed Self-Assembly," led by Lander Verstraete and collaborators, delved into the application of DSA to mitigate stochastic defects in EUV processing.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in Figures below. In the top Figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using DSA. Meanwhile, the lower Figure details the rectification process for defects in EUV Contact Patterns.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in the figures below. In the top figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using Directed Self-Assembly (DSA). Meanwhile, the lower figure details the rectification process for defects in EUV Contact Patterns. These illustrations highlight the potential of DSA in enhancing lithographic precision, addressing challenges related to line roughness and stochastic defects, and achieving improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error control in semiconductor manufacturing.

The results are particularly promising for line/spaces at a 28nm pitch, primarily addressing bridge defects. However, at a 24nm pitch, further improvement is necessary due to an excess of bridge defects. Notably, the type and frequency of defects correlate with the formulation of the block copolymer and the duration of the annealing process.

For contact arrays, the combination of EUV and DSA demonstrates improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error. This advancement also enables the use of a lower dose, contributing to enhanced precision and efficiency in semiconductor manufacturing.

Imec's research underscores the potential of DSA to revolutionize EUV lithography by addressing line roughness and stochastic defects. The successful integration of EUV and DSA holds the promise of enhancing semiconductor manufacturing processes, achieving higher precision, and enabling the production of advanced devices with improved quality. As researchers continue to refine these methods, the collaboration between EUV and DSA is set to shape the future of lithography and microfabrication.

In conclusion, DSA is revitalizing micro and nano fabrication by offering accurate and efficient methods for mass production. While challenges like defect control and metrology persist, DSA's potential to shape the future of industries such as semiconductors, biomedicine, and nanotechnology is undeniable. As research continues to refine DSA processes and overcome hurdles, its role in advancing technology and innovation is set to expand further.

Directed Self-Assembly Finds Its Footing (

SPIE 2023 – imec Preparing for High-NA EUV - SemiWiki

Directed assembly of micro- and nano-structures - Wikipedia

Monday, January 2, 2017

LEGO-style nanolayer self assembly for future logic and memory devices

Self-assembly of molecules that spontaneously form ordered phases exhibiting well-defined nanoscale periodicity and shapes may be used for future Logic, Memory and intreconnects. However, until to day these have been limited to lamellae or hexagonally packed cylinders.

A team of researchers at Brookhaven National Laboratory have recently showed how soft self-assembling materials—block copolymer thin films—can be manipulated to form a diverse library of previously unreported morphologies. The processes s modules can be repeated as an iterative self-assembly as described in the figure below.

You can read all about these exciting results it in the Open Source publication in Nature Communications: Rahman, A. et al. Non-native three-dimensional blockcopolymer morphologies. Nat. Commun. 7, 13988 doi: 10.1038/ncomms13988 (2016). 

(a) The responsive assembly strategy begins by depositing a neutral brush on the substrate of interest. A block copolymer (BCP) film is then spin-coated on the substrate and annealed to yield a well-defined morphology. Selective infiltration synthesis (SIS) is used to load one of the BCP domains with alumina; this process ‘fixes’ the thin film, making it robust and insoluble, and generates height variation between the domains. The fixed BCP film can be used as the substrate in a subsequent round of ordering. The height variation (which remains after depositing the neutral brush) templates the subsequent BCP layer, causing it to align and register in a well-defined way. Single-layer, bi-layer or multilayer inorganic replicas can be formed by ashing the film (exposure to O2 plasma), as shown in the right-most column. (b) Cross-sectional scanning electron microscopy (SEM) of an exemplar single-layer infiltrated nanostructure before and after ashing (lamellar-forming BCP, L36). (c) Cross-sectional SEM of an exemplar four-layer nanostructure. False-colour applied to highlight layers (from bottom to top): L104, L74, L36, C132. Scale bars are 100 nm. Released unde Creative Commons 4.0 from Rahman, A. et al. Non-native three-dimensional blockcopolymer morphologies. Nat. Commun. 7, 13988 doi: 10.1038/ncomms13988 (2016). 

Tuesday, January 12, 2016

Stanford presents Area Selective ALD to Develop Higher Performing, More Energy Efficient Electronics

Press release: Stanford University researchers sponsored by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductor technologies, have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors. 

The Stanford researchers employ the intrinsically selective adsorption of octadecylphosphonic acid self-assembled monolayers on Cu over SiO2 surfaces to selectively create a resist layer only on Cu. ALD is then performed on the patterns to deposit a dielectric film. A mild etchant is subsequently used to selectively remove any residual dielectric film deposited on the Cu surface while leaving the dielectric film on SiO2 unaffected. The selectivity achieved after this treatment, measured by compositional analysis, is found to be 10 times greater than for conventional area selective ALD. "Reprinted (adapted) with permission from (ACS Nano, 2015, 9 (9), pp 8710–8717, DOI: 10.1021/acsnano.5b03125). Copyright (2015) American Chemical Society."
Press release Continued :
It is well known that next-generation electronic, optoelectronic and sensing devices that contain nanoscale dimensions face increasingly difficult materials and fabrication challenges as the downward scaling of these devices continues. Conventional semiconductor manufacturing processes are time-consuming and expensive, in part due to the need for lithographic patterning. The Stanford research leverages simple ALD and etching processes that eliminate this lithography step and improve selective deposition of dielectric materials by more than 10 times in film thickness compared to similar advanced processes.

Due to difficulties of current top-down fabrication processes that contain multiple deposition, lithography and etching steps, along with problems with misalignment in lithography, using an alternative approach in which the desired materials are directly and selectively deposited would significantly facilitate the process, according to the Stanford team. 
Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.(Picture from Stanford University)
“Our technology is a promising candidate for overcoming the challenges of top-down processing and misalignment because it greatly improves the ability to perform selective deposition of materials. This research introduces a novel processing method to meet the increasingly difficult materials challenges associated with new devices,” said Dr. Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.

Link to Stacy Bent´s Research Group :
Current approaches utilize lithography for nanoscale patterning. Using lithography and etching for fabrication of 2D or 3D structures often results in misaligned features and causes a risk of shorting or high resistant areas. However, selective deposition using ALD can reduce these risks and reduce the process time and steps.

Bent explained that selective deposition allows layers of material to be added onto a substrate only where desired without the need for additional lithography steps. However, the high level of selectivity needed for a manufacture-worthy process has not yet been achieved in area selective deposition studies. In addition, most methods for area selective deposition require long processing times.

The Stanford research has been focused on selective deposition of dielectric materials on metal/dielectric patterns. These type of structures can be found in interconnects and back-end-of-line (BEOL) processing. With ALD being used in other stages of the device fabrication process as well, the results from the Stanford experiments can potentially be applied to a variety of nanoscale electronic, optoelectronic and sensing devices.

The research developments occurred during the second year of research on the topic, and the Stanford team is continuing to explore new methods for area selective ALD to improve both selectivity and manufacturability.

“The Stanford team’s research has shown for the first time that, by following selective deposition of a dielectric material using pre-treatment by an inhibitory material, they can significantly reduce the process time (from 48 hours to less than 1 hour) and also improve the limits of selective deposition of dielectrics by more than 10 times,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC.

Saturday, July 12, 2014

Self assembly of 15,000 semiconductor chips per hour

The Next Big Future Blog reports on a A first automated reel-to-reel fluidic self-assembly process for macroelectronic applications. The system enables high speed assembly of semiconductor dies (15,000 chips per hour using a 2.5 cm wide web) over large area substrates. The optimization of the system (hour 99% assembly yield) is based on identification, calculation, and optimization of the relevant forces. As an application the production of a solid state lighting panel is discussed involving a novel approach to apply a conductive layer through lamination.

A First Implementation of an Automated Reel-to-Reel Fluidic Self-Assembly Machine 
Se-Chul Park , Jun Fang , Shantonu Biswas , Mahsa Mozafari , Thomas Stauden , and Heiko O. Jacobs
Adv. Mater. 2014, DOI: 10.1002/adma.201401573 (Free down load)

In this communication, we report on recent progress towards a fi rst implementation of a self-assembly machine that is based on surface-tension-directed-self-assembly. The reported assembly process is no longer a discontinuous smallbatch hand-operated process but resembles an automated machine like process involving a conveyer belt and a reel-to-reel (RTR) type assembly approach with automated agitation. As a comparison, the assembly rate of conventional chip level pick-and-place machines depends on the cost of the system and number of assembly heads that are used. For example, a highend FCM 10000 (Muehlbauer AG) fl ip chip assembly system can assemble approximately 8000 chips per hour achieving a placement accuracy of 30 μm. 

Our current design achieves 15 k chips per hour using a 2.5 cm wide assembly region which is only a factor of 2 better than one of the faster pick-and-place machines; scaling to 150 k chips per hour, however, would be possible using a 25 cm wide web, which would be a factor of 20 faster. 

In principle, scaling to any throughput should be possible considering the parallel nature of self-assembly. In terms of placement accuracy our precision increase with a reduction of chip and solder bump size. Generally, it exceeds the 30 μm limits for the components that have been used. Under optimized operational conditions, we achieved an assembly yield of 99.8% using the self-assembly process. As an application the assembly machine is applied to the realization of area lighting panels incorporating distributed inorganic light emitting diodes (LEDs).

Tuesday, April 15, 2014

More Three-Dimensional Nanofabrication using Block Copolymer Self-Assembly by KAIST

In a recent blog post here reported about KAIST and others presented "ALD Assisted Pattern Multiplication of Block Copolymer for 5 nm Scale Nanopatterning". There seems to be no end to this topic here is a more full coverage in the form of a review paper "Three-Dimensional Nanofabrication using Block Copolymer Self-Assembly" [Free to download - thank you very much indeed!] work by KAIST.

“Three-Dimensional Nanofabrication by Block Copolymer Self-Assembly”

Caroline A. Ross*, Karl K. Berggren, Joy Y. Cheng, Yeon Sik Jung,* and Jae-Byum
Advanced Materials, 2014, published online

Thin films of block copolymers are widely seen as enablers for nanoscale fabrication of semiconductor devices, membranes, and other structures, taking advantage of microphase separation to produce well-organized nanostructures with periods of a few nm and above. However, the inherently threedimensional structure of block copolymer microdomains could enable them to make 3D devices and structures directly, which could lead to effi cient fabrication of complex heterogeneous structures. This article reviews recent progress in developing 3D nanofabrication processes based on block copolymers.

Check out this great page with access to most of the papers from The Functional Nanofabrication Lab at KAIST as free download - FUNNANO!