Ultratech Cambridge Nanotech Enter Into JDP With IMEC To Study Area-Selective Deposition Technology

SAN JOSE, Calif., June 8, 2016 /PRNewswire/ -- Ultratech, Inc. (Nasdaq: UTEK), a leading supplier of lithography, laser­ processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HB­ LEDs), as well as atomic layer deposition (ALD) systems, announced that its Cambridge Nanotech business unit Ultratech-CNT has entered into a Joint Development Program (JDP) with IMEC in the field of Area-Selective Deposition (ASD) technology. The ASD project will concentrate on the study and use of Self-Assembled Monolayers (SAMs) as a means of functionalizing surfaces to selectively inhibit ALD-grown films. Ultratech-CNT's Savannah S300 ALD system will be used for this project to explore the use of SAMs and ALD films on 300-mm wafers using a single platform. 

Laurent Lecordier, Ph.D., senior research scientist at Ultratech-CNT, has been active in research that combines SAMs and ALD. According to Lecordier, "The broader implications of this technology suggest that we will not only be able to address the field of ASD, but we will also be able to make positive contributions in industrially-relevant areas, such as low-k pore filling, work function modifications, and surface energy tuning. With the JDP in place, I am very much looking forward to participating in this work, which has garnered strong industrial and academic interest."

Given the large potential for producing disruptive applications using the combined SAMs and ALD system, (including ASD, low-k pore filling, work function modifications, surface energy tuning, and novel materials growth), Ultratech-CNT believes this collaborative program will yield high impact results.

Savannah S300 ALD System
The Savannah family of ALD systems (S100, S200, S300) has become the preferred system for university researchers worldwide engaged in ALD and looking for an affordable yet robust platform. With a wide array of process oriented options, such as low vapor pressure precursor delivery, and plasma, along with a range of real-time analytical options such as in-situ ellipsometry, in-situ quartz crystal microbalance, and mass spectrometry -- the Savannah enables the serious researcher to deposit and study a broad spectrum of single and multi-component ALD films and Self-assembled Monolayers. With over 1000 peer-reviewed journal publications referencing its ALD systems, Ultratech-CNT's ALD instruments maintain a leading position as the tools-of-choice among active researchers.

UPDATE: Area Selective Deposition Workshop - ASD 2016 hosted by Imec

Imec and the COST action HERALD will host a workshop dedicated to Area Selective Deposition “ASD 2016”, at imec in Leuven, Belgium on April 15th, 2016. This workshop will provide an excellent opportunity for the R&D community to learn about Area Selective Deposition and it will offer a forum for open discussions between researchers from academia and industry. We look forward to your participation.

The workshop will focus on the fundamental mechanisms of ASD processes and nucleation, as well as on the challenges related to the characterization of selectivity. Potential applications of selective deposition will be discussed.

The 1 day program will consist of:

• Presentations by invited speakers on the fundamentals and characterization of selectivity
• A panel discussion about potential applications of selective deposition
• A poster session covering selective deposition as well as nucleation. Poster contributions are welcome by abstract submission
• Coffee breaks, lunch and diner

Confirmed invited speakers: 

Soley Ozer (Intel), Mikko Ritala (Helsinki University), Erwin Kessels (TU Eindhoven), Simon Elliott (Tyndall National Institute), Gregory Parsons (North Caroline State University), Christos Takoudis (University of Illinois at Chicago), Hyungjun Kim (Yonsei University), Wilfried Vandervorst (imec), Manfred Buck (St Andrews University), Jim Engstrom (Cornell University)

Registration module is open - Deadline: March 25th, 2016.

- Poster contributions are welcome by abstract submission (see website). Deadline: March 15th, 2016. The poster session is covering area-selective deposition as well as nucleation.

- HERALD travel support: HERALD members can apply for travel support by sending a short motivation letter and CV to asd2016@imec.be. Deadline: March 2nd, 2016.

For more information please visit http://www2.imec.be/be_en/education/conferences/asd-workshop-2016/home.html.

More information is available at http://www2.imec.be/be_en//education/conferences/asd-workshop-2016.html

Stanford presents Area Selective ALD to Develop Higher Performing, More Energy Efficient Electronics

Press release: Stanford University researchers sponsored by Semiconductor Research Corporation (SRC), the world’s leading university-research consortium for semiconductor technologies, have developed a new area selective atomic layer deposition (ALD) process that promises to accelerate the manufacturing of higher performing, more energy efficient semiconductors. 

The Stanford researchers employ the intrinsically selective adsorption of octadecylphosphonic acid self-assembled monolayers on Cu over SiO2 surfaces to selectively create a resist layer only on Cu. ALD is then performed on the patterns to deposit a dielectric film. A mild etchant is subsequently used to selectively remove any residual dielectric film deposited on the Cu surface while leaving the dielectric film on SiO2 unaffected. The selectivity achieved after this treatment, measured by compositional analysis, is found to be 10 times greater than for conventional area selective ALD. "Reprinted (adapted) with permission from (ACS Nano, 2015, 9 (9), pp 8710–8717, DOI: 10.1021/acsnano.5b03125). Copyright (2015) American Chemical Society."
 

Press release Continued :

 

It is well known that next-generation electronic, optoelectronic and sensing devices that contain nanoscale dimensions face increasingly difficult materials and fabrication challenges as the downward scaling of these devices continues. Conventional semiconductor manufacturing processes are time-consuming and expensive, in part due to the need for lithographic patterning. The Stanford research leverages simple ALD and etching processes that eliminate this lithography step and improve selective deposition of dielectric materials by more than 10 times in film thickness compared to similar advanced processes.

Due to difficulties of current top-down fabrication processes that contain multiple deposition, lithography and etching steps, along with problems with misalignment in lithography, using an alternative approach in which the desired materials are directly and selectively deposited would significantly facilitate the process, according to the Stanford team. 

 

 

Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.(Picture from Stanford University)

 

“Our technology is a promising candidate for overcoming the challenges of top-down processing and misalignment because it greatly improves the ability to perform selective deposition of materials. This research introduces a novel processing method to meet the increasingly difficult materials challenges associated with new devices,” said Dr. Stacey Bent, Department of Chemical Engineering Chair and Jagdeep and Roshni Singh Professor in School of Engineering, Stanford University.

Link to Stacy Bent´s Research Group : http://bentgroup.stanford.edu/
 

Current approaches utilize lithography for nanoscale patterning. Using lithography and etching for fabrication of 2D or 3D structures often results in misaligned features and causes a risk of shorting or high resistant areas. However, selective deposition using ALD can reduce these risks and reduce the process time and steps.

Bent explained that selective deposition allows layers of material to be added onto a substrate only where desired without the need for additional lithography steps. However, the high level of selectivity needed for a manufacture-worthy process has not yet been achieved in area selective deposition studies. In addition, most methods for area selective deposition require long processing times.

The Stanford research has been focused on selective deposition of dielectric materials on metal/dielectric patterns. These type of structures can be found in interconnects and back-end-of-line (BEOL) processing. With ALD being used in other stages of the device fabrication process as well, the results from the Stanford experiments can potentially be applied to a variety of nanoscale electronic, optoelectronic and sensing devices.

The research developments occurred during the second year of research on the topic, and the Stanford team is continuing to explore new methods for area selective ALD to improve both selectivity and manufacturability.

“The Stanford team’s research has shown for the first time that, by following selective deposition of a dielectric material using pre-treatment by an inhibitory material, they can significantly reduce the process time (from 48 hours to less than 1 hour) and also improve the limits of selective deposition of dielectrics by more than 10 times,” said Kwok Ng, Senior Science Director of Nanomanufacturing Materials and Processes at SRC.

Can ALD save Moore´s Law?

Can ALD save Moore´s Law? - I would say it already did at the introduction og HKMG and some other things. Here is a great peace by Mark Lapedus with some insights from the leading extperts of industry and academia and I selected to high light some of them below:

Can Nano-Patterning Save Moore’s Law?

Selective deposition is showing promise in the lab, but it’s a long way from there to production.

For years the academic community has explored a novel technology called selective deposition. Then, more than a year ago, Intel spearheaded an effort to bring the technology from the lab to the fab at 7nm or 5nm. Today, selective deposition is still in R&D, but it is gaining momentum in the industry.

 “In order to make ALD-enabled nano-patterning available in the semiconductor industry, careful ALD precursor and reactant selections are required,” Samsung’s Han Jin Lim said.  

“There are a couple of places where selective deposition has been done in the past. But the applications have been pretty specific, where we have gotten our arms around the defectivity issues,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “But anytime you go selective and deposition, you’ve have to make sure the defectivity and other issues are solved. As we learn more about it, we’ll see more applications coming out of it.”

“With SAM, it might be possible to do selective-area ALD or CVD by area-deactivation,” said Erwin Kessels, a professor at the Eindhoven University of Technology. “But this only provides a solution in cases where the substrate is already patterned. Selective deposition by area-deactivation doesn’t really help you in most cases when you really want to generate patterns from the bottom-up, which is the ultimate aim. Yet, it would still be helpful to reduce the number of litho steps.”

Continue reading : http://semiengineering.com/can-nano-patterning-save-moores-law/ 

ALD-enabled nano-patterning

Here is a very good text by Mark Lapedus on ALD patterning technology from the Semiconductor Engineering Blog:

New Patterning Paradigm?

Selective deposition may be the way forward to the far reaches of device scaling after 7nm.

APRIL 16TH, 2015 - BY: MARK LAPEDUS

Chip scaling is becoming more difficult at each process node, but the industry continues to find new and innovative ways to solve the problems at every turn. And so chipmakers continue to march down the various process nodes. But the question is for how much longer? In fact, at 16nm/14nm and beyond, chipmakers are finding new and different challenges, which, in turn, could slow IC scaling or bring it to a sudden halt one day.

To prevent those occurrences, chipmakers are working on a multitude of technologies. But one in particular is gaining steam in the lab—selective deposition. Some call the technology ALD-enabled nano-patterning.

At least in theory, selective deposition is a paradigm shift in chip manufacturing that could help extend IC scaling. But researchers still have some issues to solve to make this technology viable. And even then, it is not expected to appear until 7nm or 5nm.

For decades, chipmakers have used deposition, which is a process that deposits a blanket of thin material on a surface. In contrast, combining novel chemistries with atomic layer deposition (ALD) or molecular layer deposition (MLD) tools, selective deposition involves a process of depositing materials and films in exact places. Selective deposition can be used to deposit metals on metals and dielectrics on dielectrics on a device.

Continue reading : http://semiengineering.com/new-patterning-paradigm/

Please also do check out this Review, that I have blogged about before, by Prof. Kessels et al on this topic!

The use of atomic layer deposition in advanced nanopatterning

A. J. M. Mackus, A. A. Bol and W. M. M. Kessels

Nanoscale, 2014,6, 10941-10960 

DOI: 10.1039/C4NR01954G, Review Article

Atomic layer deposition (ALD) is a method that allows for the deposition of thin films with atomic level control of the thickness and an excellent conformality on 3-dimensional surfaces. In recent years, ALD has been implemented in many applications in microelectronics, for which often a patterned film instead of full area coverage is required. This article reviews several approaches for the patterning of ALD-grown films. In addition to conventional methods relying on etching, there has been much interest in nanopatterning by area-selective ALD. Area-selective approaches can eliminate compatibility issues associated with the use of etchants, lift-off chemicals, or resist films. Moreover, the use of ALD as an enabling technology in advanced nanopatterning methods such as spacer defined double patterning or block copolymer lithography is discussed, as well as the application of selective ALD in self-aligned fabrication schemes.

Issues and options for using selective ALD at 5nm

Here is a very good blog by Mark Lapedus on scaling down some additional nodes. Mark Lapedus is Executive Editor for manufacturing at Semiconductor Engineering.

One of the more interesting option for all us ALD freaks besides the NGLs, there is another emerging option—selective deposition. Below I have cut out that part and please do forward any good open avaialble information on this topic to me (jonas.sundqvist@baldengineering.com) or simply post a comment here!

Still in the R&D stage, selective deposition could be used to selectively deposit materials, namely metals on metals and dielectrics on dielectrics, on a device. “There are a lot of people thinking about
this today,” said Girish Dixit, vice president of process applications for Lam Research . “There are many areas that selective deposition could be used in, including doing edges or removing something at the expense of something.

Selective deposition involves the use of special chemistries and existing atomic layer deposition (ALD) tools. It also makes use of molecular layer deposition (MLD), which is similar to ALD. “With MLD,you are typically making something that is primarily an organic,composed of carbon, nitrogen, oxygen and hydrogen. In classic ALD, you are making inorganic materials. There are also hybrids,” said James Engstrom, a professor in the School of Chemical and Biomolecular Engineering at Cornell University. There are some differences between traditional ALD and selective deposition using ALD. “The difference is you somehow trick the ALD process, so that it grows on material A, but does not grow on material B,” Engstrom said.

Selective deposition doesn’t replace lithography, but it does solve a problem—edge placement error. “When you want one thing to line up with another, the ability to control the placement of a feature is getting to be outside the range, because the features are small,” said Gregory Parsons, a professor in the College of Engineering at North Carolina State University.

In a theoretical flow, a lithography tool would first pattern a surface. “So, if there is a pattern available on the surface that you want to selectively deposit, then your material that you are forming would then align to the pattern that is underneath the substrate,” Parsons said. “Instead of a physical mask to align, you would want to use the chemistry of the surface to do the alignment. And if the process can recognize that selective chemical difference, then we can deposit materials exactly where we want.”

Still, the technology is unproven and there are challenges. But if the technology works, it could possibly change the landscape in IC manufacturing. “Once the ball is rolling, and you can do selective deposition on anything, then the applications will expand,” Lam’s Dixit added.

Full Story here: http://semiengineering.com/issues-and-options-at-5nm/#.VQrjFVPwzdg.linkedin

Good papers on the topic:

The use of atomic layer deposition in advanced nanopatterning by Kessels et al

Atomic layer deposition (ALD) is a method that allows for the deposition of thin films with atomic level control of the thickness and an excellent conformality on 3-dimensional surfaces. In recent years, ALD has been implemented in many applications in microelectronics, for which often a patterned film instead of full area coverage is required. This article reviews several approaches for the patterning of ALD-grown films. In addition to conventional methods relying on etching, there has been much interest in nanopatterning by area-selective ALD. Area-selective approaches can eliminate compatibility issues associated with the use of etchants, lift-off chemicals, or resist films. Moreover, the use of ALD as an enabling technology in advanced nanopatterning methods such as spacer defined double patterning or block copolymer lithography is discussed, as well as the application of selective ALD in self-aligned fabrication schemes.