Breaking the Copper Bottleneck: Lam Research’s Mo-ALD ALTUS Halo Enables Next-Generation Hybrid Metallization

Lam Research now offers molybdenum (Mo) atomic layer deposition (ALD) with its ALTUS Halo platform, introduced in 2025 as the first high-volume ALD tool designed for Mo metallization. The system enables conformal and selective, bottom-up deposition of low-resistivity, void-free Mo films, targeting advanced logic, memory, and 3D NAND applications where conventional copper and tungsten interconnects face scaling and reliability limits. This positions Lam’s Mo-ALD as a key enabler for next-generation BEOL hybrid metallization schemes.

Current density of various metal/via schemes. Red and green areas indicate higher current density.  

Hybrid metallization using Mo shows strong potential to overcome the scaling limitations of conventional copper dual damascene (Cu DD) processes in advanced semiconductor BEOL interconnects. As device dimensions shrink, Cu faces challenges such as increased resistivity, barrier thickness limitations, and stress-induced voids (SIVs), all of which degrade performance. Mo hybrid metallization, which uses bottom-up barrierless metal deposition before a conventional Cu process, significantly reduces resistance—by about 55% compared to Cu DD—and further by 15% with selective barrier deposition (SBD). This lower resistance translates into higher current densities and improved reliability. Stress distribution studies also reveal that Mo hybrid vias exhibit lower void formation risks than Cu due to smaller stress gradients at the via/barrier interfaces.

Comparison of via and line resistance for conventional Cu dual damascene and Mo hybrid metallization schemes. Mo vias reduce total resistance by ~35% without selective barrier deposition (SBD), with an additional ~20% reduction when fully replacing Cu. Applying SBD further lowers resistance, achieving up to ~55% reduction compared to the Cu baseline.

Optimization studies, performed with SEMulator3D® simulations, identified key parameters like via critical dimensions, height, and material stress properties that impact resistance, capacitance, and hydrostatic stress. Findings show that increasing Mo via height lowers resistance but raises stress, suggesting an optimal fill height around 25 nm for balancing performance and reliability. Intrinsic stress of Mo and process temperature tuning were also shown to mitigate stress-induced reliability issues, with 400°C identified as a favorable condition. Ultimately, hybrid metallization with Mo offers a scalable path forward, combining electrical and mechanical benefits, while virtual DOE and process modeling enable predictive optimization without extensive wafer-based experiments.

Sources:

Breaking the Copper Bottleneck With Molybdenum Hybrid Metallization

Lam Research Ushers in New Era of Semiconductor Metallization with ALTUS® Halo for Molybdenum Atomic Layer Deposition - Feb 19, 2025

ALD News Week 38

Solid-state batteries get a boost with new protective coating

Link: https://www.anl.gov/article/solidstate-batteries-get-a-boost-with-new-protective-coating

“A thin, glass-like layer could help protect solid-state batteries from degradation, researchers say. They use a process called atomic layer deposition (ALD) to apply a protective layer.” (ANL)

Microwave enhanced atomic layer deposition (MW-ALD): Incorporating a microwave antenna into an ALD reactor
Link: https://pubs.aip.org/avs/jva/article/43/5/052403/3361679/Microwave-enhanced-atomic-layer-deposition-MW-ALD

“Atomic layer deposition (ALD) is a technique widely used for thin film deposition with excellent uniformity and conformality. In this work, we present a modification of a conventional ALD system by integrating a microwave antenna to explore how microwave energy can enhance film growth and reduce cycle times, particularly for materials that are otherwise difficult to deposit.” (AIP Publishing)

Impacts of different thickness Al2O3 and SiO2 atomic layer deposition sidewall passivation layers on GaN-based devices
Link: https://pubs.aip.org/avs/jvb/article/43/5/052209/3361926/Impacts-of-different-thickness-Al2O3-and-SiO2-atomic-layer-deposition-sidewall
 
“The sidewall passivation layer has a critical effect on the performance and reliability of GaN-based devices. In this study, we investigate how varying the thickness of atomic layer deposition (ALD) Al₂O₃ and SiO₂ sidewall passivation layers influences device leakage, breakdown voltage, and surface recombination. The results show that thicker layers can better suppress leakage but may lead to trade-offs in other device parameters.” (AIP Publishing)

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Forge Nano to Unveil Commercial Single Module Semiconductor Wafer Fab ALD Tool at SEMICON Taiwan
Link: https://www.globenewswire.com/news-release/2025/09/04/3144564/0/en/Forge-Nano-to-Unveil-Commercial-Single-Module-Semiconductor-Wafer-Fab-ALD-Tool-at-SEMICON-Taiwan.html

DENVER, Sept. 04, 2025 (GLOBE NEWSWIRE) -- Forge Nano, Inc., a technology company pioneering domestic battery and semiconductor innovations, today announced it is unveiling a new commercial single module semiconductor wafer fab atomic layer deposition (ALD) tool – TEPHRA^{One}. The fully automated 200 mm single module platform is outfitted with features from Forge Nano’s flagship multi-process module TEPHRA in a streamlined configuration for oxide, nitride, metal and nanolaminate coatings. (GlobeNewswire)

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New Tool Announcement: Thermal/Plasma ALD System Now Available for User Access
Link: https://nanofab.ucsd.edu/new-tool-announcement_thermal-plasma-ald-system/

We are happy to announce that the new Arradiance GEMStar Thermal & Plasma ALD (Atomic Layer Deposition) System is now available for user access. This advanced system supports both thermal and plasma enhanced ALD processes and is designed to allow users to explore a wide range of thin film materials and process conditions. (nanofab.ucsd.edu)

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Press Release “ALD for Industry 2025” - Dresden
Link: https://efds.org/en/45604/

Dresden, March 12, 2025 – The 8th International Conference “ALD FOR INDUSTRY” has once again bridged the gap between basic research, industrialization and commercialization of atomic layer deposition (ALD). This event, which has been held annually in Dresden since 2017, once again welcomed over 100 participants from 14 countries and numerous exhibitors this year despite the strike at German airports. (efds.org)

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News & Announcements: Continuous, high-speed atomic layer deposition for thin-film coatings
Link: https://www.anl.gov/amd/news-announcements

“Self-exhausting” precursor pulses enable fast, precise coating applications for … (ANL)

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TSMC’s 2 nm Fabs Lock Out China OEMs, Securing ALD and Process Tool Demand for US, European, and Japanese Tier-1 Suppliers

TSMC’s decision to exclude Chinese equipment vendors from its 2 nm fabs in Taiwan and the US reshapes the competitive landscape in favor of Japanese, American, and European suppliers. With the 2 nm node set to become the largest in history by wafer volume and revenue potential, this policy shift effectively concentrates demand among a handful of Tier 1 players —ASMI, TEL, Applied Materials, and Lam Research—who already dominate in deposition, etch, and cleaning tools essential for nanosheet GAA and backside power delivery. No need to mention ASML.

Announced in January: TSMC is advancing with its 2 nm (N2) technology, establishing a pilot line at its Hsinchu Baoshan Fab 20 with an initial monthly output of around 3,000–3,500 wafers. By combining production from Hsinchu and Kaohsiung, the company expects to exceed 50,000 wafers per month by the end of 2025 and reach about 125,000 wafers per month by the end of 2026. Output at Hsinchu should rise to 20,000–25,000 wafers per month by late 2025 and 60,000–65,000 by early 2027, while Kaohsiung is projected to produce 25,000–30,000 wafers monthly by late 2025 and also expand to 60,000–65,000 by early 2027. Chairman C.C. Wei has highlighted that demand for 2 nm exceeds that of 3 nm, driven by its 24–35% lower power consumption, 15% performance boost at the same power, and 15% higher transistor density. Apple will be the first adopter, followed by MediaTek, Qualcomm, Intel, NVIDIA, AMD and Broadcom.

TSMC will start 2 nm mass production in Taiwan in the second half of 2025, initially with Fab 22 in Kaohsiung as the anchor site for yield learning. The first ramp is set at 40,000 wafers per month, expanding to 100,000 wafers per month in 2026 and reaching 200,000 wafers per month by 2027, making N2 the largest and most profitable node in TSMC’s history.

In the US, Arizona Fab 21 is being developed in phases. Phase 1 is already producing 4 nm chips, Phase 2 will start 3 nm by late 2025 or early 2026, and Phase 3 is planned for 2 nm and A16-class chips toward the end of the decade. This ensures that while Taiwan remains the cost-optimized base for N2 production, Arizona provides premium, subsidy-supported capacity for US customers, diversifying geographic and geopolitical risk.

Overall, Taiwan will carry the bulk of N2 output and cost efficiency, while Arizona secures local supply for strategic US clients like Apple, Nvidia, AMD, and Intel. By 2027, with 200,000 wafers per month globally, N2 alone could generate nearly $50 billion annually, cementing TSMC’s central role in powering AI and HPC expansion.

The move aligns directly with Washington’s Chip EQUIP Act, which ties subsidies to avoiding “foreign entities of concern.” By pre-emptively removing Chinese tools, TSMC safeguards its access to US incentives while giving its global customers—Apple, Nvidia, AMD, and Intel—assurance that supply chains are insulated from geopolitical risk. This codifies the leading suppliers as the “trusted” baseline for advanced-node capacity worldwide, effectively reinforcing their moat at the most profitable process node ever.

For ASMI, TEL, AMAT, and Lam, the outlook is very positive. With Chinese competitors pushed out, these companies can win more business and have stronger pricing power. At the same time, 2 nm wafer prices are climbing toward $30,000, far above older smartphone-focused nodes. TSMC is reviewing its suppliers for profit margins and China ties, but these four are essential for 2 nm production, so they are more likely to gain from rising demand and higher-value tools than lose ground. Put simply, the 2 nm era is set to drive lasting growth and profits for them as AI adoption accelerates through 2027.

Chinese semiconductor equipment OEMs that are cut out from TSMC’s 2 nm fabs under the new restrictions and supplier realignment:

• AMEC (Advanced Micro-Fabrication Equipment Inc.) – leading Chinese etch tool supplier, with relevance in dielectric etch and epitaxy
• Naura Technology Group – broad portfolio in etch, deposition, and cleaning tools
• Mattson Technology (China-owned, via E-Town Dragon Semiconductor) – focuses on dry strip, rapid thermal processing (RTP), and etch
• SMEE (Shanghai Micro Electronics Equipment) – China’s only domestic lithography tool maker (far behind in capability, but relevant in domestic fabs)
• Kingsemi – maker of ALD/CVD equipment, mainly for memory and advanced logic
• Piotech – deposition (CVD, PECVD, ALD) equipment vendor
• ACM Research (China) – cleaning and electrochemical deposition tools (though headquartered in the US, its operations are China-based and increasingly seen as China OEM)

At TSMC’s 2 nm fabs, the exclusion of Chinese equipment vendors channels ALD equipment demand entirely to US, European, and Japanese suppliers. ASM International (Europe) remains the clear leader in single-wafer ALD for high-k metal gate stacks and nanosheet spacers, with Applied Materials and Lam Research (US) competing in selective and plasma ALD for gate-all-around and backside power steps, while Tokyo Electron and Kokusai Electric (Japan) cover both single-wafer and batch ALD, particularly for spacer and liner deposition. By contrast, Chinese ALD players such as Naura, Kingsemi, and Piotech, while active in domestic logic and memory at 28–14 nm and some 7 nm non-EUV capacity, will not gain any capability at N2 and are explicitly excluded under TSMC’s supplier policy and US subsidy rules, leaving the largest and most profitable ALD opportunity in history to be divided among the established US, European, and Japanese Tier-1 suppliers.

Sources:

TSMC reportedly cuts Chinese chipmaking tools from 2nm fabs as suppliers face scrutiny due to emerging new US restrictions | Tom's Hardware

https://open.substack.com/pub/drrobertcastellano/p/tsmcs-2-nm-era-technology-leadership?r=l0uj0&utm_campaign=post&utm_medium=web&showWelcomeOnShare=false

TSMC Is Getting Ready to Launch Its First 2nm Production Line | TechPowerUp

Chipmetrics expands metrology portfolio with advanced test chips and wafer solutions for next-gen ALD semiconductor processes

Finnish metrology specialist Chipmetrics has expanded its portfolio with a new range of advanced test chips and wafer solutions aimed at accelerating prototyping and enhancing precision in next-generation semiconductor process development. The new releases include the ASD-1b area-selective deposition chip, a High Surface Area wafer, and pre-coated High Aspect Ratio test structures such as PillarHall and VHAR1. These tools are designed to simulate real-world manufacturing conditions with greater accuracy, helping engineers optimise processes more efficiently and reduce development cycles in ALD and other thin-film applications.

The ASD-1b chip provides a tricolour material layout with metal, SiO₂ and Si₃N₄ surfaces, enabling detailed assessment of selectivity and defectivity across multiple deposition techniques. Meanwhile, the new HSA wafer delivers up to 300 times greater surface area sensitivity through deep trench designs, supporting ultra-sensitive material studies. By offering pre-coated HAR structures, Chipmetrics addresses the growing industry demand for realistic conformality and uniformity testing. According to CEO Mikko Utriainen, these solutions are set to streamline benchmarking of new chemistries and processes, giving development teams faster, clearer feedback to advance semiconductor innovation.

Chipmetrics’ new metrology tools for advanced thin film process development. Left: Pre-coated high aspect ratio test structures, including PillarHall® (lateral AR > 1000) and VHAR1 (vertical AR = 200), for evaluating conformality and film penetration. Centre: The ASD-1b area selective deposition test chip with tricolour material layout for testing selectivity across Cu, SiO₂ and Si₃N₄ surfaces. Right: High Surface Area (HSA) wafer combining a 150 mm VHAR1 wafer within a 300 mm pocket wafer, providing up to 300× enhanced surface area for sensitive material studies.

Source:

Chipmetrics Expands Product Line with Advanced ALD Test Chips and Wafer Solutions - Chipmetrics

Shaping the Future of Thin Films: New Trends in Thermal ALD Chemistry

A new review published in the Journal of Vacuum Science & Technology A takes a detailed look at recent developments in thermal atomic layer deposition (ALD) chemistry, drawing on data from the comprehensive ALD database at atomiclimits.com. The analysis highlights how process innovations have accelerated since 2010, with more than half of all reported ALD processes emerging in the past 15 years. Binary oxides remain the dominant material group, but there has been a steady increase in the deposition of non-oxides and ternary compounds. More recently, classes such as elemental metals, two-dimensional transition metal dichalcogenides, and halides have gained prominence, driven largely by application demands in microelectronics, energy technologies, and catalysis. The study also notes the introduction of new elements into the ALD portfolio after 2010, including alkali metals and more exotic elements such as rhenium, osmium, gold, and antimony, each requiring unique process routes.

The review underscores the critical role of precursor chemistry in enabling these advances. While traditional precursors such as halides, alkoxides, and β-diketonates laid the foundation, newer processes have leaned heavily on amides and imides, followed by cyclopentadienyl compounds. However, the most significant trend is the growing reliance on heteroleptic precursors, which combine multiple ligand types to fine-tune key properties such as volatility, reactivity, and thermal stability. This flexibility has been instrumental in broadening the range of materials accessible via ALD and tailoring processes to meet the specific requirements of cutting-edge applications. Overall, the work reflects how ALD chemistry has evolved from relatively narrow beginnings into a dynamic and application-driven field with expanding industrial significance.

Source:

The review is based on ALD chemistries collected from the AtomicLimits ALD precursor database: Database of ALD processes

Popov, G.; Mattinen, M.; Vihervaara, A.; Leskelä, M. (2025). “Recent trends in thermal atomic layer deposition chemistry.” Journal of Vacuum Science & Technology A, 43, 030801. https://doi.org/10.1116/6.0004320

Beneq Secures Repeat Orders as ALD Gains Ground in MicroLED Display Market

Espoo, Finland, 14 July 2025 – Beneq, a global leader in Atomic Layer Deposition (ALD) technology, has announced significant momentum in the microLED display sector, marked by repeat orders from leading tech innovators. The development highlights the growing demand for advanced manufacturing tools capable of supporting the next generation of display technologies.

MicroLED is increasingly seen as a transformative display technology across consumer electronics, augmented and virtual reality (AR/VR), and the automotive sector. Offering superior brightness, contrast, energy efficiency and durability, microLED enables ultra-fine resolution, longer device lifetimes and seamless scalability.

According to Yole Group, global microLED display shipments are expected to grow at a compound annual rate of 180.6 percent from 2022, reaching 42.4 million units by 2029. However, manufacturing challenges remain, particularly as pixel sizes shrink below 10 micrometres. ALD plays a critical role in overcoming these hurdles by delivering ultra-thin, conformal coatings that ensure uniformity, stability and surface passivation—key for improving efficiency and reliability.

Beneq Transform® is an ALD cluster tool designed for technology development and manufacturing across power electronics (SiC, GaN, Si), RF, optoelectronics, microLED, MEMS, and sensors.

“Our top-tier customers rely on ALD technology to advance monolithic integration of microLEDs and driver electronics on a single chip,” said Mikko Söderlund, Head of Semiconductor ALD Sales at Beneq. “This enables a new class of compact, high-performance display products with faster data transfer and reduced power consumption.”

Beneq’s Transform® ALD cluster platform is central to its offering, providing high-throughput production capability with a modular, multi-chamber design. The platform supports a range of materials and processes, allowing customers to optimise optical and electrical properties while scaling from lab to fab.

These developments reinforce Beneq’s commitment to supporting microLED pioneers through both early-stage development and the transition to volume manufacturing, accelerating the path toward widespread adoption of advanced display technologies.

Sources: 

Beneq Advances MicroLED Leadership with Growing Demand from Industry Frontrunners | Beneq

Transform® and Transform® Lite

Atomic Scale Processing: A Key Enabler for Scalable and Coherent Quantum Technologies

Recent advances in quantum computing, including IBM’s 1000-qubit chip and imec’s 300 mm wafer transmon qubits, highlight a rapid progression towards scalable, fault-tolerant quantum systems. As quantum platforms such as superconducting and spin-based qubits evolve, the reproducibility and precision of fabrication processes have become essential. Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE) are emerging as critical tools to meet these demands. ALD’s conformal coating capabilities are particularly well-suited for developing 3D structures like through-silicon vias (TSVs), which are essential for high-density, low-loss interconnects in large-scale qubit arrays. However, transitioning ALD to 3D geometries requires careful adjustment of plasma conditions to maintain superconducting properties on vertical sidewalls. Despite these challenges, early successes with materials like TiN and NbN suggest strong potential for ALD in quantum manufacturing.

At the same time, improving surface and interface quality remains central to boosting qubit coherence times. Qubits are highly sensitive to material defects and interfacial contamination, which are known sources of decoherence. ALE’s self-limiting, smooth etching capabilities offer a superior alternative to conventional dry and wet etching by reducing surface roughness and enabling high selectivity. This process can mitigate damage and defects at key interfaces such as metal-air and substrate-air, which are critical loss points in superconducting qubits. The ability of ALE to tailor etch behaviour with high precision makes it a promising method for refining material interfaces and improving device performance. As these atomic-scale techniques continue to mature, they are poised to play a foundational role in the future scalability and reliability of quantum computing platforms.

Sources:

How atomic scale processing can help to pave the way for future quantum devices: A Workshop to bridge ALD/ALE and Quantum communities – Atomic Limits

AlixLabs Secures Notice of Allowance for US Patent for Innovative Semiconductor Manufacturing Technology

Swedish semiconductor startup’s APS™ patent portfolio continues to grow with xth U.S. patent, marking the company’s 10th pending global patent.

Stockholm, Sweden – May 6th, 2025 – AlixLabs is excited to announce that the US Patent and Trademark Office has issued the notice of allowance for the company’s latest patent application, US20250087487A1, titled Formation of an array of nanostructures. This milestone marks the next step in AlixLabs’ commitment to advancing semiconductor manufacturing technologies.

Internally referred to as the “Tetris” patent, in honor of Alexey Pajitnov, the new patent integrates self-aligned double patterning (SADP) with atomic layer etching (ALE)-based pitch splitting (APS™) technology. This innovative approach, being industrialized by AlixLabs since its founding in 2019, combines elements of both classical and leading-edge techniques to deliver superior performance for semiconductor manufacturing.

The invention arose from AlixLabs’ efforts to develop a process for precise sidewall angle control in APS™, a key component in silicon-based processes. By leveraging plasma etch process selectivity and combining features from complex plasma processes, AlixLabs has pioneered a method that blends the traditional SADP process with the advanced APS technology.

This allows the company to utilize mature industrial technologies while benefiting from the advanced control and improved performance of cyclic processes and topographical selectivity. As a result, AlixLabs’ solution offers semiconductor manufacturers an enhanced ability to address the challenges of patterning at sub-5 nm nodes.

This breakthrough is significant for the integration of APS™ technology into existing semiconductor production workflows, preserving the use of existing Process Design Kits (PDKs) which are essential tools for chip designers. By doing so, it reduces the barrier for APS adoption in high-volume manufacturing (HVM), easing the transition to next-generation semiconductor technologies.

The patented innovation provides semiconductor manufacturers with greater flexibility, offering a new way to fine-tune the APS™ process to meet the needs to cut capital and operational expenditure (CapEx and OpEx) as well as emissions for customers at advanced technology nodes, while allowing for broader compatibility with different materials. This new method further strengthens AlixLabs’ core APS™ patent portfolio, positioning the company as a leading enabler of next-generation semiconductor manufacturing.

Moreover, this invention not only supports the development of leading-edge logic, memory, and photonics but also simplifies the semiconductor manufacturing process by reducing CapEx and OpEx for semiconductor fabs.

“We remain committed to advancing semiconductor manufacturing with innovations that significantly enhance the precision, flexibility, and efficiency of our technologies,” commented Dmitry Suyatin, co-founder and CTO of AlixLabs. “This patent represents a critical step forward in our mission to drive the next generation of semiconductor processes and further solidify our position as a leader in the field.”

AlixLabs Secures Notice of Allowance for US Patent for Innovative Semiconductor Manufacturing Technology – AlixLabs

Tokyo Electron Delivers Record FY2025 Results Amid AI Boom, Eyes Growth Through CVD Innovation and Geopolitical Resilience

Tokyo Electron (TEL) achieved a record-breaking financial year in FY2025, with strong top- and bottom-line growth driven by robust global demand for advanced semiconductor equipment. Net sales rose by 32.8% year-on-year to approximately ¥2.43 trillion (around $15.7 billion USD), marking the highest in the company's history. Operating profit surged to ¥697.3 billion (about $4.5 billion USD), supported by an improved operating margin of 28.7%. Growth was underpinned by increased investment in leading-edge logic and memory, particularly High Bandwidth Memory (HBM) and advanced DRAM nodes, where TEL maintained or expanded market share through key Process of Record (POR) wins in etch and wafer bonding technologies. Revenue contributions diversified geographically, with notable gains in South Korea and Taiwan, even as China remained a key market. TEL also demonstrated strong cash flow, increased its R&D and capital investments, and returned significant value to shareholders through dividends and buybacks. Looking ahead, TEL forecasts continued growth in FY2026, positioning itself to capitalise on accelerating AI, 2nm logic, and heterogeneous integration trends.

Tokyo Electron TEL has demonstrated strong financial performance and strategic market expansion through FY2025, according to their investor presentation dated April 30, 2025. Their net sales, gross profit, operating profit, and net income have all reached record highs, signaling both operational efficiency and favorable market conditions.

LINK: Tokyo Electron Limited 2025 Q4 - Results - Earnings Call Presentation (OTCMKTS:TOELY) | Seeking Alpha

Tokyo Electron's Q4 FY2025 earnings call highlighted strong financial performance and an optimistic forward outlook amid geopolitical uncertainties. Despite global concerns around US tariffs and export controls—particularly in China, which saw its WFE market share fall to 35%—TEL stated that it has not observed any significant changes in customer investment sentiment or competitive dynamics. The company reaffirmed its strategy of focusing on long-term innovation rather than short-term regulatory shifts, underscoring its commitment to developing higher-productivity tools to offset potential external headwinds. Looking ahead, TEL forecasts continued double-digit WFE market growth into calendar 2026, driven by AI infrastructure demand, 2nm logic, and HBM scaling. The company plans record-high investments of ¥300 billion in R&D and ¥240 billion in CapEx for FY2026, reflecting confidence in sustained momentum across DRAM, advanced logic, and packaging technologies. TEL aims to expand global market share and reach ambitious mid-term goals, including over ¥1 trillion in operating profit and 35%+ OPM, by capitalising on technology transitions such as GAA, backside PDN, and heterogeneous integration.

LINK: Tokyo Electron Limited (TOELY) Q4 2025 Earnings Call Transcript | Seeking Alpha

Revenue and Profitability Growth:

Net sales increased significantly from ¥1,399.1 billion in FY2021 to ¥2,431.5 billion in FY2025, a 74% increase over four years. The gross profit also rose steadily, reaching ¥1,146.2 billion in FY2025, up from ¥564.9 billion in FY2021. Operating profit followed suit, more than doubling from ¥320.6 billion to ¥697.3 billion. These trends underscore TEL’s ability to scale profitably, with operating margins rising from 22.9% in FY2021 to 28.7% in FY2025. Return on equity (ROE) also remained strong, peaking at 37.2% in FY2022 and settling at 30.3% in FY2025, a testament to effective capital management.

Regional Sales Composition:

The revenue breakdown by region from Q1 FY2024 to Q4 FY2025 shows growing diversification. Notably, China has remained the single largest market, although its share declined from 47.4% in Q4 FY2024 to 34.3% in Q4 FY2025, reflecting a strategic balancing across geographies. South Korea, Taiwan, and North America significantly increased their contributions, with South Korea reaching ¥147.0 billion and Taiwan ¥135.8 billion in Q4 FY2025. This reflects growing demand from advanced logic and memory fabrication customers in these regions.

In FY2025, Tokyo Electron’s semiconductor production equipment (SPE) sales reached ¥1.86 trillion, driven by a sharp rise in DRAM-related investments, particularly for high-bandwidth memory (HBM), which accounted for 31% of total sales. Non-volatile memory (NAND) remained stable at 7%, while non-memory segments, including logic and foundry, continued to dominate with 62%, reflecting robust demand from both advanced and mature nodes. The overall recovery and expansion of customer investments across segments underpinned this strong performance.

Market Segment Performance

Tokyo Electron’s global market share in CY2024 demonstrates its leadership across multiple core segments of the semiconductor production equipment market. The company holds a commanding 92% share in coater/developer systems, underlining its unparalleled position in photoresist processing for advanced lithography applications. It also leads the wafer prober segment with a 38% share and maintains robust positions in key deposition categories, including 38% in CVD and 37% in oxidation/diffusion systems. In contrast, TEL’s market share in ALD stands at 16%, notably behind ASM International, highlighting an opportunity for expansion in this strategically important technology as the industry moves towards GAA and other 3D device structures. Performance in dry etch (27%), cleaning systems (21%), and wafer bonding (32%) rounds out a broadly competitive portfolio that positions TEL to effectively support ongoing advancements in scaling, heterogeneous integration, and high-performance packaging across logic, memory, and AI-related applications.

To further expand our future profit, we made steady progress in penetrating into new technology domains. Specifically, we released multiple new outstanding products contributing to the semiconductor technology innovation. For example, penetration to untapped segments such as single-wafer plasma CVD and PVD, gas cluster beam system which improves efficiency of leading-edge lithography, and laser-lift-off system to drastically decrease environmental footprint of processing. In fiscal 2025, we conducted share repurchase of about ¥150 billion in total.

- Toshiki Kawai - Representative Director, President and CEO

 

New product 2025 Episode™ single-wafer CVD platform

Episode™ 1 is Tokyo Electron's latest single-wafer CVD platform, launched in 2024 to address the challenges of advanced device scaling in logic, DRAM, and future AI processors. It supports up to eight process modules, enabling complex, uninterrupted multi-step processing. The system integrates the OPTCURE™ module for native oxide removal and ORTAS™ for titanium CVD, allowing immediate Ti deposition to minimise contact resistance in advanced interconnects. Episode™ 1 replaces traditional PVD with CVD to achieve uniform, low-resistivity films in high aspect ratio structures such as deep contact holes. With a 45% smaller footprint than its predecessor and advanced edge computing, data analytics, and environmental tracking capabilities, the system enhances fab productivity, engineer efficiency, and readiness for new materials in next-generation device manufacturing.

The TEL Episode™ 1 system shown in the image seems to feature twin or dual single-wafer process chambers, which is typical in modular CVD tools designed for high throughput. Each visible module (with two load ports per unit) likely contains two process chambers within the same footprint to maximise wafer handling efficiency and enable parallel processing—common in tools aimed at advanced logic and memory manufacturing.

Episode™ 1 offers a reduced footprint. Compared with the Triase+™ series, twice as many smaller modules can be installed in a system. With the same number of modules installed, Episode™ 1 takes up about 45% less fab space than its predecessor

LINK: Episode™ 1 Single-Wafer Deposition System for Semiconductors: Driving the Evolution of AI Semiconductors to Transform Everyday Life | Blog | Tokyo Electron Ltd.

ASM International Strengthens ALD Market Leadership Amid Strong Q1 Results, Growing GAA Adoption, and Strategic Positioning for Advanced Node Demand

ASM International’s Q1 2025 results reaffirm its leadership in Atomic Layer Deposition (ALD), a technology central to enabling advanced semiconductor nodes such as 2nm and beyond. With ALD accounting for more than half of its equipment revenue and strong customer engagement in leading-edge logic and memory, ASM is well-positioned to capitalise on rising demand driven by GAA architectures, high-bandwidth memory, and ongoing technology node transitions.

ASM International’s Q1 2025 results reinforce its leadership in ALD, a foundational technology for enabling advanced semiconductor nodes. ALD represented more than half of ASM’s equipment revenue, with the market expected to grow at a compound annual rate of 10–14% through 2027, and ASM maintaining a leading market share above 55% in the segments they compete in:

Single-Wafer ALD Tools

ASM’s flagship ALD platforms are single-wafer systems, which provide high precision, conformality, and process flexibility. These are used primarily in leading-edge logic and memory production.

• Key Platforms:

  • XP8 and XP8 QCM: High-productivity platforms supporting multiple process chambers; widely used for high-volume manufacturing.

  • Previum and Previum Pro: Previum systems incorporate an integrated epitaxial (EPI) pre-clean step that effectively removes 15–20 monolayers of native oxide from the substrate surface. This step is crucial for ensuring high-quality EPI film growth.

  • Pulsar®: Specialised for high-k dielectrics, such as hafnium oxide (HfO₂) typically used in gate stacks.

  • Eagle® XP8: Designed for advanced metal ALD (e.g. TiN, W), often used in logic and memory applications including barrier and liner layers.

ASM International’s strategic alignment with the prevailing trends in the wafer fab equipment (WFE) market and its concentrated customer base. Logic and foundry applications are set to remain the dominant segment of WFE spending through 2026, reinforcing ASM’s focus on enabling advanced nodes such as FinFET and GAA, where Epitaxy (Epi) and atomic layer deposition (ALD) are critical. The company’s FY24 revenue profile shows that its top five customers accounted for 51% of sales, while the top ten represented 70%, indicating strong relationships with leading-edge semiconductor manufacturers. These likely include TSMC, Samsung, Intel, SK hynix, and Micron—ASM’s probable top customers given their leading-edge node adoption and high ALD utilisation. Others may include GlobalFoundries, UMC, SMIC, and select IDMs. 

The industry’s shift to gate-all-around (GAA) transistor architectures at 2 nm and beyond is driving increased demand for single-wafer ALD and silicon epitaxy (Si Epi) processes, which are essential for integrating high-k dielectrics, advanced metals, and high aspect ratio features in both logic and memory devices. ASM’s deep engagement with leading-edge customers—particularly in logic/foundry and high-bandwidth memory (HBM) DRAM—has already translated into strong revenue contributions. Additionally, early tool shipments for the 1.4nm node reflect continued confidence from top-tier clients and extend ASM’s growth visibility as chipmakers prepare for more complex architectures requiring precise material deposition.

ASMI presented a robust growth trajectory of the single-wafer Atomic Layer Deposition (ALD) market, projected to reach between US$4.2 billion and US$5.0 billion by 2027, with a compound annual growth rate (CAGR) of 10–14% from 2022.

Summary from ASM International Q1 2025 Earnings Call:

1. ALD Market Outlook:
ALD continues to be a key growth driver for ASM, with equipment sales led by ALD and expectations of a strong increase in GAA (gate-all-around) related demand throughout 2025. ALD intensity is rising as leading-edge nodes (2 nm and 1.4 nm) require more deposition steps for complex 3D structures, high-k dielectrics, and metal gate stacks. ASM confirmed ongoing R&D engagement for 1.4nm and highlighted that ALD demand will further accelerate in next-gen nodes, backside power delivery, and in advanced DRAM (e.g. HBM), which increasingly adopt logic-like ALD layers. ASM remains confident in long-term ALD market growth, forecasting double-digit increases in application layers per node.

2. Trade, Tariffs, and Geopolitical Risk:
ASM addressed potential impacts from new US tariff announcements, noting no immediate effect on equipment, but acknowledging possible indirect macroeconomic consequences. The company has prepared multiple mitigation scenarios, including flexible global manufacturing—already expanding in Korea and establishing capability in Arizona (set to scale in 2H 2026). ASM emphasised its ability to localise production quickly if needed. While there’s been no pull-forward of tool orders due to tariff concerns, the company is monitoring the situation closely and maintaining optionality in its supply chain to navigate shifting trade conditions.

ASM International NV (ASMIY) Q1 2025 Earnings Call Transcript | Seeking Alpha

"ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength"

ASM International (ASMIY) delivered a strong Q1 FY25, exceeding expectations in revenue, margins, and orders, driven by robust AI infrastructure demand, early ramp-up of 2nm nodes, and resilient performance in China. Despite macroeconomic risks and export controls, ASM saw solid contributions from mature logic foundries and high-bandwidth memory (HBM), which relies on advanced techniques like ALD and Epi. The company’s improved operational efficiency, growing AI demand, and clearer long-term growth visibility led the author to upgrade the stock to a “strong buy,” supported by a belief that ASM can reach the high end of its FY27 revenue target with continued margin expansion.

LINK: ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength (OTCMKTS:ASMIY) | Seeking Alpha

Neumonda and Ferroelectric Memory Company Collaborate in the Commercialization of Non-Volatile DRAM

Neumonda and Ferroelectric Memory (FMC) are working together to design, provide test solutions, and market FMC’s nonvolatile DRAM+. This collaboration aims nothing less than to bring semiconductor DRAM memory design and manufacturing back to Germany.

Marco Mezger, COO of Neumonda, Thomas Rueckes, CEO of FMC, and Peter Poechmueller, CEO of Neumonda (from left to right), celebrate the collaboration of the two German memory powerhouses

Two German memory innovators join forces to bring semiconductor memory back to Germany

Bad Homburg / Dresden, April 3, 2024 – Neumonda and Ferroelectric Memory (FMC) are working together in the design, provision of test solutions, and marketing of FMC’s nonvolatile DRAM+. This collaboration aims nothing less than to bring semiconductor DRAM memory design and manufacturing back to Germany.

FMC commercializes a disruptive technology that combines non-volatile properties of ferroelectric hafnium oxide (HfO2) with RAM to create a non-volatile DRAM memory for AI, medical, industrial, automotive, and consumer applications. As part of the agreement, Neumonda which holds several patents in the design and testing of DRAM memory, will support FMC with memory consulting services and with its Rhinoe, Octopus, and Raptor test platforms for FMC’s nonvolatile DRAM+ products.

“FMC was founded to exploit the disruptive invention of the ferroelectric effect of HfO2 for semiconductor memories. Applied to a DRAM, it turns the DRAM capacitor into a low power, nonvolatile storage device while maintaining the high DRAM performance to produce a disruptive nonvolatile DRAM memory ideal for AI compute,” explained Thomas Rueckes, CEO of FMC. “Since our technology is unique in the market, cost-effective testing of our memory products is of great importance for our product offerings. With Neumonda and its radically new approach to testing, we have found a partner that can help us speed up the development of our products. We also are excited to work with Neumonda as we share the common vision to bring Memory back to Europe”

Neumonda combines unmatched expertise in memory and, with its Neumonda Technology division, revolutionizes memory testing. Its testers are lightweight, low-cost, and energy-efficient and enable Neumonda to conduct manufacturer-independent tests at a level and detail that has not been possible before—all this at a fraction of the costs of traditional testers.

“As our test platforms are maturing, FMC’s products are an ideal test ground to prove the capabilities of our Rhinoe, Octopus, and Raptor testers, as well as the high-quality yield they enable,” explained Peter Poechmueller, CEO of Neumonda. “One of my personal goals behind founding Neumonda was to bring semiconductor memory back to Europe. With this collaboration, we take a big step closer to establishing a new German memory manufacturer.

About FMC

FMC was founded in 2016 as a spin-off from NaMLab GmbH, a TU Dresden company, to commercialize ferroelectric hafnium oxide technology originally invented by Qimonda, the former German DRAM manufacturer. FMC is a full stack fabless semiconductor company with operations in Dresden (Germany), Milan (Italy) and North America. FMC product offerings include high density, low power, nonvolatile DRAM and Cache chiplets for disruptive performance and power efficiency improvements in edge and cloud AI systems. Since its foundation, FMC has been working closely with Saxonian, Federal German and European funding providers and is very thankful for this continuous support. For more information visit: www.ferrolectric-memory.com

About Neumonda

NEUMONDA combines extensive memory experience with the “DNA” of former memory manufacturer Qimonda, with the aim to offer the most extensive portfolio of specialized memory solutions and competence in the market. It governs MEMPHIS Electronic, a distributor of memory ICs and modules of different suppliers; Intelligent Memory, the manufacturer of DRAM and NAND-based memory solutions; and NEUMONDA Technology which designs and holds IP for application test systems for memory applications. Combining these different areas of expertise, NEUMONDA is able to offer unique global memory competency that can help companies in any industry to meet their current and future memory requirements. www.neumonda.com

3rd and Last Call for Papers, and List of Speakers / Symposium on ALD & ALE Applications #21, at 248th ECS Fall Meeting / Oct. 12-16, 2025 in Chicago, USA

This fall, the 248th ECS Meeting will be held on Oct. 12-16, 2025 in Chicago (IL, USA), and is expected to gather some 3,000 participants and 40 exhibitors from both academia and industry.

The conference has a strong focus on emerging technology and applications in both solid-state science & technology and electrochemistry.

• General information and the Meeting Program can be found here: Important Information and Call for Papers.
• For more information about our annual symposium G01 and the conference website: Meeting Information. 

The organizers of symposium G01 on “Atomic Layer Deposition & Etching Applications, 21” encourage you to submit your abstract(s) on topics, comprising but not limited to: 

1. Semiconductor CMOS applications: development and integration of ALD high-k oxides and metal electrodes with conventional and high-mobility channel materials; 

2. Volatile and non-volatile memory applications: extendibility, Flash, MIM, MIS, RF capacitors, etc.; 3. Interconnects and contacts: integration of ALD films with Cu and low-k materials; 

4. Fundamentals of ALD processing: reaction mechanisms, in-situ measurement, modeling, theory; 

5. New precursors, delivery systems & sustainability issues; 

6. Optical, photonic and quantum applications; applications aiming at Machine Learning, Artificial Intelligence 

7. Coating of nanoporous materials by ALD; 

8. Molecular Layer Deposition (MLD) and hybrid ALD/MLD; 

9. ALD for energy conversion applications such as fuel cells, photovoltaics, etc.; 

10. ALD for energy storage applications; 

11. Productivity enhancement, scale-up and commercialization of ALD equipment and processes for rigid and flexible substrates, including roll-to-roll and spatial processing; 

12. Area-selective ALD; 

13. Atomic Layer Etching (‘reverse ALD’) and related topics aiming at self-limited etching, such as atomic layer cleaning, etc. 

FYI: Last year at the PRiME 2024 Meeting in Honolulu, our symposium G01 on ALD & ALE Applications 20 attracted some 80 participants, attending a full 3-days schedule with 50 presentations (42 oral, of which 16 invited, plus 8 poster presentations). We expect to be at least as successful this Fall in Chicago. 

Abstract submission 

Meeting abstracts should be submitted not later than the deadline of March 28, 2025 via the ECS website: Submission Instructions

Submission Instructions Invited speakers A list of invited speakers follows below: 

Visa and travel For extensive information, see last year’s version: VISA AND TRAVEL INFORMATION

In addition, ECS’ Francesca Di Palo (francesca.dipalo@electrochem.org) can provide you with an official participation letter issued by the Electrochemical Society. For (limited) general travel grant questions, please contact travelgrant@electrochem.org. 

As in the past years, we expect also our symposium to be able provide some partial travel allowance to selected speakers. We are looking forward to meeting you all at our symposium G01 on ALD & ALE Applications 21, in Chicago | Oct. 12-16, 2025!

Bridging the Lab-to-Fab Gap: Overcoming ALD Scaling Challenges with Chipmetrics, Finland

Scaling Atomic Layer Deposition (ALD) from laboratory research to high-volume semiconductor manufacturing presents numerous challenges, particularly as the industry moves towards more complex 3D structures like 3D NAND, Through-Silicon Vias (TSVs), and nanosheet transistors. One major hurdle is the disparity between lab-scale process development and industrial fabrication, where variations in chamber design and wafer size can lead to unexpected process deviations. Additionally, throughput and cost considerations play a critical role, as slow deposition rates can hinder industrial adoption due to high operating expenses. Defect control is another key concern, as even minuscule particle contamination can significantly impact yield, yet many research facilities lack the advanced defect detection capabilities necessary for high-volume manufacturing. Furthermore, test structure availability is a limiting factor, with sub-100 nm, high-aspect-ratio structures often restricted to leading semiconductor manufacturers, creating barriers for process validation and qualification.

Chipmetrics' PillarHall® metrology chips offer an innovative solution to these challenges by providing dedicated test structures with aspect ratios up to 10,000:1, allowing for rapid and cost-effective ALD validation without the need for complex cross-sectional analysis. These metrology chips facilitate the development of high-aspect-ratio thin film depositions by enabling researchers and manufacturers to evaluate process performance in a scalable manner, ensuring compatibility with industrial requirements. Beyond technical validation, the ability to conduct precise, non-destructive measurements enhances efficiency and reduces development costs, accelerating the transition from lab to fab. As semiconductor manufacturing continues to evolve, tools like PillarHall play a crucial role in streamlining the process transfer while maintaining the precision and reliability demanded by the industry.

PillarHall LHAR4 Test Chip in animated presentation. How to use the PillarHall chip in characterizing 3D thin film process conformality. Lateral High Aspect Ratio, Ultra High Aspect Ratio, Thin Film, Conformal, Deposition, Atomic Layer Processing, Atomic Layer Deposition, Chemical Vapor Deposition, ALD, CVD, HAR, 3D, metrology, Atomic Layer Etching, ALE

In this insightful presentation given by the inventor of PillarHall test chips, Professor Riikka Puurunen from the School of Chemical Engineering, Department of Chemical and Metallurgical Engineering at Aalto University, talks about "Recent Progress in Analysis of the Conformality of Film by Atomic Layer Deposition.

Source:

Challenges of Transferring Deposition Processes to Industry Partners in the Semiconductor Industry - Chipmetrics

ALD FOR INDUSTRY 2025: Advancing Atomic Layer Deposition from Science to Industrial Applications in Dresden

The 8th International Conference "ALD for Industry" took place in Dresden from March 11 to 12, 2025, bringing together experts to discuss advancements in Atomic Layer Deposition (ALD) technology. In addition to the previously mentioned presentations, the conference featured several notable talks:

Prof. Fred Roozeboom

AlixLabs and Aether Semiconductor

Silicon Austria Labs

ASM International

The handshake

Prof. Riikka Puurunen

"Fundamentals of Atomic Layer Deposition: A Tutorial" by Prof. Riikka Puurunen

Prof. Riikka Puurunen from Aalto University, Finland, delivered a comprehensive tutorial on the fundamentals of ALD. She covered the history of ALD, its underlying surface chemistry, typical reaction mechanisms, and growth modes. Prof. Puurunen also discussed the role of diffusion in 3D structures and provided insights into surface reaction kinetics.

​In her tutorial titled "Fundamentals of Atomic Layer Deposition," Prof. Riikka Puurunen of Aalto University provided a comprehensive overview of ALD, a nanotechnology technique for precise surface modifications and thin coatings. She traced ALD's dual origins: Atomic Layer Epitaxy (ALE) developed by Tuomo Suntola in 1974, and Molecular Layering (ML) introduced by Valentin Aleskovskii and Stanislav Koltsov in the 1960s. The tutorial delved into the core principles of ALD, emphasizing its reliance on repeated, self-terminating reactions between gaseous reactants and surfaces. Prof. Puurunen categorized typical reaction mechanisms, discussed factors influencing saturation and growth modes, and highlighted "growth per cycle" (GPC) as a fundamental characteristic of ALD processes. She also explored the role of diffusion in complex 3D structures, noting how diffusion-limited growth can provide insights into surface reaction kinetics. The presentation available at Fundamentals of ALD: tutorial, at ALD for Industry, Dresden, by Puurunen 2025-03-11 | PPT

"Spatial ALD of IrO₂ and Pt Films for Green H₂ Production by PEM Electrolysis" by Dr. Paul Poodt

Dr. Paul Poodt, Chief Technology Officer at SparkNano, presented on the application of spatial ALD in fabricating iridium dioxide (IrO₂) and platinum (Pt) films. These materials are crucial for enhancing the efficiency of proton exchange membrane (PEM) electrolyzers used in green hydrogen production. Dr. Poodt highlighted how spatial ALD enables precise control over film thickness and composition, leading to improved performance and durability of electrolyzer components.

SparkNano’s CTO, Paul Poodt, presented on Spatial ALD of IrO₂ and Pt Films for Green H₂ Production by PEM Electrolysis on March 12 at 10:20 AM during the Emerging Applications session. Attendees had the opportunity to connect with him to discuss SparkNano’s spatial ALD technology.

"Advancements in ALD for Next-Generation Semiconductor Devices" by Dr. Christoph Hossbach

Dr. Christoph Hossbach from Applied Materials / Picosun Europe discussed recent progress in applying ALD techniques to next-generation semiconductor devices. His presentation covered the integration of ALD processes in manufacturing advanced transistors and memory devices, emphasizing the role of ALD in achieving atomic-scale precision and conformality required for modern microelectronics. 

"ALD Applications in Quantum Technology" by Dr. Martin Knaut

Dr. Martin Knaut of TU Dresden explored the utilization of ALD in developing components for quantum technologies. He highlighted how ALD's ability to deposit uniform and defect-free thin films is essential for fabricating qubits and other quantum devices, potentially leading to more stable and scalable quantum computing systems. 

"Emerging Applications of ALD in the Medical Field" by Dr. Mira Baraket

Dr. Mira Baraket from Atlant 3D presented on the potential of ALD in medical applications, including the development of biocompatible coatings for implants and drug delivery systems. She discussed how ALD can enhance the performance and safety of medical devices by providing precise control over surface properties.

Sources:

ALD for Industry 2025 – EFDS

JSR Expands Global Semiconductor Material Capabilities with New Photoresist Facilities, Advanced MOR Variants, and Strategic Acquisition of CVD/ALD Precursor Firm

JSR Corporation is expanding its global development and production of advanced photoresists by establishing a new R&D center in Japan and constructing a semiconductor photoresist plant in Korea. Since acquiring Inpria Corporation in 2021, JSR has been commercializing Metal Oxide Resist (MOR) for EUV lithography. The new R&D center in Japan’s Kanto region will enhance collaboration with global customers and partners, while the Korean plant, expected to begin operations in 2026, will handle the final production process for MOR to support local adoption. JSR aims to drive innovation in photoresists and help customers establish commercial production processes worldwide.

JSR's MOR, developed through its 2021 acquisition of Inpria Corporation, is a next-generation photoresist designed for EUV lithography. MOR is based on metal oxide nanoparticles, offering superior etch resistance and improved pattern resolution compared to traditional chemically amplified resists (CARs). This allows for finer feature definition and reduced line-edge roughness, critical for advanced semiconductor manufacturing below 10 nm. JSR has been scaling MOR for commercial adoption, with major semiconductor manufacturers evaluating its use in high-volume production. The company is expanding its R&D and manufacturing capacity, including a new R&D center in Japan and a production facility in Korea, to support global adoption of MOR.

JSR have investigated different flavors of MOR for EUV lithography, primarily focusing on variations in metal cores and process optimizations. Initially, zirconium (Zr) and hafnium (Hf) based MORs were explored, but their relatively low EUV absorption led researchers to investigate alternative metal cores such as titanium (Ti), zinc (Zn), indium (In), and tin (Sn). These new metal cores exhibited improved lithographic performance, achieving higher EUV absorption, smaller particle size, and better scum reduction. Additionally, process optimizations such as using higher dissolution rate photoacid generators (PAGs), new organic solvent developers, and lower soft bake temperatures were tested to improve scum removal and resolution. The new metal core variants demonstrated resolutions down to 13 nm with reduced defects, suggesting their potential for advanced semiconductor manufacturing.

In August 2024, JSR Corporation completed the acquisition of Yamanaka Hutech Corporation (YHC), a Kyoto-based manufacturer specializing in high-purity chemicals for semiconductor manufacturing. This strategic move allows JSR to expand its product portfolio to include Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) precursors, which are essential for forming advanced and complex semiconductor device structures. YHC, established in 1960, has over 60 years of experience in advanced molecular design, synthesis technology, and quality control systems, supplying high-quality CVD/ALD precursors to leading-edge semiconductor device manufacturers. The acquisition aligns with JSR's strategy to strengthen its position as a global supplier of semiconductor materials, enhancing its capabilities in both miniaturization and device structure innovation.

Sources:

JSR Expands Global Development and Production Functions for Leading-Edge Photoresists | 2024 | News | JSR Corporation

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