High-Precision ALD and Etching Techniques Enable Sub-1nm EOT in Monolayer MoS₂ Transistors

Researchers from Stanford University and Yonsei University have investigated the role of silicon seed layers in enabling high-quality atomic layer deposition (ALD) of HfO₂ on monolayer MoS₂, achieving sub-nanometer equivalent oxide thickness (EOT) and precise threshold voltage control.

Researchers developed a method to achieve sub-1 nm equivalent oxide thickness (EOT) in monolayer MoS2 transistors using atomic layer deposition (ALD) of HfO2 with a silicon seed layer, enabling improved threshold voltage control and low hysteresis. They investigated six seed layer candidates (Si, Ge, Hf, La, Gd, Al2O3) and found that only Si and Ge preserved the integrity of MoS2. The Si seed provided the best interface, allowing for the fabrication of normally-off transistors with a well-behaved threshold voltage. The resulting devices demonstrated a low EOT of approximately 0.9 nm, minimal leakage current (<0.6 μA/cm²), and a subthreshold swing of ~80 mV/dec at room temperature. This method offers a simple and accessible approach to depositing high-quality top-gate dielectrics in common nanofabrication facilities.

The manufacturing process of monolayer MoS2 transistors in the study involves several key steps, including atomic layer deposition (ALD) and etching processes:

1. MoS2 Growth and Device Preparation: Monolayer MoS2 is synthesized using chemical vapor deposition (CVD) at 750°C on a SiO2 (90 nm) / p++ Si substrate. Alignment markers are deposited, and large contact pads (SiO2/Ti/Pd) are patterned and lifted off.

2. Channel Patterning and Etching: The transistor channels are defined via electron-beam lithography and etched using xenon difluoride (XeF2) chemistry. Gold source and drain contacts are then deposited using electron-beam evaporation.

3. Seed Layer Deposition: For the top-gate structure, ultrathin Si and Ge seed layers (~1 nm) are deposited using e-beam evaporation under high vacuum (~10⁻⁷ Torr). These seed layers are exposed to air before undergoing characterization via Raman and XPS measurements.

4. Atomic Layer Deposition (ALD) of HfO₂: The Si or Ge-seeded samples are placed in the ALD chamber at 200°C for 30 minutes before initiating the deposition process. HfO₂ is grown using tetrakis(dimethylamido)hafnium (TDMAH) and H₂O as precursors at 200°C. The ultrathin Si seed oxidizes into SiOx, forming a high-quality interface for dielectric growth.

5. Top-Gate Metallization and Etching: The Pd top gate is patterned and deposited using e-beam evaporation. To expose the contact pads for probing, the top-gate oxide is selectively removed using inductively coupled plasma (ICP) etching with CF₄.

6. Annealing: The top-gated devices undergo vacuum annealing at 150°C, while back-gated devices without top gates are annealed at 250°C for two hours to remove moisture and stabilize electrical characteristics.

This process enables the formation of high-quality MoS₂ transistors with sub-1 nm equivalent oxide thickness (EOT), low leakage, and precise threshold voltage control.

Sources:

Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS2 Transistors | Nano Letters

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