Friday, January 31, 2025
Forge Nano Expands ALD Capabilities with New TEPHRA™ Cluster Tool and State-of-the-Art Cleanroom
Thursday, January 30, 2025
Lam Research’s Dry Resist: A Breakthrough in EUV Lithography for Next-Generation Logic and Memory Manufacturing
Lam Research’s dry resist technology represents a major shift in EUV lithography and semiconductor patterning, addressing critical challenges such as stochastic defectivity, resolution limitations, and cost-efficiency. With recent qualifications for advanced DRAM and 2nm logic manufacturing, along with a growing ecosystem for high-volume production, dry resist is positioned to disrupt traditional chemically amplified resists (CARs) and enable future High-NA EUV adoption.
One of the most significant recent developments is Lam’s qualification of dry resist for 28nm pitch BEOL logic at 2nm and below in collaboration with imec. This qualification confirms that dry resist can eliminate multi-patterning steps, reducing complexity and improving EUV throughput. The process is designed to work with both low-NA and high-NA EUV scanners, ensuring its relevance for sub-2nm logic scaling. This represents a key milestone in extending direct EUV printing to future logic nodes, an approach that could significantly lower lithography costs while improving pattern fidelity.
In addition, a leading DRAM manufacturer has selected Lam’s Aether dry resist technology as its production tool of record for advanced DRAM nodes. This decision highlights dry resist’s low-defect, high-fidelity patterning capabilities, which are essential for scaling memory architectures. The technology enables lower exposure doses while reducing stochastic defects, which are a major concern in EUV-based DRAM production. Given that Samsung, SK Hynix, and Micron are all increasing their reliance on EUV for next-generation DRAM, Lam’s dry resist is well-positioned for widespread adoption in the memory sector.
To ensure a stable supply chain for dry resist materials, Lam Research has partnered with Entegris and Gelest, a Mitsubishi Chemical Group company. This collaboration ensures reliable dual-source precursor production, providing chipmakers with long-term process stability. The partnership also focuses on the development of next-generation high-NA EUV precursors, further strengthening dry resist’s role in future sub-2nm manufacturing.
SEM images of 28 nm pitch line/space patterns imaged with 0.33NA EUV in dry resist from Entegris precursor.
A critical enabler of dry resist technology is its atomic layer deposition (ALD) process, which replaces traditional spin-coating used in CARs. ALD-based vapor-phase deposition offers higher uniformity, eliminating polymer chain variations found in conventional resists. It also allows precise thickness control, which is essential for optimizing EUV photon absorption and etch selectivity. Unlike CARs, which rely on a complex mixture of polymers, dry resist materials are based on single-component metal-organic precursors such as organo-tin oxides. These materials provide higher EUV photon absorption, improving sensitivity and pattern resolution.
Another key advantage of dry resist is its anisotropic dry development process, which replaces wet solvent-based development. Traditional CAR-based EUV resists require organic solvents or aqueous bases, leading to stochastic defects, material loss, and waste. Dry resist, by contrast, is developed entirely in the gas phase, selectively removing unexposed regions and forming a negative-tone image. This eliminates line collapse and delamination issues, improving yield stability. Additionally, the elimination of wet chemistries significantly reduces chemical waste, making dry resist a more sustainable solution with five to ten times lower material consumption compared to traditional resists.
Lam’s dry resist technology is poised to disrupt traditional CAR-based EUV lithography, particularly as the industry moves toward High-NA EUV adoption. By reducing multi-patterning dependency, the technology enhances cost-effective EUV scaling, making it an attractive solution for both logic and memory manufacturers. This positions Lam as a key leader in next-generation EUV resist solutions, challenging conventional resist suppliers like JSR, TOK, and Inpria.
From a sustainability perspective, dry resist significantly lowers EUV exposure dose requirements, leading to higher scanner throughput and lower energy consumption. Its reduced defectivity translates to higher yield per wafer, further enhancing cost-efficiency. The collaboration with Entegris and Gelest ensures supply-chain stability, making dry resist a viable and scalable technology for sub-2nm nodes.
Sources:
Saturday, January 18, 2025
Revolutionizing Silicon Photonics: First Electrically Pumped Group IV Laser Achieved for Seamless Integration on Silicon Chips
Researchers have achieved a groundbreaking milestone in silicon photonics by developing the first electrically pumped Group IV laser, made from silicon-germanium-tin layers directly grown on silicon wafers. This innovation paves the way for cost-effective, energy-efficient photonic integrated circuits in next-gen silicon chips.
This laser not only operates with a low current of 5 milliamperes at 2 volts but also features a sophisticated multi-quantum well structure and ring geometry to minimize power consumption and heat generation. Though the device currently functions at cryogenic temperatures, its development path mirrors earlier advancements in germanium-tin lasers that achieved room-temperature operation within a few years. The laser’s manufacturability is further underscored by its growth on standard silicon wafers, aligning with industry-standard processes. This achievement is poised to catalyze the adoption of low-cost photonic integrated circuits (PICs) in microchips, meeting the growing demand for energy-efficient hardware in AI and IoT applications while paving the way for advances in optical data transmission and next-generation silicon photonics.
Sources:
Silicon Photonics Breakthrough: The “Last Missing Piece” Now a Reality
Friday, January 17, 2025
3D Vertical Ferroelectric Capacitors for Memory Scaling
3D vertical ferroelectric capacitors are revolutionizing memory technology, offering higher density and performance by leveraging vertical structures to overcome planar scaling limits. Using aluminum-doped hafnium oxide (Al:HfO₂), these capacitors achieve stable remnant charge, low voltage operation, and enhanced scalability, addressing advanced applications in AI and edge computing. Recent innovations, such as the TiN/Al:HfO₂/TiN configuration introduced by Dongguk University, South Korea, demonstrate improvements in endurance and integration. This progress builds on foundational work by Qimonda and Fraunhofer IPMS-CNT in Dresden Germany, including Tim Böscke's pioneering discovery of ferroelectricity in hafnium oxide and Johannes Müller's ALD advancements using ALD process developments FHR and ASM tools. These developments cement Al:HfO₂ as a DRAM and CMOS-compatible solution for next-generation non-volatile memory technologies.
A recent study, 3D Vertical Ferroelectric Capacitors with Excellent Scalability (by Eunjin Lim et al Dongguk University, South Korea)), introduces a 3D vertical ferroelectric capacitor with a TiN/Al:HfO₂/TiN configuration. It employs a unique architecture with multiple small holes sharing a common pillar electrode, enhancing ferroelectric properties and scalability. Analyses using advanced microscopy confirm its structural integrity, while the device demonstrates high endurance, minimal variability, and excellent retention. This architecture also supports integration into one-transistor n-capacitor ferroelectric memory with vertical transistors.
Importantly, Earlier work by Fraunhofer IPMS-CNT, including the 2012 study Incipient Ferroelectricity in Al-Doped HfO₂ Thin Films, first demonstrated ferroelectric properties in HfO₂ thin films doped with aluminum. This research identified an antiferroelectric-to-ferroelectric phase transition, influenced by Al concentration and annealing conditions, and attributed ferroelectricity to a non-centrosymmetric orthorhombic phase (Pbc2₁). This foundational work highlighted the potential of Al:HfO₂ for applications in memory and sensing technologies.
The later paper High Endurance Strategies for Hafnium Oxide-Based Ferroelectric Field Effect Transistors further emphasized Al:HfO₂’s scalability and compatibility with CMOS technology. It explored strategies to improve endurance and reduce interfacial stress, including modifying interfacial materials and exploring MFS structures. These strategies balance performance, reliability, and scalability, supporting the broader adoption of ferroelectric memory.
In Johannes Müller's PhD thesis (2014, Fraunhofer IPMS-CNT), the Atomic Layer Deposition (ALD) processes for hafnium oxide (HfO₂) and aluminum-doped hafnium oxide (Al:HfO₂) utilized advanced deposition equipment to achieve precise doping and phase control. The processes were performed using a 300 mm FHR ALD 300 and an ASM PULSAR 3000®, both of which are designed for high-uniformity deposition on large substrates, such as 300 mm wafers. These tools facilitated the use of tetrakis(ethylmethylamino)hafnium (TEMAHf) and trimethylaluminum (TMA) as precursors for hafnium and aluminum, respectively, along with oxidants like water or ozone. By tailoring precursor ratios, deposition temperatures, and annealing conditions, the processes ensured the stabilization of the orthorhombic Pbc2₁ phase, critical for the ferroelectric properties of Al:HfO₂ films. These advancements highlight the scalability and compatibility of ALD-fabricated Al:HfO₂ films with CMOS technology.
The patent US 2009/0057737 A1, authored by Tim Böscke et al., describes a method for fabricating integrated circuits with a dielectric layer that exhibits enhanced properties, such as high dielectric constants and ferroelectricity. The process involves forming a preliminary dielectric layer, such as hafnium oxide or doped hafnium oxide (e.g., aluminum- or silicon-doped), using techniques like Atomic Layer Deposition (ALD). The dielectric layer is initially amorphous and undergoes a phase transition to a crystalline state upon heating above its crystallization temperature. The method includes precise doping of the dielectric layer to stabilize desirable phases, such as orthorhombic or tetragonal, which are essential for achieving ferroelectricity. A covering layer, often a conductive electrode material, is deposited before annealing to assist in crystallization and enhance material properties. The innovations outlined aim to improve memory applications, such as capacitors and transistors, by offering higher storage densities, lower leakage currents, and compatibility with advanced CMOS processes. This patent is foundational in the development of ferroelectric hafnium oxide-based technologies.
Sources:
- 3D Vertical Ferroelectric Capacitors with Excellent Scalability: 3D Vertical Ferroelectric Capacitors with Excellent Scalability | Nano Letters
- Mueller, S., et al., Incipient Ferroelectricity in Al‐Doped HfO₂ Thin Films, Advanced Functional Materials, 2012. Wiley Online Library
- High Endurance Strategies for Hafnium Oxide-Based Ferroelectric Field Effect Transistor, Fraunhofer IPMS, 2016. (N-432037.pdf): N-432037.pdf
Ferroelektrizität in Hafniumdioxid und deren Anwendung in nicht-flüchtigen Halbleiterspeichern Ferroelektrizität in Hafniumdioxid und deren Anwendung in nicht-flüchtigen Halbleiterspeichern - US 2009/0057737A1 (prev. QIMONDA AG, now NAMLAB GGMBH) https://patentimages.storage.googleapis.com/56/02/b2/d476f4848ffe82/US20090057737A1.pdf
Saturday, January 11, 2025
Integrating Metal-Oxide EUV Resists with Directed Self-Assembly for High-Resolution Chemical Patterning
Extreme ultraviolet (EUV) lithography struggles with resist materials that can deliver both high resolution and acceptable throughput, often resulting in rough patterns and printing defects that degrade semiconductor performance. To overcome this, researchers are exploring directed self-assembly (DSA) of block copolymers (BCPs), which can naturally rectify pattern defects when aligned to EUV-defined chemical guides. However, metal-oxide EUV resists (MORs), which provide high resolution, face challenges in converting their patterns into effective chemical guides for DSA integration.
This study presents a novel method using hydrogen silsesquioxane (HSQ), a negative tone resist, to create chemical patterns for integrating MORs with DSA. The process involves forming a sacrificial chromium pattern from HSQ, which is later replaced with a polyethylene oxide brush layer and a nonpolar polystyrene brush. These steps allow the successful assembly of polystyrene-block-poly(methyl methacrylate) BCPs, achieving 24 nm full-pitch resolution. This approach shows potential for producing sub-10 nm patterns by combining high-χ BCPs with MOR-based EUV lithography, advancing next-generation semiconductor fabrication.
DSA of BCPs is a promising nanofabrication technique that utilizes the phase separation properties of BCPs to create highly ordered nanoscale patterns with feature sizes below 10 nm. In DSA, BCPs self-organize into distinct microdomains, forming well-defined structures that can be guided using chemoepitaxy or graphoepitaxy. Chemoepitaxy involves chemically patterned surfaces that influence the alignment and orientation of BCP domains, while graphoepitaxy uses topographical features to achieve similar control. High-χ (chi) BCPs are often used to achieve finer pattern resolutions, and material optimizations such as selecting appropriate substrates and brush layers are crucial to improving pattern quality and reducing defects. DSA has been explored for various semiconductor applications, including the creation of dense line-space arrays, hole shrink patterns, and advanced memory devices, offering significant potential to enhance pattern fidelity, reduce defectivity, and lower manufacturing costs.
Sources:
https://journals.spiedigitallibrary.org/conference-proceedings-of-spie/12497/124970K/EUV-lithography-line-space-pattern-rectification-using-block-copolymer-directed/10.1117/12.2657990.full
https://www.mdpi.com/2073-4360/12/10/2432
https://www.spiedigitallibrary.org/conference-proceedings-of-spie/PC12054/PC1205402/Exploring-the-synergy-between-EUV-lithography-and-directed-self-assembly/10.1117/12.2622565.full
https://journals.aps.org/prb/abstract/10.1103/PhysRevB.101.085407
Friday, January 10, 2025
Game-Changing ALD Breakthrough: KJLC Achieves First Scandium Nitride PEALD Process
Wednesday, January 8, 2025
SEMI World Fab Forecast Highlights Strong Fab Investments and New Fabs in 2025
The latest World Fab Forecast by SEMI, published on December 19, 2024, highlights strong growth in global semiconductor manufacturing from 2023 to 2025. Key takeaways from the report include increased investments in fab equipment and capacity expansions across both memory and foundry segments, indicating a resilient and growing industry.
SEMI’s latest World Fab Forecast report reveals that 18 new semiconductor fabs will begin construction in 2025, including three 200mm and fifteen 300mm facilities, primarily in the Americas, Japan, China, and Europe. These projects, set to start operations between 2026 and 2027, reflect the industry's focus on advanced nodes for AI and high-performance computing (HPC). Total semiconductor capacity is expected to grow at a 6.6% annual rate, driven by leading-edge logic technologies, while mainstream and mature nodes continue to support automotive, IoT, and power applications. Foundries remain key drivers of capacity growth, with generative AI demand boosting memory markets, particularly high-bandwidth memory (HBM). [Semiconductor Digest, LINK below]
For 2024, global fab equipment spending is projected to rise by 8% year-over-year to approximately 111 billion dollars, surpassing previous projections. The foundry segment is expected to account for 59 billion dollars of this investment, marking a 2% increase from 2023. The memory segment is set to see the most significant growth, with spending projected to jump by 50% to 34 billion dollars. This surge in memory investments reflects a rebound from the recent downturn and aligns with rising demand for advanced semiconductor technologies.
Looking ahead to 2025, fab equipment spending is expected to grow by an additional 4%, reaching approximately 116 billion dollars. The foundry segment will likely invest around 65 billion dollars, while the memory segment is forecasted to maintain robust spending at 33 billion dollars.
In terms of capacity expansion, the report predicts continued growth in both memory and foundry capacity. Memory capacity is expected to grow by 4% in 2024 and 3% in 2025, while foundry capacity, including pure-play foundries and IDM fabs, is projected to see 12% growth in 2024 and 11% in 2025. This reflects strong demand for advanced logic chips and specialty processes.
On the construction front, investments in new fab construction are expected to dip slightly in 2024, with a 5% decline to 39 billion dollars. However, SEMI anticipates 45 new construction projects for volume fabs, excluding R&D and pilot facilities, between 2025 and 2030. These projects are expected to support long-term demand growth across various segments, including AI chips, automotive semiconductors, and memory.
In 2025, the industry is expected to see the completion of several new fabs that are currently under construction. These new fabs will be crucial for meeting growing demand for advanced semiconductor technologies and are expected to bring significant additional capacity online. Many of these facilities will focus on next-generation nodes, particularly for applications in AI, high-performance computing, and automotive sectors. The report highlights that regions such as Taiwan, South Korea, and the US will see major investments in these new fabs, further strengthening their positions as key players in the global semiconductor supply chain.
Sources:
ALD for Industry | International Conference & Exhibition - March 11 - 12, 2025 | Dresden, Germany
- Industrial batch ALD for optical applications | Shuo Li, Afly Solution Oy, Finland
- Direct Processing by µDALP™. Precision Coatings for Next Gen Devices | Maksym Plakhotnyuk, ATLANT 3D, Denmark
- Nanoscale solid-state lithium-ion electrolytes enabled by atomic layer deposition | Messaoud Bedjaoui, CEA Leti, France
- Fabrication of Surface Relief Gratings using ALD-based Technologies to Overcome the Challenges of Reactive Ion Etching of TiO2 | Mathias Franz, Fraunhofer ENAS, Germany
- Monitoring and optimisation of ALD processes with Remote Plasma Optical Emission Spectroscopy | Erik Cox, Gencoa Ltd, UK
- Optimizing Plasma-Assisted Atomic Layer Deposition using Impedans RFEAs | Angus McCarter, Impedans Ltd., UK
- Improving atomic layer deposition process of silicon oxide (SiO2) and aluminum oxide (Al2O3) | Long Lei, Fraunhofer IMPS, Germany
- Introducing a Surface Acoustic Wave-Based Miniaturized Aerosol Source for Controlled Liquid Precursor Delivery in ALD Processes | Mehrzad Roudini, Leibniz IFW, Germany
- Challenges and Solutions in ALD of Thermal Budget Sensitive Ferroelectric Materials | Bart Vermeulen, Ferroelectric Memory Co GmbH, Germany
- ALD for Nanoparticles: From Fundamentals to Industrial Applications | Rong Chen, University of Science and Technology HUST, China
- Recent developments and emerging applications in atmospheric-pressure ALD on high-porosity membranes | Fred Roozeboom, University of Twente, Netherlands
- Past, present and future of ALD from an industrial perspective | Jan Willem Maes, ASM, Belgium
- Advanced in-situ QCM process monitoring | Martin Knaut, ALS Metrology UG, Germany
- Cryogenic Atomic Layer Etching (Cryo-ALE) of low-k dielectrics like SiO2, and GaN etching. | Rémi Dussart, Université d´Orleans, France
- ALD for Memory Applications: a matter of details | Laura Nyns, IMEC, Belgium
- Spatial ALD of IrO2 and Pt films for green H2 production by PEM electrolysis | Paul Poodt, SparkNano B. V., The Netherlands
- APECS Pilot Line – Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems | Wenke Weinreich, Fraunhofer IPMS, Germany
- Sean Barry, Carleton University, Canada
- Gloria Gottardi, Fondazione Bruno Kessler, Italy
- Christoph Hossbach, Applied Materials / Picosun Europe, Germany
- Martin Knaut, TU Dresden, Germany
- Laura Nyns, IMEC, Belgium
- Fred Roozeboom, University Twente, Netherlands
- Jonas Sundqvist, Alixlabs, Sweden
Surface Passivation: A Cornerstone for Advancing Semiconductor Technologies
Saturday, January 4, 2025
2025 Book - Emerging Atomic Layer Deposition for Hydrogen Energy
Scalable ALD Process for High-Performance MoS₂ Films on Flexible Substrates Unlocks Advanced Electronics Applications
The process begins with 6-inch p-type silicon wafers, onto which a 285 nm layer of thermal SiO₂ is grown at 1000°C using a tube furnace. To enhance the chemical termination of the surface oxide, the wafers are treated in a UV/O₃ reactor for 10 minutes. The subsequent step involves the deposition of MoO₃ via a thermal atomic layer deposition (ALD) process using a Cambridge Nanotech Savannah S200 system. The ALD process utilizes bis(tert-butylimido)bis(dimethylamido) molybdenum as the molybdenum precursor and ozone as the oxidant. By conducting 15 ALD cycles at 250°C, a uniform MoO₃ film with a thickness of 1.31 ± 0.13 nm is achieved across the entire 6-inch wafer, ensuring excellent consistency. This initial MoO₃ layer provides precise control over the number of MoS₂ layers that are subsequently formed, making it a critical step in the overall process.
Friday, January 3, 2025
Breakthrough in Semiconductor Technology: Amorphous ALD Deposited Nanometal Film Enhances Miniaturization Efficiency
A joint research team from Ajou University in Korea and Stanford University in the US has developed a groundbreaking semiconductor material using an amorphous semi-metallic thin film. Unlike traditional metals that suffer from increased resistivity as they get thinner, this newly discovered material exhibits decreased resistivity when its thickness is reduced. This characteristic addresses a critical challenge in semiconductor miniaturization, where the narrowing of circuit lines impedes electron movement and hampers performance. The material is created by layering niobium (Nb) crystals on a sapphire lattice and covering it with amorphous niobium phosphide (NbP). The research, published in Science, demonstrates that this new material outperforms existing metals like copper and tantalum when the thickness drops below 10 nm, providing a promising solution for next-generation semiconductors.
This amorphous thin film is notable for its compatibility with current semiconductor fabrication processes and its ability to enhance performance without requiring high-temperature treatments. The team plans to further optimize the process using atomic layer deposition (ALD), a method that ensures precise control over film thickness at the atomic scale, making it ideal for advanced semiconductor miniaturization. Professor Oh Il-gwon, who led the research, emphasized the material's potential to overcome existing limitations in semiconductor technologies and its role in securing future industry leadership. This discovery is expected to revolutionize semiconductor wiring processes, improving both efficiency and production costs in the race for smaller, faster, and more efficient chips.
Surface conduction and reduced electrical resistivity in ultrathin noncrystalline NbP semimetal
Editor’s summary
Abstract
Sources:
Korean and American researchers develop new semiconductor material enhancing performance - CHOSUNBIZ