Friday, January 3, 2025

Driving Next-Generation CMOS Logic: TSMC’s Innovations in Transistor Technologies and AOSFET Advancements

TSMC leads in advanced CMOS logic technologies by continuously innovating dense transistors and interconnect stacks—two core building blocks of high-performance logic chips. The computing capability of any logic technology depends on how densely transistors are interconnected and their switching speed, which is affected by resistive and capacitive circuit loads. TSMC’s R&D efforts focus on developing novel, scalable transistor concepts to maintain cost-effective, energy-efficient solutions for leading-edge logic technology.

Recent advancements in transistor technology include innovations in amorphous oxide semiconductor field-effect transistors (AOSFETs). A 2024 study highlights a new evaluation framework for integrating AOSFETs into back-end-of-line (BEOL) processes. This framework measures performance through five key parameters, including drive current, leakage current, threshold voltage (VTH), subthreshold slope, and stability. The study demonstrates how a tungsten-doped In₂O₃ transistor with a 55 nm channel length and oxide capping layer improves device stability, showcasing progress in low-dimensional materials for next-generation transistors.

Enhancement-mode Atomic Layer Deposited W-doped In2O3 Transistor at 55 nm Channel Length by Oxide Capping Layer with Improved Stability



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