Driving Next-Generation CMOS Logic: TSMC’s Innovations in Transistor Technologies and AOSFET Advancements

TSMC leads in advanced CMOS logic technologies by continuously innovating dense transistors and interconnect stacks—two core building blocks of high-performance logic chips. The computing capability of any logic technology depends on how densely transistors are interconnected and their switching speed, which is affected by resistive and capacitive circuit loads. TSMC’s R&D efforts focus on developing novel, scalable transistor concepts to maintain cost-effective, energy-efficient solutions for leading-edge logic technology.

Recent advancements in transistor technology include innovations in amorphous oxide semiconductor field-effect transistors (AOSFETs). A 2024 study highlights a new evaluation framework for integrating AOSFETs into back-end-of-line (BEOL) processes. This framework measures performance through five key parameters, including drive current, leakage current, threshold voltage (VTH), subthreshold slope, and stability. The study demonstrates how a tungsten-doped In₂O₃ transistor with a 55 nm channel length and oxide capping layer improves device stability, showcasing progress in low-dimensional materials for next-generation transistors.

Enhancement-mode Atomic Layer Deposited W-doped In2O3 Transistor at 55 nm Channel Length by Oxide Capping Layer with Improved Stability

Decoupling from Dependence: The Global Semiconductor Industry Races to Diversify Amid Geopolitical Risks

The semiconductor industry is at a critical juncture, driven by the dual pressures of rising demand for advanced chips in artificial intelligence (AI) and the urgent need to mitigate geopolitical vulnerabilities. With Taiwan’s fabs, particularly TSMC, supplying over 90% of the world’s cutting-edge semiconductors, nations are rapidly investing in new fabs to reduce reliance on both Taiwan and China. While TSMC, Samsung, and Intel lead efforts to expand capacity in regions like the US, Europe, and Japan, these initiatives fall short of replacing Taiwan’s unparalleled output of 2 nm and below chips by 2030. Simultaneously, China’s struggle to compete at leading-edge nodes, compounded by export restrictions on critical tools, further underscores the fragility of the global semiconductor supply chain. These dynamics signal a transformative era as the free world works to establish more resilient and geographically diversified semiconductor ecosystems.

According to a recent article by FT (Source), the primary drivers for 2 nm technology development are the surging demand for custom and specialized chips, particularly in artificial intelligence (AI), and the need to create competitive alternatives to current large-scale semiconductor manufacturers. Rapidus, for instance, is targeting a niche in the AI market by producing bespoke chips that prioritize efficiency and can outperform more generic chips, such as those produced by Nvidia, in specific applications.

The motivation also includes addressing capacity limitations from dominant players like TSMC, which prioritizes large orders. Rapidus sees an opportunity to capture smaller customers who are willing to pay a premium for speed and customization. Additionally, geopolitical factors are influencing the push for advanced technology, with Japan aiming to reduce reliance on Taiwan's semiconductor manufacturing expertise and establish its own ecosystem for leading-edge production. 

This is why the semiconductor industry is advancing rapidly toward 3 nm and 2 nm process nodes, with leading players outlining production timelines and capacity expansions over the next five years. Below is a detailed overview of these developments, including plans from TSMC, Samsung, Intel, and Rapidus.

The forecast predicts a 540% growth in the global AI semiconductor market between 2020 and 2030, driven by increasing adoption across key segments such as servers, networking, edge devices, and PCs/smartphones. Servers are projected to dominate the market, reflecting the growing demand for AI in data centers and cloud computing, while networking and edge computing are expected to see rapid expansion, driven by real-time processing needs in IoT and automotive applications. Moderate growth is anticipated in the PCs/smartphone segment as AI integration in consumer electronics continues. Tokyo’s recent $65 billion investment in AI and semiconductor industries underscores the importance of this market, which is expected to exceed $400 billion by 2030, highlighting the transformative role of semiconductors in powering AI advancements across industries.

TSMC

Taiwan Semiconductor Manufacturing Company (TSMC) is enhancing its semiconductor fabrication capabilities globally, focusing on 3 nm and 2 nm and below nodes.

• 3 nm Production (Taiwan): TSMC began volume production of its 3 nm process technology in December 2022 at Fab 18, located in the Southern Taiwan Science Park (STSP). Fab 18 consists of eight phases, each featuring a cleanroom area of 58,000 square meters, roughly double the size of a standard logic fab. TSMC has invested over NT$1.86 trillion in Fab 18, creating more than 11,300 high-tech jobs.
  Source

• 2 nm Development (Taiwan): TSMC’s 2 nm process is scheduled for risk production in late 2024 and mass production in 2025. A new facility in Hsinchu Science Park is under construction, with equipment installation set for April 2024.
  Source

• 2 nm (Arizona, USA): TSMC is building a second fab in Arizona to produce 2 nm nodes, with production expected to begin in 2028. A third fab, focused on cutting-edge technologies, is planned for later this decade. This is part of a $40 billion investment, the largest foreign investment in Arizona's history.
  Source

Samsung

Samsung Electronics is expanding its semiconductor manufacturing capabilities in South Korea and the United States, focusing on 3 nm and 2 nm nodes.

• 3 nm Production (South Korea): Samsung began mass production of its first-generation 3 nm chips in the second half of 2022, using its proprietary Multi-Bridge Channel Field-Effect Transistor (MBCFET) technology, a Gate-All-Around (GAA) architecture. Second-generation 3 nm production began in 2023, offering improved energy efficiency and performance.
  Source

• 2 nm Development (South Korea): Samsung plans to start 2 nm production in 2025 for mobile devices, followed by high-performance computing in 2026 and automotive semiconductors by 2027. The 2 nm (SF2) process is expected to deliver a 12% performance increase, 25% power efficiency improvement, and 5% area reduction compared to 3 nm.
  Source

• Taylor Fab (Texas, USA): Samsung is constructing a $17 billion fab in Taylor, Texas. Initially planned for 4 nm production in late 2024, the fab may start directly with 2 nm technology in 2026 to align with Samsung’s broader roadmap.
  Source

Intel

Intel Corporation is investing in global semiconductor manufacturing, focusing on advanced nodes like Intel 3, Intel 20A, and Intel 18A.

• United States: Intel’s Fab 42 in Arizona produces 10 nm chips and is transitioning to Intel 7 and Intel 4 nodes. In Ohio, Intel is building two fabs with a $20 billion investment to produce Intel 18A by the decade's end.
  Source

• Europe: Intel’s Fab 34 in Ireland will produce Intel 4 technology using EUV lithography. In Germany, Intel delayed its is investing €17 billion to construct two fabs in Magdeburg, focusing on advanced nodes.
  Source

• Israel: Intel’s Fab 28 in Kiryat Gat, Israel, is transitioning from 10 nm to Intel 7 and Intel 4 processes. Intel has committed $10 billion to expand this facility.
  Source

Rapidus

Rapidus, a Japanese semiconductor start-up, aims to produce 2 nm chips, positioning itself as a significant player in the advanced semiconductor market.

• 2 nm Development: Rapidus plans to start trial production of 2 nm chips in April 2025, with mass production by 2027. The company is collaborating with IBM to integrate cutting-edge technology, including Extreme Ultraviolet (EUV) lithography.
  Source

• Manufacturing Facilities: Rapidus is building its IIM-1 fab in Chitose City, Hokkaido, Japan. The first EUV machine from ASML is expected to arrive in mid-December 2024.
  Source

• Strategic Approach: Rapidus is rethinking traditional manufacturing models by emphasizing smaller batch production with faster cycle times, aiming for greater efficiency and adaptability.
  Source

SMIC

China’s stake in leading-edge semiconductor manufacturing and AI is hindered by significant technological and geopolitical challenges. While domestic efforts, such as those by SMIC, have made strides in producing 7 nm chips, China remains far behind global leaders like TSMC, Samsung, and Intel, who are advancing toward 2 nm production. Critical dependencies on foreign equipment, such as ASML's EUV lithography machines, and U.S.-led export restrictions on advanced semiconductor tools and high-performance GPUs have further constrained its progress. Although China has invested heavily in AI development, its capabilities remain primarily focused on practical applications like surveillance and automation rather than leading innovation in foundational AI technologies. To conclude, China has an uphill battle to compete in the global semiconductor and AI industries.

Is the free world Decoupling from China and future risk of relying on Taiwan Fabs?

The global semiconductor industry is undergoing significant restructuring as it increasingly decouples from China and prepares for potential decoupling from Taiwan’s fabs. Geopolitical tensions, driven by concerns over China's ambitions toward Taiwan and its own restricted access to advanced chip-making technologies, have accelerated efforts by the US, Europe, and their allies to diversify supply chains and reduce dependency on both regions. Export controls targeting China, including restrictions on advanced chips and manufacturing tools, have prompted heavy investments in domestic semiconductor manufacturing in the US, Japan, South Korea, and Europe. Simultaneously, Taiwan’s pivotal role in leading-edge semiconductor production, dominated by TSMC, has highlighted vulnerabilities, spurring new fabs outside the island, such as TSMC’s facilities in Arizona and Samsung’s in Texas. These shifts reflect a broader trend toward creating more resilient, geographically dispersed semiconductor ecosystems that mitigate risks associated with reliance on any single region for critical technologies.

Current global plans for semiconductor manufacturing expansion aim to reduce dependency on Taiwan but fall short of ensuring sufficient non-Taiwan capacity for 2 nm and below nodes in the near term. Taiwan, led by TSMC, still dominates leading-edge semiconductor production, supplying over 90% of the world’s advanced chips. While significant investments are underway—such as TSMC's Arizona fabs, Samsung’s expansions in South Korea and Texas, and Intel's facilities in the US, Europe, and Israel—these efforts are unlikely to match Taiwan’s scale and technological leadership at 2 nm and below by 2027-2030.

For example, TSMC’s planned Arizona fab is projected to produce 2 nm chips by 2028, but its capacity will be a fraction of TSMC's output in Taiwan. Similarly, Samsung and Intel are progressing toward advanced nodes, but both face challenges in matching TSMC’s efficiency and yield at these cutting-edge technologies. Additionally, the complexity of EUV lithography and the industry's high R&D costs further limit the pace at which non-Taiwan fabs can scale to competitive capacities.

TSMC 2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects

TSMC’s New, Industry-Leading 2nm CMOS Logic Platform: In a late-news paper, TSMC researchers will unveil the world’s most advanced logic technology. It is the company’s forthcoming 2nm CMOS (i.e., N2), platform, designed for energy-efficient computing in AI, mobile, and HPC applications. It offers a 15% speed gain (or 30% power reduction) at >1.15x chip density versus the most advanced logic technology currently in production, TSMC’s own 3nm CMOS (N3) platform, introduced in late 2022.

The new N2 platform features GAA nanosheet transistors; middle-/back-end-of-line interconnects with the densest SRAM macro ever reported (~38Mb/mm²); and a holistic, system-technology co-optimized (STCO) architecture offering great design flexibility. That architecture includes a scalable copper-based redistribution layer and a flat passivation layer (for better performance, robust CPI, and seamless 3D integration); and through-silicon vias, or TSVs (for power/signal with F2F/F2B stacking). The researchers say the N2 platform is currently in risk production and scheduled for mass production in 2H’ 25. N2P (5% speed enhanced version of N2) targets to complete qualification in 2025 and mass production in 2026.

The cross-sectional image shows that the N2 platform’s Cu redistribution layer (RDL) and passivation provide seamless integration with 3D technologies.

Graph showing that the new N2 high-density cells gain 14~15% speed@power vs. N3E FinFlex 2-1 fin cells across the Vdd range; a 35% power savings at higher voltage; and a 24% power savings at lower voltage

The graph above compares two CMOS technology nodes, TSMC's N3E and N2, specifically for Arm's A715 core. N3E FinFlex (2-1 Fin) architecture, represented by the blue dotted line, operates at higher power but achieves higher speed than previous nodes. Operating at voltages between 0.5V and 0.9V, the N3E design can achieve significant performance levels but comes with a power increase. Now, N2 NanoFlex HD (High-Density) Energy-Efficient Cells as in the The N2 node, marked by the green dotted line, introduces "NanoFlex" cells that are optimized for energy efficiency. Compared to N3E, it achieves similar speeds but with substantially lower power consumption, marking a shift toward lower power designs in advanced nodes.

Key Improvements:

• When shifting from 0.6V to 0.55V in the N3E architecture, there's a 15% reduction in speed but a 24% reduction in power.
• For N2, at 0.85V, there's a 14% reduction in speed and a 35% reduction in power compared to similar performance points in N3E.
• These efficiency improvements are essential for high-performance applications in power-sensitive environments.

In summary, TSMC's N3E focuses on performance with FinFlex technology, while N2's NanoFlex HD cells target power efficiency, marking a clear trend in CMOS architecture evolution for balancing power and speed.

For the latest insights from the 2024 IEEE International Electron Devices Meeting (IEDM), including groundbreaking advancements in 2nm CMOS logic, extremely scaled transistors, monolithic CFET inverters, energy-efficient 3D computing-in-memory, and novel device technologies, you can explore the full press kit here.

Sources: 

IEDM Press kit Paper #2.1, “2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications,” G. Yeap et al, TSMC https://www.ieee-iedm.org/press-kit

TSMC's 22ULL ReRAM with Ruthenium Layer Challenges Fujitsu's TaO-Based Technology with an Iridium layer in Embedded Memory Race

Techinsights reports (link below) that TSMC and Fujitsu are leading the charge in embedded ReRAM technology, with TSMC's new 22ULL eReRAM introducing a significant challenge to Fujitsu's established 40 nm TaO-based eReRAM. Both companies employ different resistive materials—Fujitsu uses a tantalum oxide (TaO) layer enhanced with an iridium layer, while TSMC incorporates a hafnium oxide (HfO) layer, paired with a ruthenium (Ru) layer, which enhances performance and reliability. TSMC's 22ULL platform, featuring this advanced HfO and Ru-based ReRAM, is set to challenge Fujitsu's position, especially in critical applications like automotive and IoT, where efficiency and capacity are paramount. With TSMC offering both eMRAM and eReRAM solutions, the competition between these technologies will significantly influence the future of embedded memory devices.

Other materials with similar resistive switching properties include: titanium oxide (TiOx), nickel oxide (NiO), zinc oxide (ZnO), zinc titanate (Zn2TiO4), Manganese oxide (MnOx), magnesium oxide (MgO), aluminum oxide (AlOx), and zirconium dioxide (ZrO2).

Screendumps from Techinsights website, Top an overview table and below TSMC resp. Fujitsu 28 nm ReRAM.

Sources:

TSMC vs. Fujitsu: A Brief Comparison of 22ULL Embedded ReRAM Technologies | TechInsights

Intel's Strategic Leap with 14A Node and DSA: Pioneering Next-Gen Semiconductor Manufacturing

Semi Analysis recently published a deeper dive into of Directed Self Assembly (DSA) and prospects of Intel using it at their 14A node (Link below). Intel's latest efforts in semiconductor manufacturing have brought considerable attention to its 18A node, yet it's the 14A node that is most important according to the analysis for the success of Intel Foundry's IDM 2.0 strategy. While the industry watches the ongoing discussions around the merits of TSMC's N2 and Intel’s 18A technologies, Intel is quietly setting a foundational stage with its 14A node, aiming to solidify customer trust and secure critical, high-value chip projects for the future. A key element in Intel's strategy may be the adoption of DSA that could significantly reduce lithography costs. DSA utilizes the self-organizing properties of block copolymers (BCPs) that assemble into predetermined patterns when guided by an underlying template. This approach promises to lower the doses required in extreme ultraviolet (EUV) lithography, allowing for more efficient patterning at reduced costs.

However, integrating DSA into commercial manufacturing involves challenges such as defectivity and pattern limitations, which could hinder its adoption. So I looked more into historical patent filings and found that reveal a typical hype cycle with increased filings during periods of peak expectations, followed by a decline as practical challenges emerged. Intel and TSMC have been consistently filing DSA patents, indicating sustained investment and belief in DSA's potential. Merck, among other chemical suppliers, has significantly increased patent filings, aligning with technological advancements in DSA. Please find on overview below.

It is well known that Intel plans to be the first major company to implement ASML’s high-NA EUV lithography scanners in high volume, despite the higher costs associated with single exposure high-NA systems compared to low-NA double patterning. It was also recently reported on X and other places that ASML is delivering a High-NA System to another player. SemiAnalysis argues that, the economic challenge posed by high-NA technology is addressed through the integration of DSA, which can improve the final pattern quality and dramatically reduce the necessary dose, thus potentially making high-NA economically more viable.

The benefits of DSA are significant: 

• The ability to produce finer features with lower line edge roughness and increased throughput, thanks to its ability to heal discrepancies in the EUV guide patterns. 
• Substantial cost savings and improved yield, especially for layers critical to the performance of advanced logic chips (bigger dies like AI accelerators).

However, DSA's integration into a commercial manufacturing environment is not without risks. The risks associated with Intel's adoption of DSA include:

• The primary risk with any new patterning technology is defectivity, for DSA it is linked to the chemical purity of the block copolymers (BCP). Synthesizing BCP to extremely high purities is challenging, and any inhomogeneity directly impacts the critical dimension (CD), leading to defects. Trace metals need to be below 10 parts-per-trillion, and filtering out organic impurities is difficult, impacting the viability of DSA for mass production. My assessment - Expect this to come from a MERCK or a Japanese chemical vendor.
• DSA is inherently limited to producing 1D line/space patterns or contact hole arrays, restricted to a single pitch per layer. This complicates the integration with other process technologies that might require more diverse patterning capabilities. However, these issues have potential solutions similar to those used in multi-patterning schemes.
• Despite the theoretical benefits and recent advances in DSA, it remains largely untested in high-volume, leading-edge manufacturing. Intel is pioneering the use in high-NA scenarios, but the broader adoption across the industry, including by competitors like TSMC who are also developing DSA, remains uncertain. 

Source: Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA) (semianalysis.com)

So let´s do the Patbase Test - how does this hold out if we dig into historical and current patent filing by the suspects!

Yes indeed, we have seen much increased filing the past decade or so representing a typical hype cycle. The hype cycle is a model developed by Gartner that describes the progression of a technology from inception to widespread adoption and maturity. It typically consists of five phases: the Technology Trigger, Peak of Inflated Expectations, Trough of Disillusionment, Slope of Enlightenment, and Plateau of Productivity. So for DSA in semiconductor manufacturing, the technology first garnered attention when its potential applications in advanced lithography were identified (2000-2010), marking the Technology Trigger. Interest surged about 2011, leading to a Peak of Inflated Expectations around 2016/2017, evidenced by a spike in patent filings as companies raced to capitalize on the emerging technology. However, as practical and economic challenges such as defectivity and integration complexities became evident, the enthusiasm waned, and DSA entered the Trough of Disillusionment. During this phase, the technology's limitations led to a decline in interest as initial expectations were not met. Over time, as more sustainable applications and improvements are developed, DSA may progress into the Slope of Enlightenment, where understanding and optimization occur as described in the assessment by SemiAnalysis, before finally reaching the Plateau of Productivity in the years to come, where it becomes a standard part of semiconductor manufacturing processes. This progression through the hype cycle reflects the typical maturation path of innovative technologies in the industry. Please note that there is a delay in patent filing data of up to 18 months so 2022, 2023 and 2024 are not complete yet.

Patent filing since 2000 in DSA (Patbase, 2024-04-19)

2. Yes, Intel is actively filing DSA patents and in the lead, and so is TSMC, along with other key players in the ecosystem. Over the past decade, the pattern of DSA patent filings has been quite revealing. Initially, GlobalFoundries and IBM in Upstate New York were early filers. GlobalFoundries ceased their filings around the time they decided not to pursue 7 nm and nodes below. IBM also stopped filing after completing their 2 nm demonstration on 300 mm wafers in 2021. Main contenders Intel and TSMC have been consistently filing DSA patents throughout the hype cycle and have continued to do so. Notably, there has been a clear acceleration in Intel's patent filings since 2019, although there was a slight drop during the COVID-19 lockdowns. Looking at chemical suppliers, Merck has taken the lead, with increased filings beginning in parallel with Intel from 2019 onwards, and accelerating until today. Other suppliers such as JSR, Shin-Etsu, and Brewer Science are also active in the DSA space. In the segment of wafer equipment OEMs, Tokyo Electron and SCREEN have been dominant. However, SCREEN appears to have recently exited the game.

DSA Patent filing last decade (Patbase , 2024-04-19)

In Summary - good assessment by SemiAnalysis and i passes the Patbase Test!

TSMC Set to Revolutionize Chip Technology with Trillion-Transistor Packages by 2030

In a groundbreaking announcement at IEDM, TSMC has unveiled ambitious plans to develop chip packages harboring over one trillion transistors and monolithic chips with more than 200 billion transistors by 2030. This visionary goal is set to be achieved through the development of advanced production nodes, including 2nm-class N2 and N2P, and even finer 1.4nm-class A14 and 1nm-class A10 processes. Despite the slowdown in process technology development and existing technical and financial challenges, TSMC remains optimistic about accomplishing these targets within the next five to six years. The company, renowned as the world's largest semiconductor foundry, is confident in overcoming industry hurdles to bring these complex, multi-chiplet systems and more intricate monolithic chips to the forefront of technology. This development signals a significant leap in chip architecture, promising transformative advancements in the tech industry.

Source:

https://www.kitguru.net/channel/generaltech/joao-silva/tsmc-expects-to-create-chip-packages-with-over-1-trillion-transistors-by-2030/

TSMC To Report Breakthrough in NMOS Nanosheets Using Ultra-Thin MoS2 Channels at IEDM 2023

A TSMC-led research team, in collaboration with National Yang Ming Chiao Tung University and National Applied Research Laboratories, has unveiled promising results for using ultra-thin transition metal dichalcogenides (TMDs), specifically MoS2, as the channel material in NMOS nanosheets. Their innovative approach deviates from the conventional method of thinning Si channels. The team's devices exhibited impressive performance metrics: a positive threshold voltage (VTH) of ~1.0 V, a high on-current of ~370 µA/µm at VDS = 1 V, a large on/off ratio of 1E8, and a low contact resistance ranging between 0.37-0.58 kΩ-µm. These outcomes were primarily attributed to the introduction of a novel C-shaped wrap-around contact, which enhances contact area, and an optimized gate stack. While the devices demonstrated satisfactory mechanical stability, a challenge remains in addressing defect creation within the MoS2 channels. This groundbreaking study, titled "Monolayer-MoS2 Stacked Nanosheet Channel with C-type Metal Contact" by Y-Y Chung et al., is a pivotal step forward in nanosheet scaling using TMDs.

ALD is a the technique for the precise and uniform synthesis of MoS₂, especially for semiconductor applications on large-scale wafers. The choice of precursors plays a crucial role in achieving optimal deposition characteristics. Mo (CO) 6 and H2S have been identified as the primary precursors for depositing molybdenum and sulfur components, respectively. These precursors have demonstrated the capacity for self-limiting growth behavior within a specific ALD temperature window, leading to uniform MoS₂ layers. Notably, this process has been successfully scaled up to achieve highly uniform film growth on large 300 mm SiO2/Si wafers, marking its potential for industry-level manufacturing. The ability to maintain uniformity and thickness control on such wafers emphasizes the potential of ALD in integrating MoS₂ into next-generation electronic devices and further underscores the significance of selecting appropriate precursors for optimal deposition outcomes. Other precursors have been investigated. MoCl₅ and MoF₆ serve as alternative molybdenum sources. For the sulfur component, H₂S is commonly paired with molybdenum precursors, but (CH₃)₂S has also been explored. The choice of these precursors directly impacts the properties of the resulting MoS₂ film in the ALD process and therefore precursor development for 2D MoS2 is a hot field of ongoing research.

While deposition methods are abundant, etching processes are comparatively scarce. Recent research by Elton Graugnard et al also introduces a thermal Atomic Layer Etching (ALE) technique for MoS2, leveraging MoF6 for fluorination, alternated with H2O exposures, to etch both crystalline and amorphous MoS2 films. This process has been characterized using various analytical techniques like QCM, FTIR, and QMS. The etching is temperature-dependent, with a significant increase in mass change per cycle as temperature rises. The mechanism involves two-stage oxidation of Mo, producing volatile byproducts. The resultant etch rates were established for different films, and post-etch annealing rendered crystalline MoS2 films. The thermal MoS2 ALE introduces a promising low-temperature method for embedding MoS2 films in large-scale device manufacturing.

Chem. Mater. 2023, 35, 3, 927-936

Sources:

 https://www.ieee-iedm.org/press-kit

https://pubs.acs.org/doi/10.1021/acs.chemmater.2c02549

The Semiconductor Showdown: TSMC's GAA FETs vs. Intel's RibbonFET

The semiconductor industry is witnessing a fierce competition between TSMC and Intel, as they advance transistor designs with TSMC's Gate-All-Around (GAA) FETs and Intel's RibbonFET. Atomic Layer Deposition (ALD) plays an instrumental role in crafting these intricate designs. As the race to dominate the microelectronics realm heats up, the innovations from these giants foretell a transformative phase for technology between 2024 and 2026. This article dives into their respective technologies, comparing their strategies and highlighting the future implications for the semiconductor industry.

Both TSMC and Intel are pushing the boundaries of semiconductor innovation with advanced transistor designs. TSMC's GAA (Gate-All-Around) FET (Field-Effect Transistor) technology and Intel's RibbonFET are prime examples of this evolution. ALD is crucial for GAA FET production, ensuring precision and atomically thin, conformal or on purpose non-conformal or selectively deposited films. As transistors miniaturized, ALD replaced traditional silicon dioxide gate dielectrics with high-k materials, reducing gate leakage and offering enhanced uniformity. One of the challenges in GAA FETs is accurately aligning the gate material around the channel; ALD facilitates this through self-aligned processes. Additionally, in configurations with multiple gates or nanosheets, ALD accurately deposits spacer materials, preserving the necessary separation between nanosheets. ALD also offers precise doping for GAA FETs, including NMOS and PMOS. With atomic-level control, ALD introduces dopants like phosphorus for NMOS and boron for PMOS. Given the shrinking device dimensions, ALD's precision becomes vital, especially when considering techniques like solid-state doping to achieve ultra-shallow profiles.

TSMC's Gate-All-Around (GAA) FET technology represents a significant shift from the traditional FinFET transistor design. In a GAA FET, the gate material wraps entirely around the channel, unlike the FinFET where the gate is only on three sides of a vertical fin. This complete encirclement provides enhanced control over the current flow through the channel, reducing leakage current and allowing for lower voltage operation. The result is improved energy efficiency and performance.

TSMC's roadmap to N2. (Image: TSMC)

On the other hand, Intel's RibbonFET introduces a similar gate-all-around design but with a unique twist. Instead of a traditional vertical fin, RibbonFET uses nanosheet technology, where multiple flat nano-sheets are stacked to form the channel. This design offers even better control of the current flow, leading to significant gains in performance and efficiency. RibbonFET is one of Intel's flagship innovations for its advanced nodes, emphasizing the company's commitment to reclaiming technology leadership in the semiconductor space.

Intel 20A Ribbon FET (intel.com)

In a recent article Tom´s Hardware (Anton Shilow, link below) compares the advanced semiconductor technology nodes from industry TSMC and Intel, focusing on TSMC's N3P and N2 nodes against Intel's 20A and 18A nodes. Forecasted for release between 2024 and 2026, these nodes represent the forefront of semiconductor innovation. TSMC's N3P, a 3nm-class node, is set to be available by 2025 and offers performance comparable to Intel's 18A. Interestingly, TSMC's 2nm-class N2, expected in the second half of 2025, is anticipated to outpace Intel's 18A in terms of power, performance, and area advantages. Intel's 20A, arriving in 2024, promises significant advancements by introducing RibbonFET gate-all-around transistors and a backside power delivery network. The subsequent 18A will further refine these innovations. While TSMC leans on its proven FinFET technology for the N3P, it plans to introduce nanosheet GAA transistors in the N2. 

As the semiconductor race intensifies, both companies are heavily invested in outpacing each other, with TSMC focusing on technology maturity and cost-effectiveness, and Intel aiming to regain its technology leadership. The dynamics between these tech giants will shape the semiconductor industry's future.

Comparison of Advanced Semiconductor Technology Nodes: TSMC N3P & N2 vs. Intel 20A & 18A, highlighting the competitive landscape of the semiconductor industry for the years 2024-2026 based on Toms Hardware article below.

Sources: 

TSMC: Our 3nm Node Comparable to Intel's 1.8nm Tech | Tom's Hardware (tomshardware.com)

Intel and TSMC company web pages

TSMC Foresees Stabilization in PC and Smartphone Demand; Remains Optimistic Amid Semiconductor Challenges

TSMC believes that the demand for personal computers and smartphones is beginning to stabilize after an extended downturn. During an earnings call, TSMC's CEO, C.C. Wei, stated that while there are early signs of stabilization in these markets, it's premature to predict a rapid recovery. There's been a notable decrease in global smartphone shipments, dropping from 1.4 billion units to 1.1 billion. However, there's been consistent demand in areas like artificial intelligence and high-performance computing, which are projected to stay strong through 2024-2025. Wei foresees potential for growth in 2024. 

He also commented on US export controls and their potential long-term effects. This comes after the US tightened regulations on AI chip exports to China, impacting major TSMC clients like Nvidia. Despite a 24.8% fall in TSMC's net profit for Q3, the company remains optimistic about its prospects, especially as it collaborates with Intel on chip production.

Source: TSMC says PC and smartphone markets starting to bottom out - Nikkei Asia

Intel to Sell 10% Stake in IMS Nanofabrication to TSMC for $4.3 Billion

Intel will sell a 10% stake in IMS Nanofabrication to TSMC, valuing IMS at $4.3 billion, maintaining Intel's majority ownership. IMS leads in multi-beam mask writing tools for advanced extreme ultraviolet lithography, crucial for AI and mobile applications. This investment enhances IMS' independence and fosters innovation, including high-numerical-aperture EUV technology. The deal is set to close in Q4 2023. IMS is vital for semiconductor industry growth, with the market projected to reach $1 trillion by 2030. Intel acquired IMS in 2015 and sold a 20% stake to Bain Capital earlier in 2023, while TSMC's partnership with IMS dates back to 2012.

About IMS Nanofabrication

IMS Nanofabrication Global, LLC, a majority-owned subsidiary of Intel Corporation, is the global technology leader for multi-beam mask writers. Its customers are the largest chip manufacturers in the world, who rely on its technology to produce current and future chip generations. IMS’ innovative multi-beam writers play a key role in chip manufacturing and provide significant added value to the semiconductor industry. They are continually customized and refined by an interdisciplinary team, in line with the latest market demands. Over the last 10 years, IMS has perfected its electron-based multi-beam technology. The first-generation multi-beam mask writer, MBMW-101, is successfully operating all over the world. The second-generation multi-beam mask writer, MBMW-201, entered the mask writer market in the first quarter of 2019 for the 5nm technology node. And this year, IMS is launching MBMW-301, a fourth-generation multi-beam mask writer that delivers unprecedented performance. Learn more at www.ims.co.at/en/.

ASML Remains on Track to Deliver High NA EUV Machines in 2023

ASML, the leading semiconductor equipment manufacturer, is set to ship the first pilot tool from its next product line in 2023, despite some supplier delays, according to CEO Peter Wennink. These High NA EUV machines, crucial for top chipmakers to create smaller and better chips in the coming decade, will cost over $300 million euros each and provide up to 70% better resolution. ASML currently dominates the lithography market, a pivotal step in chipmaking, and is seeing strong demand for its older DUV machines, with 30% sales growth forecasted in 2023, primarily driven by Chinese customers.

ASML's High NA EUV machines are used by a range of prominent semiconductor manufacturers, including TSMC, Intel, Samsung, SK Hynix, and Micron. These chipmakers rely on ASML's cutting-edge lithography equipment to manufacture semiconductor chips, from microprocessors to memory chips.

"High NA" stands for "High Numerical Aperture." Numerical Aperture (NA) is a measure of the ability of an optical system, such as a lens or mirror, to gather and focus light. A higher numerical aperture indicates a greater ability to capture light and provide finer detail and resolution in imaging or lithography processes. ASML's High NA EUV machines, are designed to gather light from a wider angle compared to their previous generation tools. This wider angle collection of light allows for significantly improved resolution in the semiconductor manufacturing process, making it possible to create smaller and more advanced semiconductor chips with greater precision required for the Ångström Era - basically the sub 2 nm nodes.

Source:

ASML to ship first pilot tool in its next product line in 2023 -CEO | Reuters

TSMC's Silicon Photonics Investment Boosts AI Chip Efficiency for ChatGPT

Taiwan Semiconductor Manufacturing Co. (TSMC) is heavily investing in silicon photonics, combining silicon chips and optical tech to enhance AI applications like ChatGPT. TSMC, the world's top contract chipmaker, aims to improve AI chip performance through silicon photonics, addressing energy efficiency and computing power issues. This technology integrates optics with silicon-based circuits for high-speed, low-power data transmission. Silicon photonics attracts substantial investment across the semiconductor industry, impacting data centers, supercomputers, networking, and more. TSMC is developing integrated silicon photonics systems with advanced chip packaging technology but has not yet entered mass production. The global silicon photonics market is projected to grow to $7.86 billion by 2030.

Source:

TSMC bets on silicon photonics to enable more powerful ChatGPT - Nikkei Asia

TSMC Marks Major Milestone: First EUV Machine Installed in Arizona Fab, Job Opportunities Open

Taiwan Semiconductor Manufacturing Co. (TSMC) has achieved a significant milestone in its Arizona manufacturing venture by installing its inaugural extreme ultraviolet lithography (EUV) machine. This advanced machine, procured from Dutch semiconductor equipment leader ASML Holding NV, is a pivotal asset for TSMC's future high-end chip production endeavors.

EUV technology is a critical aspect of semiconductor fabrication, facilitating the printing of intricate designs on microchips significantly smaller than a human hair. TSMC's achievement underscores its commitment to innovation and technological leadership.

While the installation of the EUV machine marks a remarkable accomplishment, TSMC acknowledges that the setup of the new fab in Arizona involves numerous additional tasks. The company emphasized the need for approximately 2,000 skilled workers to handle the installation of various equipment pieces and services in the complex. This requirement stems from TSMC's unique tool configurations and specifications.

TSMC, recognized as the world's largest contract chip manufacturer, is channeling substantial investments amounting to $40 billion into constructing two wafer fabs in Phoenix. The first facility will employ the advanced 4-nanometer process, while the second, already under construction, will utilize the more sophisticated 3-nanometer process. This latter technology has already entered mass production in Taiwan.

The presence of skilled workers has been a contentious topic linked to the Arizona project. TSMC Chairman Mark Liu explained that a deficiency in experts capable of properly installing equipment at the Arizona site has led to a delay in mass production, now projected for 2025 rather than late 2024.

However, TSMC's approach to addressing this shortfall has sparked debates. The company's bid to bring in around 500 Taiwanese workers on temporary E-2 visas has faced resistance from local unions, who assert that prioritizing American jobs is paramount, especially considering the significant subsidies TSMC seeks under the CHIPS and Science Act. This legislation, signed by President Joe Biden, encourages semiconductor investments in the United States.

US Senator Mark Kelly of Arizona emphasized that the visa applications will be evaluated in accordance with established laws and procedures. As TSMC navigates these challenges, its progress in Arizona remains a focal point in the semiconductor industry's dynamic landscape.

TSMC installs first EUV machine in U.S.; job opening ads posted - Focus Taiwan

TSMC's 2nm Chip Plant Faces Delays in Taichung, Water and Electricity Hurdles Cited

Taiwan Semiconductor Manufacturing Company (TSMC) is experiencing setbacks in the construction of its highly anticipated 2-nanometer chip manufacturing plant in Taichung City, Taiwan. Delays have been attributed to challenges related to water and electricity supply, crucial for the resource-intensive chip fabrication process. This development comes as TSMC seeks to expand its manufacturing capabilities amid a rapidly evolving semiconductor landscape.

aiwan Semiconductor Manufacturing Company (TSMC), a global leader in semiconductor manufacturing, is facing delays in the construction of its planned 2-nanometer chip manufacturing plant in Taichung City, Taiwan. The director of the agency responsible for managing science and technology infrastructure on the island has indicated that the construction will not commence by the end of this year.

TSMC initially intended to establish two 2-nanometer manufacturing sites in Taiwan, with the first site in Hsinchu City. However, due to delays in the approval process for the Taichung site, the company confirmed its decision to also manufacture next-generation chips in Kaohsiung City.

The primary challenges affecting the Taichung site relate to the plant's water and electricity requirements. Chip fabrication demands high-purity conditions, necessitating large volumes of pure water to meet product purity standards. TSMC has encountered obstacles in securing an adequate water supply, particularly during a 2021 drought that led the company to employ water tankers to fulfill its water needs.

These developments underscore the intricate logistical challenges inherent in semiconductor manufacturing, where resource-intensive processes require precise environmental conditions. While TSMC continues to innovate and expand its global operations, addressing these challenges becomes paramount to maintaining its position at the forefront of the semiconductor industry.

Source: TSMC's Advanced 2nm Site Remains In Limbo, EUV Machines In Play In Arizona (wccftech.com)

Intel Takes Strategic Steps to Regain Semiconductor Chip Leadership

Intel plans to separate its manufacturing and fabless units to regain its semiconductor chip leadership. The move aims to serve emerging markets and make chip manufacturing more efficient. Intel seeks to emulate TSMC's success and become the second-largest external foundry by 2030.

In an effort to reclaim its position as a leader in the semiconductor chip industry, Intel has announced plans to separate its manufacturing and fabless units. This strategic move aims to address evolving market dynamics and capitalize on emerging sectors such as cloud computing, edge computing, and artificial intelligence (AI). By granting independence to its foundry business and diversifying its chip production, Intel aims to regain its competitive edge and accelerate chip development.

Diversifying into New Markets

Intel's factories have traditionally focused on serving the PC and server markets, but the company recognizes the need to adapt to the changing landscape. By separating fabless and manufacturing operations, Intel can now cater to a broader customer base, including external clients. The new fabs, set to be operational by early 2024, will manufacture chips for non-Intel customers, making Intel a potential competitor to contract chip manufacturers like TSMC.

Emulating the TSMC Playbook

Intel's strategy shares similarities with Taiwan Semiconductor Manufacturing Co. (TSMC), which has successfully produced chips for companies like Nvidia, Apple, and AMD. TSMC's approach of guaranteeing capacity to long-term partners during the recent chip shortage has proven effective. Intel aims to replicate this success by becoming the second-largest external foundry by 2030 and generating more than $20 billion in manufacturing revenue.

Competing for Internal Fab Capacity

The separation of fabless and manufacturing units introduces a new dynamic within Intel. Internal chip design units will now compete with external customers for fab capacity, potentially accelerating Intel's internal chip design efforts. The competition for volume will drive efficiency and faster innovation, as internal business units can leverage third-party foundries if they are willing to pay top dollar for guaranteed capacity.

Reviving Manufacturing Prowess

Intel's ability to deliver chips on time has been a key challenge, allowing TSMC to emerge as a leader in the industry. However, Intel aims to regain its position by focusing on advanced nodes such as the Intel 18A process, which incorporates cutting-edge technologies like gate-all-around (GAA) transistors. By emphasizing more efficient manufacturing processes and performance improvements, Intel intends to win back customers and regain its reputation as a reliable chip manufacturer.

Intel is expanding as a foundry in Europe

Intel's expansion plans in Europe took a significant step forward as the company signed a deal with the German government to build a €30 billion chip manufacturing site in Magdeburg. Germany will cover a third of the investment, marking the largest foreign direct investment in the country's modern history. The agreement was signed during a meeting between German Chancellor Olaf Scholz and Intel CEO Pat Gelsinger in Berlin. The investment will significantly expand Intel's production capacity in Europe and is seen as a crucial strategic move for Germany and Europe to establish self-sufficiency in strategic technologies. The project, known as the "Silicon Junction," is expected to create 3,000 high-quality jobs and additional positions in supplier networks. The EU's executive branch will review the plan to ensure fair competition. With this expansion, Germany aims to become one of the major global semiconductor production sites and reduce its dependence on imported chips and global supply chains. The completion of the twin semiconductor plants is expected by 2027 and will contribute to the EU's goal of decreasing reliance on China and the US for microchip production.

Conclusion

Intel's decision to separate its manufacturing and fabless units marks a strategic shift aimed at regaining its leadership in the semiconductor chip industry. By diversifying into emerging markets, emulating successful models like TSMC's, and focusing on advanced manufacturing processes, Intel hopes to reclaim its competitive edge and position itself as a leading player in the evolving landscape of chip manufacturing.

Source: 

Intel to build €30 billion chip plant in Germany | Euronews

Intel Looks to Regain Semiconductor Chip Leadership from TSMC; Separates Manufacturing and Fabless Units (hpcwire.com)

Samsung to focus on treatment of gas used in chip production to achieve net-zero emissions

A major cause of greenhouse gas emissions is process gas used in semiconductor wafer manufacturing comes from processing equipment such as reactive ion etching (RIE) and deposition (CVD and ALD). You can read and watch an interview here and study that paper that was recently published by me and my professor friends Henrik Pedersen and Sean Barry:

BALD Engineering - Born in Finland, Born to ALD: Green CVD: How Sustainable is Thin Film Deposition?

Green CVD-Toward a sustainable philosophy for thin film deposition by chemical vapor deposition

It is almost obvious that higher VPs at Samsung and TSMC (LINK) did just that ;-)

[Korea Herald, Link below] Advancing abatement technologies to reduce carbon emissions is the top priority in the Samsung Electronics semiconductor unit's goal to become carbon neutral by 2050, a top official said Friday.

"Treatment of gas used to manufacture semiconductor chips is our biggest focus in our spending (to achieve net-zero emissions)," Song Doo-guen, executive vice president and head of the Environment ＆ Safety Center at Samsung Electronics, told reporters at a briefing in Seoul.

According to the article, Song Doo-guen, executive vice president and head of the Environment & Safety Center at Samsung Electronics, speaks at a briefing in Seoul, Friday and announced that:

• Samsung has pledged a 7 trillion won ($5 billion) investment to achieve its climate ambitions, and announced that it had recently joined RE100, a coalition comprising 380 global enterprises committed to becoming 100 percent renewable.
• Alongside the plan to cut direct carbon emissions, Samsung has also laid out a raft of plans to reduce indirect emissions, mainly by pursuing ultralow-power chip products.
• Other eco-conscious plans it has drawn up include capping the maximum use of freshwater to 300,000 tons a day by 2030 and eradicating gaseous and liquid pollutants by 2040 with treatment technology.

Source: Samsung chip plants look to stamp out carbon footprint (koreaherald.com)

Inside TSMC, the Taiwanese chipmaking giant that’s building a new plant in Phoenix

[CNBC, link below] Recently CNBC got an exclusive tour of the US$ 12 billion semiconductor fab, in Phoenix, Arizona, where TSMC will start making 5 nm chips in 2024. The company says it will ramp up to produce 20,000 wafers each month.

“This project is designed as a 5 nm fab. Actually, it’s a copy from the fab we have in Taiwan,” Chen said.

Nearby, one of the world’s largest cranes was lifted to its full height of 200 feet. The 2,300-ton crane was brought to the site on 153 semi trucks. Site supervisor Jim White said contractors have moved nearly 4 million cubic yards of dirt and have used more than 260 million gallons of water since construction began in April.

Building a fab and making chips takes an incredible amount of water, not an abundant resource in the middle of the desert. Arizona’s biggest water source is groundwater, but deep wells at big farms are using water up faster than it’s naturally replenished. Chen said TSMC needs around 4.7 million gallons of water each day to support production. In Arizona, TSMC said, an on-site water treatment center will recycle up to 90% of water used at the fab.

Full article with video:

TSMC: Taiwanese chipmaker ramping production to end chip shortage (cnbc.com)

We got an exclusive tour inside Taiwanese chipmaking giant TSMC's $12 billion fabrication plant outside Phoenix, Arizona. Watch the full video here: https://t.co/00keVTCxah pic.twitter.com/JV2ceg6l6v

— CNBC (@CNBC) September 17, 2022

TSMC to double energy efficiency and clean water consumption for semiconductor wafer manufacturing

According to TSMC 2021 Sustainability Report, they aim to by 2030, amongst many goals & actions:

• double energy efficiency after five years of mass production for each process technology
• reduce unit water consumption (liter/12-inch equivalent wafer mask layers) by 30% (Base year: 2010)

Link to report: e-all.pdf (tsmc.com)

Comparison confirms that SMIC reaches 7nm without access to western equipment & technologies

Similarities with TSMC 7nm have been found

After TechInsights revealed their initial findings on the SMIC MinerVa Bitcoin mining processor, their team did further analysis and comparison against TSMC 7nm. This new analysis confirms that despite current sanctions restricting access to the most advanced equipment technologies, Chinese Semiconductor Manufacturing International Corporation (SMIC) has used 7nm technology to manufacture the MinerVa Bitcoin Miner application-specific integrated circuit (ASIC).

The TechInsights analysis also uncovered many similarities between the SMIC 7nm and the TSMC 7nm, which are available in our comparison brief.

Source: SMIC 7nm is truly 7nm technology, how it compares to TSMC 7nm | TechInsights

According to the SeekingAlpha assessment earlier this year (Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha) SMIC is using a large amount of multiple pattering mask layers like in the first TSMC and Samsung 7 nm nodes (N7). 

"At 7nm, normally 15 DUV systems and 5 EUV systems are demanded, depending on chip type and company. However, since SMIC is not permitted to use EUV, then they will be substituted by DUV, and 20 DUV systems will be used.

In both cases, multiple patterning is done to delineate that pattern, whether it is 28nm or 7nm. This multiple patterning process is more or less a trick to reach even the 28nm dimensions. The multiple patterning is typically a combination of deposition, etch, and lithography steps.

If we look at Chart 3 below, using immersion DUV (ArF-1) at the 20nm node there are 13 mask layers, each of which uses multiple dep-etch steps. If we move across the top of the chart, at 10nm there are 18 mask layers, an increase of 50% in the use of deposition-etch steps.

Multiple patterning at the 7nm node, as shown in the bottom left of the chart, requires 27 mask layers. However, by switching to EUV (bottom right) at 7nm, only 14 mask layers are required, similar to the 20nm node with DUV.

The terminology is as follows in switching from DUV to EUV:Double litho, double etch (LELE) process will be eliminated

While ArF-I would continue to be used for the self-aligned double patterning (SADP) and

Self-aligned quadruple patterning (SAQP) processes."

 

Table from SeekingAlpha as cited above

From an ALD point of view, the FEOL and metallization up to M2 use 19 in the case of Immersion Lithography (N7) vs 10 in the case of EUV (N7+) ALD spacer-defined multiple patterning masks (SADP or SAQP). However, the bigger difference is in etch for LELE etc., where EUV N7+ uses only 2 such masks.

TSMC Self-Aligned Via Process Development for Beyond the 3nm Node

Semiwiki Tom Dillinger reports on an interesting paper by TSMC at the recent IEDM 2021 conference in San Francisco using selective ALD with the help of SAMs or Dielectric on Dielectric (DOD) as it is called.

From the article sumary: Continued interconnect scaling below the 3nm node will necessitate unique process development research to maintain electrical and reliability specs in the presence of (up to 4nm) overlay error. The need for low-K interlevel dielectrics is a given – yet, the via etch in these materials is not especially tolerant of EPE.

TSMC has demonstrated a potential process flow for a “self-aligned via” with an additional DoD material. The etch rate differential of the DoD results in more robust via-to-adjacent metal reliability. This process flow utilizes two unique steps – the SAM of a blocking material on metal surfaces, and the selective ALD of a dielectric-on-dielectric.

Full article: Self-Aligned Via Process Development for Beyond the 3nm... - SemiWiki