Intel's Strategic Leap with 14A Node and DSA: Pioneering Next-Gen Semiconductor Manufacturing

Semi Analysis recently published a deeper dive into of Directed Self Assembly (DSA) and prospects of Intel using it at their 14A node (Link below). Intel's latest efforts in semiconductor manufacturing have brought considerable attention to its 18A node, yet it's the 14A node that is most important according to the analysis for the success of Intel Foundry's IDM 2.0 strategy. While the industry watches the ongoing discussions around the merits of TSMC's N2 and Intel’s 18A technologies, Intel is quietly setting a foundational stage with its 14A node, aiming to solidify customer trust and secure critical, high-value chip projects for the future. A key element in Intel's strategy may be the adoption of DSA that could significantly reduce lithography costs. DSA utilizes the self-organizing properties of block copolymers (BCPs) that assemble into predetermined patterns when guided by an underlying template. This approach promises to lower the doses required in extreme ultraviolet (EUV) lithography, allowing for more efficient patterning at reduced costs.

However, integrating DSA into commercial manufacturing involves challenges such as defectivity and pattern limitations, which could hinder its adoption. So I looked more into historical patent filings and found that reveal a typical hype cycle with increased filings during periods of peak expectations, followed by a decline as practical challenges emerged. Intel and TSMC have been consistently filing DSA patents, indicating sustained investment and belief in DSA's potential. Merck, among other chemical suppliers, has significantly increased patent filings, aligning with technological advancements in DSA. Please find on overview below.

It is well known that Intel plans to be the first major company to implement ASML’s high-NA EUV lithography scanners in high volume, despite the higher costs associated with single exposure high-NA systems compared to low-NA double patterning. It was also recently reported on X and other places that ASML is delivering a High-NA System to another player. SemiAnalysis argues that, the economic challenge posed by high-NA technology is addressed through the integration of DSA, which can improve the final pattern quality and dramatically reduce the necessary dose, thus potentially making high-NA economically more viable.

The benefits of DSA are significant: 

• The ability to produce finer features with lower line edge roughness and increased throughput, thanks to its ability to heal discrepancies in the EUV guide patterns. 
• Substantial cost savings and improved yield, especially for layers critical to the performance of advanced logic chips (bigger dies like AI accelerators).

However, DSA's integration into a commercial manufacturing environment is not without risks. The risks associated with Intel's adoption of DSA include:

• The primary risk with any new patterning technology is defectivity, for DSA it is linked to the chemical purity of the block copolymers (BCP). Synthesizing BCP to extremely high purities is challenging, and any inhomogeneity directly impacts the critical dimension (CD), leading to defects. Trace metals need to be below 10 parts-per-trillion, and filtering out organic impurities is difficult, impacting the viability of DSA for mass production. My assessment - Expect this to come from a MERCK or a Japanese chemical vendor.
• DSA is inherently limited to producing 1D line/space patterns or contact hole arrays, restricted to a single pitch per layer. This complicates the integration with other process technologies that might require more diverse patterning capabilities. However, these issues have potential solutions similar to those used in multi-patterning schemes.
• Despite the theoretical benefits and recent advances in DSA, it remains largely untested in high-volume, leading-edge manufacturing. Intel is pioneering the use in high-NA scenarios, but the broader adoption across the industry, including by competitors like TSMC who are also developing DSA, remains uncertain. 

Source: Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA) (semianalysis.com)

So let´s do the Patbase Test - how does this hold out if we dig into historical and current patent filing by the suspects!

Yes indeed, we have seen much increased filing the past decade or so representing a typical hype cycle. The hype cycle is a model developed by Gartner that describes the progression of a technology from inception to widespread adoption and maturity. It typically consists of five phases: the Technology Trigger, Peak of Inflated Expectations, Trough of Disillusionment, Slope of Enlightenment, and Plateau of Productivity. So for DSA in semiconductor manufacturing, the technology first garnered attention when its potential applications in advanced lithography were identified (2000-2010), marking the Technology Trigger. Interest surged about 2011, leading to a Peak of Inflated Expectations around 2016/2017, evidenced by a spike in patent filings as companies raced to capitalize on the emerging technology. However, as practical and economic challenges such as defectivity and integration complexities became evident, the enthusiasm waned, and DSA entered the Trough of Disillusionment. During this phase, the technology's limitations led to a decline in interest as initial expectations were not met. Over time, as more sustainable applications and improvements are developed, DSA may progress into the Slope of Enlightenment, where understanding and optimization occur as described in the assessment by SemiAnalysis, before finally reaching the Plateau of Productivity in the years to come, where it becomes a standard part of semiconductor manufacturing processes. This progression through the hype cycle reflects the typical maturation path of innovative technologies in the industry. Please note that there is a delay in patent filing data of up to 18 months so 2022, 2023 and 2024 are not complete yet.

Patent filing since 2000 in DSA (Patbase, 2024-04-19)

2. Yes, Intel is actively filing DSA patents and in the lead, and so is TSMC, along with other key players in the ecosystem. Over the past decade, the pattern of DSA patent filings has been quite revealing. Initially, GlobalFoundries and IBM in Upstate New York were early filers. GlobalFoundries ceased their filings around the time they decided not to pursue 7 nm and nodes below. IBM also stopped filing after completing their 2 nm demonstration on 300 mm wafers in 2021. Main contenders Intel and TSMC have been consistently filing DSA patents throughout the hype cycle and have continued to do so. Notably, there has been a clear acceleration in Intel's patent filings since 2019, although there was a slight drop during the COVID-19 lockdowns. Looking at chemical suppliers, Merck has taken the lead, with increased filings beginning in parallel with Intel from 2019 onwards, and accelerating until today. Other suppliers such as JSR, Shin-Etsu, and Brewer Science are also active in the DSA space. In the segment of wafer equipment OEMs, Tokyo Electron and SCREEN have been dominant. However, SCREEN appears to have recently exited the game.

DSA Patent filing last decade (Patbase , 2024-04-19)

In Summary - good assessment by SemiAnalysis and i passes the Patbase Test!

SK hynix to Lead in Advanced DRAM Production, Overtaking Samsung with Earlier Start

Korean SK hynix is set to initiate mass production of its advanced 6th generation 10nm class DRAM (node 1c) in the third quarter of this year, ahead of its competitor Samsung Electronics. The move positions SK hynix to potentially lead in the DDR5 server memory market, which is needed for data centers operated by major tech companies. SK hynix has outlined a strategic internal roadmap that includes achieving necessary customer certifications in anticipation of a surge in demand, especially following compatibility approval with Intel's server platforms. This certification is crucial as Intel holds a dominant share in the global server CPU market. 

The DDR5 DRAM from SK hynix is designed to be compatible with Intel CPUs, a significant advantage given Intel’s extensive market presence. Meanwhile, Samsung plans to start its mass production of similar DRAM by the end of the year, having shared its development roadmap at the recent MemCon 2024 conference. Both companies are using leading-edge Extreme Ultraviolet (EUV) lithography in their processes, which enhances chip yield and power efficiency over previous generations.

SK hynix's new M16 DRAM plant in Icheon, Gyeonggi Province / Courtesy of SK hynix

Source: SK hynix Leads with ‘6th Generation 10 nm’ DRAM Production Ahead of Samsung - Businesskorea

Applied Materials Pioneer® CVD film for EUV Sculpta and DRAM Sym3 Etch applications

Applied Materials continues to lead in semiconductor technology with its introduction of the Producer® XP Pioneer® CVD patterning film at the SPIE Advanced Lithography + Patterning conference. This latest innovation is critical for DRAM scaling and EUV lithography, offering improved etch selectivity and pattern fidelity due to enhanced film density and stiffness. Optimized for use with the Sculpta® pattern-shaping system, Pioneer allows for advanced patterning capabilities, crucial for maintaining precise feature dimensions. With its adoption by leading foundry-logic and memory manufacturers, the Pioneer system is set to significantly enhance Applied Materials' portfolio and revenue, affirming its leadership in CVD technologies.

Applied Materials' Draco™ hard mask and Sym3® Y HT etch system have revolutionized DRAM production by enabling the etching of perfectly cylindrical capacitor holes, significantly enhancing etch selectivity and improving critical dimension uniformity, which contributes to a notable increase in the company's market share in DRAM.

Demand for DRAM innovation continues to grow to feed the insatiable need for memory bandwidth in the AI era. The recently launched Pioneer CVD patterning film has already been adopted by leading memory manufacturers for DRAM patterning. Pioneer is a completely new CVD architecture based on a unique high-density carbon formula that is more resilient to etch chemistries used in the most advanced process nodes, permitting thinner film stacks with superior sidewall feature uniformity.

A thinner hard mask means less vertical distance is required for etch, resulting in a lower aspect ratio. This allows use of lower-power plasma and offers better control of the ratio of ions to radicals. A higher concentration of ions produces more efficient etches with better control, allowing desired patterns to be transferred to the wafer with exceptional fidelity. Pioneer is also being co-optimized with Applied’s new Sym3® Y Magnum® etch system to provide better control over conventional carbon films for critical etch applications in memory processing.

For EUV Lithography the Pioneer CVD patterning film developed by Applied Materials addresses the stringent demands of EUV lithography by increasing film density and stiffness, which enhances etch selectivity and allows for finer pattern control, vital for the ultra-fine dimensions required in advanced chip manufacturing.

Source: Building on an Unmatched Foundation of CVD Innovation (appliedmaterials.com)

Intel Receives ASML's First High-NA EUV Lithography Scanner, Pioneering Next-Gen Semiconductor Manufacturing

ASML has delivered its groundbreaking High-NA EUV lithography scanner, the Twinscan EXE:5000, to Intel Oregon. Marking a significant technological leap, this first-of-its-kind scanner boasts a 0.55 NA lens, enabling 8nm resolution for advanced semiconductor manufacturing. Designed for process technologies beyond 3nm, it promises to enhance chip production efficiency and reduce costs. Intel's early adoption of this state-of-the-art equipment, valued between $300-$400 million, positions them at the forefront of the industry, potentially setting new standards in High-NA manufacturing. This development represents a major milestone in semiconductor technology, signaling a new era of innovation and capability in chip production.

ASML's New Chapter: Navigating Tech Innovation and Geopolitical Shifts Under Christophe Fouquet's Leadership

In an era of significant technological and geopolitical changes, ASML, the number one player in the semiconductor industry, stands at a crossroads. The forthcoming retirement of Martin van den Brink and Peter Wennink, who have jointly steered ASML for over a decade, signals the end of a dynamic period. Van den Brink's leadership in technology development propelled ASML to unparalleled heights in the lithography sector, while Wennink’s diplomatic and financial acumen solidified its market dominance. ASML's impact extends beyond technology; it has become a geopolitical force, enhancing the Netherlands and Europe's strategic significance in global politics.

The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. 

As ASML approaches its 40th anniversary in April 2024, it confronts a changing landscape. The company has weathered various phases – from early struggles to market leadership, marked by innovations like the PAS 5500 and immersion lithography. Under Van den Brink, ASML prioritized technological advancement, often at the expense of other factors like reliability.

The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. The shift in focus from chip performance to system-level advancements requires a nuanced approach. Additionally, as technology matures, reliability and predictability become crucial for maintaining ASML's competitive edge.

The transition from a "firefighter" engineering culture to one emphasizing process and reliability won't be easy. Fouquet must balance innovation with operational efficiency, ensuring ASML remains responsive to market and geopolitical dynamics. This requires a departure from the legacy of Van den Brink, focusing instead on a holistic, structured approach to development and engineering.

Fouquet's tenure will be pivotal in shaping ASML's future. His leadership must navigate the complexities of a highly competitive industry, geopolitical pressures, and the evolving technological landscape. The challenge lies in fostering a culture that values reliability and process without stifling the innovative spirit that has been ASML's hallmark. As the company moves into its fifth decade, its ability to adapt and evolve under Fouquet's guidance will determine its continued success in a rapidly changing world.

Advancing the Microchip Revolution: EUV Lithography's Challenges and Future Outlook

Extreme Ultraviolet (EUV) lithography represents a significant advancement in semiconductor manufacturing, enabling the production of more compact and efficient integrated circuits, particularly for 7 nm Logic process nodes and below and leading edge DRAM. This technology, developed and marketed primarily by ASML Holding, uses a highly specialized process involving laser-pulsed tin droplet plasma to etch patterns onto substrates at the 13.5 nm wavelength scale. The progression from early prototypes to more efficient models has been remarkable, with modern EUV systems capable of handling 200 wafers per hour, a substantial improvement from initial prototypes.

Looking into the future, EUV lithography is expected to play a critical role in advancing semiconductor technology, especially as the demand for smaller and more powerful chips increases. However, several technological challenges need addressing continiously to fully harness EUV's potential:

1. Optical Component Durability: The EUV process requires highly specialized and sensitive optical components, including mirrors and photomasks. These components are prone to degradation from exposure to high-energy photons and contaminants. Improving their durability and developing efficient cleaning and maintenance processes are crucial.

2. Throughput Efficiency: While significant improvements have been made, further enhancing the throughput of EUV systems is vital. This includes reducing setup times, increasing the speed of the lithography process, and minimizing downtime due to maintenance or component replacement.

3. Pattern Fidelity and Defect Reduction: As circuit patterns become increasingly smaller, maintaining pattern fidelity and reducing defects is challenging. This involves improving the resolution of EUV systems, enhancing photoresist materials to better respond to EUV exposure, and developing more effective methods to mitigate the impact of secondary electrons generated during the lithography process.

EUV Lithography - Balancing Technological Advancements with Energy Challenges

EUV lithography, pivotal in advanced semiconductor manufacturing, faces significant energy consumption challenges. The generation of EUV light, typically via laser-pulsed tin plasma, is inherently energy-intensive. Additionally, maintaining the necessary vacuum environment and cooling systems for these high-precision machines further escalates energy use. As EUV technology becomes more prevalent, especially for producing smaller, more efficient chips, optimizing energy efficiency is critical. Future developments are expected to focus on more efficient light sources, improved system design for energy conservation, and advanced thermal management, aiming to reduce the overall energy footprint of EUV lithography processes.

The semiconductor industry, traditionally known for its high environmental impact, is increasingly embracing sustainability. With the global demand for semiconductors rising, manufacturers face the challenge of scaling up production while addressing substantial water and electricity usage and managing hazardous waste from gases used in manufacturing. Historically, the focus has been on balancing power, performance, and cost. Recently, however, sustainability has emerged as a crucial consideration, with many facilities actively working to decarbonize their supply chains and reduce overall environmental impact (data from imec)

EUV Lithography's Hydrogen Demand: A Growing Concern in Chip Manufacturing

EUV Lithography, also raises concerns regarding its significant hydrogen consumption. The EUV process relies heavily on hydrogen gas to maintain the cleanliness of the optical elements, particularly for preventing tin deposition on the mirrors. The need for a continuous supply of hydrogen to facilitate this cleaning process contributes to the overall operational costs and resource demands of EUV systems. As EUV technology becomes more widespread in chip manufacturing, addressing the sustainability and efficiency of hydrogen usage will be essential, both from an environmental and economic perspective.

In EUV lithography, managing hydrogen usage presents distinct challenges. The technology requires hydrogen for removing contaminants from critical mirrors, demanding systems capable of handling high volumes while maintaining vacuum integrity. This necessity places a premium on innovative system designs that minimize the footprint and energy consumption associated with hydrogen management, directly impacting the cost and efficiency of semiconductor manufacturing. Safety considerations, given hydrogen's flammability, are paramount. Advanced, fuel-free hydrogen management strategies are employed to ensure safety and environmental compliance. These strategies focus on reducing flammability risks and eliminating the need for additional fuels, thereby minimizing carbon emissions and contributing to sustainable manufacturing practices.

Continued research and development in these areas are essential for the advancement of EUV lithography, ensuring it meets the rapidly evolving demands of the semiconductor industry.

Sources: 

Christophe Fouquet’s ASML must reinvent itself – Bits&Chips (bits-chips.nl)

www.imec.be

www.edwards.com

Wikipedia

2023 update to IRDS roadmap reminds key EUV issues.

1. EUV dose triples every four nodes => increasing electron blur?
2. EUV cannot replace multiple patterning, even with higher NA.https://t.co/hZzkfKGfyr

— Fred Chen (@DrFrederickChen) December 28, 2023

TechInsights Discovers Micron's Cutting-Edge D1β LPDDR5 16 Gb DRAM Chips in Apple iPhone 15 Pro: Setting a New Standard in Memory Technology

TechInsights has confirmed Micron's cutting-edge D1β LPDDR5 16 Gb DRAM chips in the Apple iPhone 15 Pro, marking the industry's first venture into the D1β generation. These chips are smaller and denser than their predecessors, showcasing significant advancements in DRAM technology. Notably, Micron has achieved this without utilizing Extreme Ultraviolet Lithography (EUVL), a technique employed by competitors like Samsung and SK Hynix for their DRAM processes. This achievement highlights Micron's dedication to pushing the boundaries of DRAM technology, emphasizing innovation and efficiency in the tech landscape. Micron's groundbreaking D1β LPDDR5 16 Gb DRAM chip promises to reshape the future of memory technology, setting a new standard for the industry.

(Source Micron.com)

1-BETA includes cool stuff

High-k/Metal Gate

Micron's 1β fabrication process uses the company's 2nd generation high-K metal gate (HKMG) and is said to increase bit density of a 16Gb memory die by 35% as well as to improve power efficiency by 15% when compared to a similar DRAM device made on the company's 1α node

Pitch multiplication without the need for EUV Lithography

Micron's use of proprietary multi-patterning lithography involves advanced techniques for defining circuit patterns on semiconductor wafers with the highest precision. This approach allows Micron to create intricate patterns on the chips, achieving higher memory capacity in a smaller footprint. It enables the company to fit billions of memory cells on a chip that's roughly the size of a fingernail. 

While the semiconductor industry has been transitioning to extreme ultraviolet lithography (EUVL) to overcome technical challenges in patterning, Micron has opted for its multi-patterning lithography approach. This choice showcases Micron's expertise and innovation in lithography techniques, enabling them to continue shrinking circuit features and achieving greater memory capacity without relying on EUVL, which is still considered an emergent technology. 

By using proprietary multi-patterning lithography, Micron not only reduces the cost per bit of data but also enables devices with small form factors, such as smartphones and IoT devices, to incorporate more memory into compact spaces. This approach underscores Micron's commitment to staying at the forefront of memory technology innovation.

"While the industry has begun to shift to a new tool that uses extreme ultraviolet light to overcome these technical challenges, Micron has tapped into its proven leading-edge nano-manufacturing and lithography prowess to bypass this still emergent technology. Doing so involves applying the company’s proprietary, advanced multi-patterning techniques and immersion capabilities to pattern these minuscule features with the highest precision," Micron explains. Thy Tran, VP Process Integration, Micron

On the heels of the news that Micron has begun shipping QS-sample LPDDR5X components developed on the new 1-beta DRAM process node to its smartphone customers, host Jim Greene welcomes Thy Tran, Vice President of DRAM Process Integration, to the Chips Out Loud Podcast to discuss the emergent technology.

Sources:

Micron LPDDR5 16 Gb Non-EUVL Chip Found in Apple iPhone 15 Pro | TechInsights

LPDRAM | LPDDR | Micron Technology

Micron Ships World’s Most Advanced DRAM Technology With 1-Beta Node | Micron Technology

(Source: TechInsights.com)

ASML's 2023 Outlook: Surging Ahead in Semiconductor Equipment Despite Challenges and Export Controls

In 2023, ASML, the leading semiconductor lithography equipment supplier, is set to achieve remarkable success, outpacing its rivals and emerging as the number 1 provider of Wafer Fabrication Equipment. Boasting an impressive 30% revenue growth forecast for the year, ASML is thriving amidst an industry landscape marked by its consistent performance. With a substantial backlog of cutting-edge Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems and surging demand from China, ASML's growth continues despite hurdles like supply chain disruptions and regulatory changes, ASML remains a beacon of innovation and resilience in the semiconductor sector.

By Abhishek Kumar Thakur and Jonas Sundqvist

ASML, a leading supplier of semiconductor equipment, is poised for a significant year in 2023, projected to surpass Applied Materials (AMAT) as the top provider of Wafer Fabrication Equipment. This achievement is attributed to ASML's robust revenue growth, expected to reach a remarkable 30% increase in 2023, while Applied Materials faces a decline of 20% according to Seeking Alpha*. ASML's success can be attributed to a substantial backlog of Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems, driven by heightened demand in China.

* Fact check: Due to strong DUV revenue and despite the increased uncertainties, ASML expects strong growth for 2023 with a net sales increase towards 30% and a slight improvement in gross margin, relative to 2022. ASML Holding revenue for the twelve months ending June 30, 2023 was $27.293B, a 25.97% increase year-over-year. AMAT revenue is estimated to increase by 2.6% to 26.33 B. Meaning ASML would pass bu end of 2023.

https://finance.yahoo.com/quote/AMAT/analysis/ 

Despite facing challenges like supply chain disruptions and a factory fire, ASML has consistently ranked among the top three semiconductor equipment suppliers since 2017. Their backlog of EUV systems, combined with growing acceptance of DUV tools, contributes to their strong performance.

However, potential headwinds include supply chain concerns, past issues like the Berlin factory fire, and looming sanctions affecting exports to China. While ASML has addressed some challenges, the possibility of US sanctions in 2024 poses a threat to its growth.

Furthermore, ASML now faces new export controls imposed by the Netherlands, impacting shipments to China. While the company downplays these controls' immediate financial impact, they are expected to affect specific DUV systems, adding to global efforts to limit China's semiconductor advancements.

In this volatile landscape, ASML's ability to adapt to evolving regulations and maintain its technological leadership will be crucial. The impact of these restrictions, especially on shipments to China, could influence the company's growth trajectory in the semiconductor industry. Despite these challenges, ASML remains a prominent player with significant potential in the semiconductor equipment market.

ASML is set to deliver the industry's first High-NA extreme ultraviolet (EUV) lithography scanner by the end of 2023, marking a significant development for advanced chip manufacturing. The Twinscan EXE:5000 pilot scanner with a 0.55 numerical aperture (NA) will enable chipmakers to explore High-NA EUV technology. This innovation is crucial for achieving an 8nm resolution, suitable for manufacturing technologies beyond 5nm nodes. Intel is expected to be the first customer, but integration and adoption details are still uncertain. This advancement requires substantial investments, with reports suggesting costs of $300-400 million per unit.

To add some colour, initially, Intel had plans to employ ASML's High-NA tools for its 18A (1.8 nm) production node, scheduled for high-volume manufacturing in 2025, aligning with ASML's Twinscan EXE:5200 delivery. However, Intel accelerated its 18A production, moving it to the latter part of 2024. This change in strategy involved the use of ASML's Twinscan NXE:3600D/3800E with two exposures and Applied Material's Endura Sculpta pattern-shaping system. The objective was to reduce reliance on EUV double patterning techniques. Applied Materials' Centura Sculpta is a pattern-shaping machine equipped with a unique algorithm that can manipulate patterns produced by an EUV scanner. It has the capability to stretch these patterns in a user-defined direction along the X-axis. This process effectively reduces the space between features and enhances pattern density. This means that moving ahead ASML and Applied Materials are entering an interesting competitive space previously not encountered.

ASMLs Products

As an background, ASML specializes in the production of cutting-edge lithography systems crucial for semiconductor manufacturing. Their product portfolio includes the following key offerings:

Extreme Ultraviolet (EUV) Lithography Machines: ASML's EUV lithography machines are at the forefront of semiconductor manufacturing technology. These machines use extremely short wavelengths of light to create intricate patterns on silicon wafers, enabling the production of advanced and smaller semiconductor chips. EUV technology is essential for next-generation processors and memory chips.

Deep Ultraviolet (DUV) Lithography Machines: DUV lithography systems are another vital component of ASML's product lineup. They use longer wavelengths of light compared to EUV and are employed for a wide range of semiconductor applications, including memory and logic chip production. ASML's DUV systems are known for their precision and reliability.

TWINSCAN Series: Within the DUV lithography category, ASML offers the TWINSCAN series, which includes machines like the TWINSCAN NXT:2000i, NXT:2050i, and NXT:2100i. These systems are designed for immersion lithography, where the wafer and the lens are submerged in a liquid, enhancing precision and resolution.

EUV High Numerical Aperture (NA) Systems: ASML has been advancing its lithography machines by increasing the numerical aperture (NA), a key parameter that affects resolution. High-NA systems are capable of printing even smaller features on semiconductor wafers, enabling the production of highly advanced chips.

ASML's lithography machines are considered critical infrastructure for semiconductor manufacturing, and the company's technological leadership in this area has positioned it as a dominant player in the industry. The company's ability to innovate and adapt its lithography systems to meet the ever-increasing demands of semiconductor manufacturers has been a key factor in its success and growth prospects. However, the recent export controls and geopolitical pressures, particularly concerning shipments to China, introduce additional challenges and uncertainties for ASML and its specialized products.

Sources:

ASML Hit With New Dutch Limits on Chip Gear Exports to China - Bloomberg

ASML To Top WFE Semiconductor Equipment In 2023, Topping Applied Materials | Seeking Alpha

ASML to ship first pilot tool in its next product line in 2023, CEO says | Reuters

ASML to Deliver First High-NA EUV Tool This Year (anandtech.com)

EUV Alternative Speeds Up Chip Production - EE Times

BALD Engineering - Born in Finland, Born to ALD: ASML Remains on Track to Deliver High NA EUV Machines in 2023

BALD Engineering - Born in Finland, Born to ALD: Netherlands' chip tool export controls take effect for DUV Lithography and ALD

BALD Engineering - Born in Finland, Born to ALD: Applied Materials’ Pattern-Shaping Technology - Centura Sculpta

ASML Remains on Track to Deliver High NA EUV Machines in 2023

ASML, the leading semiconductor equipment manufacturer, is set to ship the first pilot tool from its next product line in 2023, despite some supplier delays, according to CEO Peter Wennink. These High NA EUV machines, crucial for top chipmakers to create smaller and better chips in the coming decade, will cost over $300 million euros each and provide up to 70% better resolution. ASML currently dominates the lithography market, a pivotal step in chipmaking, and is seeing strong demand for its older DUV machines, with 30% sales growth forecasted in 2023, primarily driven by Chinese customers.

ASML's High NA EUV machines are used by a range of prominent semiconductor manufacturers, including TSMC, Intel, Samsung, SK Hynix, and Micron. These chipmakers rely on ASML's cutting-edge lithography equipment to manufacture semiconductor chips, from microprocessors to memory chips.

"High NA" stands for "High Numerical Aperture." Numerical Aperture (NA) is a measure of the ability of an optical system, such as a lens or mirror, to gather and focus light. A higher numerical aperture indicates a greater ability to capture light and provide finer detail and resolution in imaging or lithography processes. ASML's High NA EUV machines, are designed to gather light from a wider angle compared to their previous generation tools. This wider angle collection of light allows for significantly improved resolution in the semiconductor manufacturing process, making it possible to create smaller and more advanced semiconductor chips with greater precision required for the Ångström Era - basically the sub 2 nm nodes.

Source:

ASML to ship first pilot tool in its next product line in 2023 -CEO | Reuters

TSMC Marks Major Milestone: First EUV Machine Installed in Arizona Fab, Job Opportunities Open

Taiwan Semiconductor Manufacturing Co. (TSMC) has achieved a significant milestone in its Arizona manufacturing venture by installing its inaugural extreme ultraviolet lithography (EUV) machine. This advanced machine, procured from Dutch semiconductor equipment leader ASML Holding NV, is a pivotal asset for TSMC's future high-end chip production endeavors.

EUV technology is a critical aspect of semiconductor fabrication, facilitating the printing of intricate designs on microchips significantly smaller than a human hair. TSMC's achievement underscores its commitment to innovation and technological leadership.

While the installation of the EUV machine marks a remarkable accomplishment, TSMC acknowledges that the setup of the new fab in Arizona involves numerous additional tasks. The company emphasized the need for approximately 2,000 skilled workers to handle the installation of various equipment pieces and services in the complex. This requirement stems from TSMC's unique tool configurations and specifications.

TSMC, recognized as the world's largest contract chip manufacturer, is channeling substantial investments amounting to $40 billion into constructing two wafer fabs in Phoenix. The first facility will employ the advanced 4-nanometer process, while the second, already under construction, will utilize the more sophisticated 3-nanometer process. This latter technology has already entered mass production in Taiwan.

The presence of skilled workers has been a contentious topic linked to the Arizona project. TSMC Chairman Mark Liu explained that a deficiency in experts capable of properly installing equipment at the Arizona site has led to a delay in mass production, now projected for 2025 rather than late 2024.

However, TSMC's approach to addressing this shortfall has sparked debates. The company's bid to bring in around 500 Taiwanese workers on temporary E-2 visas has faced resistance from local unions, who assert that prioritizing American jobs is paramount, especially considering the significant subsidies TSMC seeks under the CHIPS and Science Act. This legislation, signed by President Joe Biden, encourages semiconductor investments in the United States.

US Senator Mark Kelly of Arizona emphasized that the visa applications will be evaluated in accordance with established laws and procedures. As TSMC navigates these challenges, its progress in Arizona remains a focal point in the semiconductor industry's dynamic landscape.

TSMC installs first EUV machine in U.S.; job opening ads posted - Focus Taiwan

An Update on Directed Self-Assembly (DSA) for Advancing Micro and Nano Fabrication

Revolutionizing fabrication, Directed Self-Assembly (DSA) innovates micro to nano devices and materials. It leverages block co-polymer morphology for precise patterns and guides micro/nano particles, enhancing manufacturing. In semiconductors, DSA addresses lithography challenges, while Imec's research showcases DSA-EUV synergy for defect-free outcomes. Complex rectification processes, illustrated by Imec, spotlight improved Critical Dimension Uniformity and Pattern Placement Error control. As DSA advances, its collaboration with EUV promises precision, efficiency, and innovation across industries.

DSA has emerged as a groundbreaking technique for mass-producing micro to nano devices and materials with precision and efficiency. This method harnesses the inherent properties of materials to assemble them into intricate structures, revolutionizing manufacturing processes across various industries.

DSA leverages block co-polymer morphology to create patterns, enhancing feature control and shape accuracy. This involves guiding the assembly of micro and nano particles to achieve desired structures, made possible by the precise control of surface interactions and polymer thermodynamics. The key advantage of DSA is its ability to create structures at remarkably small scales, enabling advancements in diverse fields.

In the semiconductor industry, DSA offers a new perspective on lithography challenges. Despite initial setbacks, DSA is being revisited to address critical issues such as stochastic defects in extreme ultraviolet (EUV) lithography. These defects, which can contribute significantly to patterning errors, have led semiconductor manufacturers to explore DSA as a solution to rectify these problems. Notably, DSA is not replacing traditional methods but rather enhancing them. It is being integrated with existing manufacturing processes to enable increased resolution and precision, all while reducing costs.

However, challenges persist in integrating DSA into high-volume manufacturing. Defect control remains a primary concern, as the technology strives to meet industry standards of minimal defectivity. Common defects include line bridging, collapse, bubbles, and dislocations. Efforts are ongoing to optimize annealing temperature, etching methods, and film thickness to reduce these defects. Another challenge is the complexity of pattern inspection, which demands accurate metrology methods. Researchers are exploring machine learning-based approaches to automate the inspection process and achieve higher throughput.

Despite these challenges, DSA is being applied to various applications beyond semiconductors. Tissue engineering benefits from the precision of directed assembly, enabling the controlled organization of cells into desired micro-structures. In nanotechnology, DSA facilitates the creation of precise nanostructures, leading to advancements in areas such as graphene nanoribbon arrays and thin-film quantum materials.

Revolutionizing EUV Lithography with Directed Self-Assembly (DSA)

EUV lithography has revolutionized semiconductor manufacturing but comes with its share of challenges, particularly in addressing line roughness and stochastic defects. DSA has now gained attention as a potential game-changer to tackle these issues in EUV lithography.

Recent research from Imec sheds light on the promising synergy between EUV and DSA in overcoming lithography challenges. In the study titled "EUV Lithography Line Space Pattern Rectification Using Block Copolymer Directed Self-Assembly: A Roughness and Defectivity Study," led by Julie Van Bel and team, the researchers explored the combination of DSA with EUV. Their findings indicate that this integration surpasses DSA processes based on Immersion lithography, offering lower line width roughness and freedom from dislocation defects.

Another study, "Mitigating Stochastics in EUV Lithography by Directed Self-Assembly," led by Lander Verstraete and collaborators, delved into the application of DSA to mitigate stochastic defects in EUV processing.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in Figures below. In the top Figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using DSA. Meanwhile, the lower Figure details the rectification process for defects in EUV Contact Patterns.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in the figures below. In the top figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using Directed Self-Assembly (DSA). Meanwhile, the lower figure details the rectification process for defects in EUV Contact Patterns. These illustrations highlight the potential of DSA in enhancing lithographic precision, addressing challenges related to line roughness and stochastic defects, and achieving improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error control in semiconductor manufacturing.

The results are particularly promising for line/spaces at a 28nm pitch, primarily addressing bridge defects. However, at a 24nm pitch, further improvement is necessary due to an excess of bridge defects. Notably, the type and frequency of defects correlate with the formulation of the block copolymer and the duration of the annealing process.

For contact arrays, the combination of EUV and DSA demonstrates improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error. This advancement also enables the use of a lower dose, contributing to enhanced precision and efficiency in semiconductor manufacturing.

Imec's research underscores the potential of DSA to revolutionize EUV lithography by addressing line roughness and stochastic defects. The successful integration of EUV and DSA holds the promise of enhancing semiconductor manufacturing processes, achieving higher precision, and enabling the production of advanced devices with improved quality. As researchers continue to refine these methods, the collaboration between EUV and DSA is set to shape the future of lithography and microfabrication.

In conclusion, DSA is revitalizing micro and nano fabrication by offering accurate and efficient methods for mass production. While challenges like defect control and metrology persist, DSA's potential to shape the future of industries such as semiconductors, biomedicine, and nanotechnology is undeniable. As research continues to refine DSA processes and overcome hurdles, its role in advancing technology and innovation is set to expand further.

Directed Self-Assembly Finds Its Footing (semiengineering.com)

SPIE 2023 – imec Preparing for High-NA EUV - SemiWiki

Directed assembly of micro- and nano-structures - Wikipedia

U.S. and Netherlands Tighten Restrictions on Chipmaking Equipment Sales to China, Impacting ALD and ASM International

The United States and the Netherlands are set to impose stricter restrictions on the sale of chipmaking equipment to China, aiming to prevent the use of foreign technology for military strengthening. In their efforts to curb China's access to advanced semiconductor technology, the Dutch government plans to restrict equipment from ASML, the leading chip equipment maker in the Netherlands, while the U.S. plans to further withhold Dutch equipment from specific Chinese fabs. These measures will impact atomic layer deposition (ALD) firm ASM International as well.

Besides ASM and Lithography, ASM International and ALD is of national interest to The Netherlands. During the recent Royal State Visit of King Willem-Alexander and Queen Máxima of the Netherlands to imec, ASM, a long-standing partner of imec, was in attendance. With over 30 years of partnership, ASM has made significant investments in research and development and maintains a substantial on-site team at imec known in the industry as ASM B or ASM Belgium. During the visit, ASM had the opportunity to highlight its role in the semiconductor ecosystem of both the Netherlands and Belgium, emphasizing how this collaboration connects Europe to advanced semiconductor manufacturing activities on a global scale. (Source: ASM LinkedIn)

ASML, Europe's largest chip equipment company, dominates in lithography, a crucial step in the chip manufacturing process. The Dutch government intends to announce new regulations, including a licensing requirement, for ASML's deep ultraviolet (DUV) semiconductor equipment. ASML's more sophisticated extreme ultraviolet (EUV) lithography machines are already restricted and have never been shipped to China. The U.S. is expected to identify specific Chinese facilities, possibly including those operated by SMIC, China's largest chipmaker, in a new rule that restricts foreign equipment containing any U.S. parts. ASM International, an ALD firm, is also likely to be impacted by the new Dutch regulations.

The U.S. and Dutch measures aim to prevent China from gaining access to advanced chipmaking technology that could be used for military purposes. These actions reflect the ongoing tensions between the U.S. and China regarding national security concerns and technological competition. While the exact details and timing of the restrictions may change, the increasing limitations on chipmaking equipment sales are expected to have significant implications for the global semiconductor industry and the supply chain dynamics in the coming months.

Sources:

US, Dutch set to hit China's chipmakers with one-two punch | Daily Mail Online

State visit to Belgium – programme | News item | Royal House of the Netherlands (royal-house.nl)

EUV Lithography Embraces Sustainability with Hydrogen Recycling System

Edwards Vacuum and Imec Develop Reverse Fuel Cell to Recycle Contaminated Hydrogen in Chip Manufacturing

The semiconductor industry relies heavily on extreme ultraviolet (EUV) lithography systems to increase transistor density. These systems use large amounts of hydrogen to sweep away contaminants and maintain the cleanliness of their optics. Currently, the contaminated hydrogen is burned to form water, requiring a constant supply of new hydrogen. However, this process contributes to carbon emissions as most hydrogen is produced from natural gas using steam processing.

“It’s similar to a fuel cell, in reverse.”—Anthony Keen, Edwards Vacuum

To address this issue, engineers at Edwards, a vacuum systems firm based in England, have developed a hydrogen recovery system that can recycle up to 80 percent of the gas. The system functions similarly to a fuel cell but in reverse. The contaminated hydrogen is mixed with moisture and nitrogen, ionized, and then forced through a proton-exchange membrane using an electric field. On the other side of the membrane, the protons recombine with electrons to form pure hydrogen, while contaminants and water remain on the other side and can be disposed of properly. The recovered hydrogen can then be sent back to the EUV lithography system.

Edwards collaborated with Imec, a research and innovation hub for nanoelectronics and digital technologies, to test the recovery system. The tests conducted on Imec's silicon pilot line demonstrated that the system recovered 70 to 80 percent of the hydrogen and resulted in a net reduction in energy consumption.

The implementation of this hydrogen recovery system in the semiconductor industry could help lower the environmental footprint of EUV lithography systems and contribute to reducing the carbon emissions associated with chip manufacturing. The semiconductor industry has been striving to reduce its carbon footprint, with estimates suggesting it could account for 3 percent of global emissions by 2040. Edwards will need to make a case to top chipmakers, such as Intel, Samsung, and TSMC, to adopt this green technology and further promote sustainability in chip production.

Sources: 

The Semiconductor Industry’s Most Important Tool Goes Green - IEEE Spectrum

Edwards - Edwards Vacuum

TechInsights found Samsung DRAM chips in Samsung Galaxy S23 with Five EUV mask layers

TechInsights found Samsung DRAM chips in Samsung Galaxy S23 with Five EUV mask layers. These are from DRAM wafers produced in the so-called D1a node (or D1α, α as in alpha)

👉https://t.co/oSv4yiHJiB
Get your products to market faster: @TechInsightsinc found next-gen #DRAM found in the #GalaxyS23. @Samsung is the first company to apply five #EUV lithography masks on DRAM D1a, the first node to fully adopt EUVL for #DRAM. Learn more. #semiconductor pic.twitter.com/2Pqg7gKuE9

— TechInsights (@techinsightsinc) May 1, 2023

This is in line with a previous press release from Samsung (2020) so no real surprise here: Samsung Announces Industry’s First EUV DRAM with Shipment of First Million Modules – Samsung Global Newsroom

"EUV to be fully deployed from 4th-gen 10nm-class DRAM (D1a) next year"

EUV will be fully deployed in Samsung’s future generations of DRAM, starting with its fourth-generation 10nm-class (D1a) or the highly-advanced 14nm-class, DRAM. Samsung expects to begin volume production of D1a-based DDR5 and LPDDR5 next year, which would double manufacturing productivity of the 12-inch D1x wafers.

 

Applied Materials’ Pattern-Shaping Technology - Centura Sculpta

Applied Materials’ pattern-shaping technology is a breakthrough innovation that brings new capabilities to the patterning engineer's toolkit. This animation shows how engineers can replace EUV double patterning steps with the Centura® Sculpta® patterning system to reduce the cost, complexity and environmental impact of leading-edge chipmaking.

Applied Materials showcased a patterning technology that helped chipmakers to create high-performance transistors and interconnect wiring with fewer EUV lithography steps, thereby lowering the cost, complexity, and environmental impact of advanced chipmaking. To help chipmakers shrink designs without the added cost, complexity, and energy and materials consumption of EUV double patterning, Applied Materials worked closely with leading customers to develop the Centura Sculpta patterning system.

Chipmakers such as Intel, Samsung and TSMC, can now print a single EUV pattern and then use the Sculpta system to elongate the shapes in any chosen direction to reduce the space between features and increase pattern density. The Sculpta system can provide chipmakers with capital cost savings of $250 million per 100K wafer starts per month of production capacity, manufacturing cost savings of $50 per wafer, and energy savings of more than 15 kWh per wafer, the company said.

Ryan Russell, corporate vice president for logic technology development at Intel Corp, said, "Having collaborated closely with Applied Materials in the optimization of Sculpta around our process architecture, Intel will be deploying pattern-shaping capabilities to help us deliver reduced design and manufacturing costs, process cycle times and environmental impact."

Applied Materials Centura with four Sculpta chambers

Applied Materials also launched a new eBeam metrology system specifically designed to precisely measure the critical dimensions of semiconductor device features patterned with EUV and emerging High-NA EUV lithography. Applied's new VeritySEM 10 system features a unique architecture that enables low-landing energy at 2X better resolution than conventional CD-SEMs. It also provides a 30% faster scan rate to reduce interaction with the photoresist and increase throughput​.

• Directed ribbon-beam capability for novel etching applications

Journal of Vacuum Science & Technology B 33, 06FA02 (2015); https://doi.org/10.1116/1.4932161

Comparison confirms that SMIC reaches 7nm without access to western equipment & technologies

Similarities with TSMC 7nm have been found

After TechInsights revealed their initial findings on the SMIC MinerVa Bitcoin mining processor, their team did further analysis and comparison against TSMC 7nm. This new analysis confirms that despite current sanctions restricting access to the most advanced equipment technologies, Chinese Semiconductor Manufacturing International Corporation (SMIC) has used 7nm technology to manufacture the MinerVa Bitcoin Miner application-specific integrated circuit (ASIC).

The TechInsights analysis also uncovered many similarities between the SMIC 7nm and the TSMC 7nm, which are available in our comparison brief.

Source: SMIC 7nm is truly 7nm technology, how it compares to TSMC 7nm | TechInsights

According to the SeekingAlpha assessment earlier this year (Applied Materials: SMIC Move To 7nm Node Capability Another Headwind (NASDAQ:AMAT) | Seeking Alpha) SMIC is using a large amount of multiple pattering mask layers like in the first TSMC and Samsung 7 nm nodes (N7). 

"At 7nm, normally 15 DUV systems and 5 EUV systems are demanded, depending on chip type and company. However, since SMIC is not permitted to use EUV, then they will be substituted by DUV, and 20 DUV systems will be used.

In both cases, multiple patterning is done to delineate that pattern, whether it is 28nm or 7nm. This multiple patterning process is more or less a trick to reach even the 28nm dimensions. The multiple patterning is typically a combination of deposition, etch, and lithography steps.

If we look at Chart 3 below, using immersion DUV (ArF-1) at the 20nm node there are 13 mask layers, each of which uses multiple dep-etch steps. If we move across the top of the chart, at 10nm there are 18 mask layers, an increase of 50% in the use of deposition-etch steps.

Multiple patterning at the 7nm node, as shown in the bottom left of the chart, requires 27 mask layers. However, by switching to EUV (bottom right) at 7nm, only 14 mask layers are required, similar to the 20nm node with DUV.

The terminology is as follows in switching from DUV to EUV:Double litho, double etch (LELE) process will be eliminated

While ArF-I would continue to be used for the self-aligned double patterning (SADP) and

Self-aligned quadruple patterning (SAQP) processes."

 

Table from SeekingAlpha as cited above

From an ALD point of view, the FEOL and metallization up to M2 use 19 in the case of Immersion Lithography (N7) vs 10 in the case of EUV (N7+) ALD spacer-defined multiple patterning masks (SADP or SAQP). However, the bigger difference is in etch for LELE etc., where EUV N7+ uses only 2 such masks.

Lam Research, Entegris, Gelest Team Up to Advance EUV Dry Resist Technology Ecosystem

Collaboration provides robust chemical supply chain for global chipmakers using the breakthrough technology and supports R&D for next-generation EUV applications

SEMICON WEST 2022, SAN FRANCISCO, July 12, 2022 – Lam Research Corp. (NASDAQ: LRCX), Entegris, Inc. (NASDAQ: ENTG), and Gelest, Inc, a Mitsubishi Chemical Group company, today announced a strategic collaboration that will provide semiconductor manufacturers worldwide with reliable access to precursor chemicals for Lam’s breakthrough dry photoresist technology for extreme ultraviolet (EUV) lithography, an innovative approach used in the production of next-generation semiconductors. The parties will work together on EUV dry resist technology research and development (R&D) for future device generations of logic and DRAM products that will help enable everything from machine learning and artificial intelligence to mobile devices.

A robust supply chain for process chemicals is critical to EUV dry resist technology integration into high-volume manufacturing. This new long-term collaboration further broadens the growing ecosystem for dry resist technology and will provide dual-source supply from semiconductor material leaders with provisions for continuity of delivery in all global markets.

LAM is a semiconductor processing and fabrication equipment designer and manufacturer who has announced a new dry photoresist technology in collaboration with IMEC and ASML. This new dry technology differs from the wet photoresist currently used in all commercial semiconductor foundries such as TSMC, Intel, Samsung, Micron, Global Foundries and SK Hynix. (source: SemiAnalysis LINK)

These stochastic defects lead to a variety of issues with the future 3nm/2nm nodes. One of these issues that can be mitigated by moving to dry deposit and develop is line collapse. When the solvent is washed away, the lines can become unstable and collapse. Other issues such as line edge roughness are also mitigated when moving to a dry deposit and develop flow. (source: SemiAnalysis LINK)

In addition, Lam, Entegris, and Gelest will work together to accelerate the development of future cost-effective EUV dry resist solutions for high numerical aperture (high-NA) EUV patterning. High-NA EUV is widely seen as the patterning technology that will be required for continued device scaling and advancement of semiconductor technology over the coming decades. Dry resist provides the high etch resistance and tunable thickness scaling of deposition and development necessary to support high-NA EUV's reduced depth of focus requirements. "Dry resist technology is a breakthrough that shatters the biggest barriers to scaling to future DRAM nodes and logic with EUV lithography," said Rick Gottscho, executive vice president and chief technology officer of Lam Research. "This collaboration brings together Lam's dry resist expertise and cutting-edge solutions with material science capabilities and trusted supply channels from two industry precursor chemical leaders. This important expansion of the dry resist ecosystem paves the way for exciting new levels of innovation and high-volume manufacturing with the technology." First developed by Lam in collaboration with ASML and IMEC, dry resist extends the resolution, productivity, and yield of EUV lithography, thereby addressing key challenges associated with creation of next-generation DRAM and logic technologies. It provides superior dose-to-size and dose-todefectivity performance, enabling higher EUV scanner productivity and lower cost of ownership. In addition, Lam's dry resist process offers key sustainability benefits by consuming less energy and five to ten times less raw materials than traditional resist processes. "Lam's dry resist approach reflects key innovations at the material level and offers a wide range of advantages, including better resolution, improved cost-efficiency and compelling sustainability benefits," said Bertrand Loy, chief executive officer of Entegris. "We are proud to be a part of this innovative collaboration to accelerate dry resist adoption and to be a trusted process materials supplier for customers as they push to create the next generation of semiconductors with this important technology." "Our collaboration with Lam and Entegris to advance dry resists for EUV lithography demonstrates our commitment to support chipmakers as they innovate in materials science," said Jonathan Goff, president of Gelest, a Mitsubishi Chemical Group company. "We've seen EUV demonstrate exceptional value in recent years, and we're pleased to be part of the growing ecosystem to extend its potential."

The US Patent Office has approved AlixLabs’ patent application for nanofabrication by ALE Pitch Splitting (APS)

(30 April 2021, Lund Sweden). The US Patent Office has approved AlixLabs’ (AlixLabs AB) patent application for nanofabrication by ALE Pitch Splitting (APS).

The US Patent Office has issued a patent (US10930515) on February 23, 2021. The patent covers methods to split nanostructures in half by a single process step using Atomic Layer Etching (ALE). The method has the potential to have a big impact on the semiconductor industry by enabling sustainable scaling of electronic components and shrink chip designs further in a cost-effective way. The method is complementary for single exposure Immersion and Extreme UV (EUV) Lithography and corresponding multiple patterning technologies like self-aligned double and quadruple patterning (SADP resp. SAQP) as well as directed self-assembly (DSA).

In direct comparison to mentioned more complicated and expensive methods, APS may cut the need for certain fab equipment investments considerably, reduce manufacturing cost and energy consumption as well as reduce greenhouse gas emission during the patterning processing by up to 50%, allowing greener and affordable way forward for the semiconductor industry.

AlixLabs aims at applications for the manufacturing of leading-edge sub 5nm Logic Devices and Memory Chips that are used for everyday consumer electronic devices, 5G and AI.

The company’s CEO Dr. Jonas Sundqvist comments:

After founding the company in 2019 we now move into very exciting times. The team has been expanded with Dr. Mohammad Karimi as Principal Scientist and we have several applications and projects in the pipeline for broadening our patent protection and creating further opportunities for commercial agreements starting now. Currently, we are taking on the first round of private investments and will expand operations for both core activities in Lund, Sweden, at NanoLund and Lund Nano Lab, and the IDEON Science Park in Sweden. In addition, we are heading to the heart of the European semiconductor industry in Dresden Germany for a lab to fab transfer to 300 mm silicon wafer process verification to get ready for customer demonstrations of APS.

The company’s CTO Dr. Dmitry Suyatin comments:

This patent is built on a surprising discovery by the inventors, which took place at Lund Nano Lab during the Master project by Dr. Sabbir A. Khan who has recently received his PhD from the University of Copenhagen and now continues his postdoctoral work at Niels Bohr Institute in Copenhagen.

About AlixLabs AB:

AlixLabs (www.alixlabs.com) is an innovative startup enabling the semiconductor industry to scale down Logic and Memory components in a cost-effective manner by the use of ALE Pitch Splitting (APS).

Background Information:

Lund Nano Lab: https://www.nano.lu.se/facilities/lund-nano-lab

IDEON Science Park: https://www.ideoninnovation.se/our-startups

Picture: