Showing posts with label EUV. Show all posts
Showing posts with label EUV. Show all posts

Friday, February 7, 2025

JSR Expands Global Semiconductor Material Capabilities with New Photoresist Facilities, Advanced MOR Variants, and Strategic Acquisition of CVD/ALD Precursor Firm

JSR Corporation is expanding its global development and production of advanced photoresists by establishing a new R&D center in Japan and constructing a semiconductor photoresist plant in Korea. Since acquiring Inpria Corporation in 2021, JSR has been commercializing Metal Oxide Resist (MOR) for EUV lithography. The new R&D center in Japan’s Kanto region will enhance collaboration with global customers and partners, while the Korean plant, expected to begin operations in 2026, will handle the final production process for MOR to support local adoption. JSR aims to drive innovation in photoresists and help customers establish commercial production processes worldwide.

JSR's MOR, developed through its 2021 acquisition of Inpria Corporation, is a next-generation photoresist designed for EUV lithography. MOR is based on metal oxide nanoparticles, offering superior etch resistance and improved pattern resolution compared to traditional chemically amplified resists (CARs). This allows for finer feature definition and reduced line-edge roughness, critical for advanced semiconductor manufacturing below 10 nm. JSR has been scaling MOR for commercial adoption, with major semiconductor manufacturers evaluating its use in high-volume production. The company is expanding its R&D and manufacturing capacity, including a new R&D center in Japan and a production facility in Korea, to support global adoption of MOR.



JSR have investigated different flavors of MOR for EUV lithography, primarily focusing on variations in metal cores and process optimizations. Initially, zirconium (Zr) and hafnium (Hf) based MORs were explored, but their relatively low EUV absorption led researchers to investigate alternative metal cores such as titanium (Ti), zinc (Zn), indium (In), and tin (Sn). These new metal cores exhibited improved lithographic performance, achieving higher EUV absorption, smaller particle size, and better scum reduction. Additionally, process optimizations such as using higher dissolution rate photoacid generators (PAGs), new organic solvent developers, and lower soft bake temperatures were tested to improve scum removal and resolution. The new metal core variants demonstrated resolutions down to 13 nm with reduced defects, suggesting their potential for advanced semiconductor manufacturing.

In August 2024, JSR Corporation completed the acquisition of Yamanaka Hutech Corporation (YHC), a Kyoto-based manufacturer specializing in high-purity chemicals for semiconductor manufacturing. This strategic move allows JSR to expand its product portfolio to include Chemical Vapor Deposition (CVD) and Atomic Layer Deposition (ALD) precursors, which are essential for forming advanced and complex semiconductor device structures. YHC, established in 1960, has over 60 years of experience in advanced molecular design, synthesis technology, and quality control systems, supplying high-quality CVD/ALD precursors to leading-edge semiconductor device manufacturers. The acquisition aligns with JSR's strategy to strengthen its position as a global supplier of semiconductor materials, enhancing its capabilities in both miniaturization and device structure innovation.

Sources:

JSR Expands Global Development and Production Functions for Leading-Edge Photoresists | 2024 | News | JSR Corporation

tec125-4.pdf

Thursday, January 30, 2025

Lam Research’s Dry Resist: A Breakthrough in EUV Lithography for Next-Generation Logic and Memory Manufacturing

Lam Research’s dry resist technology represents a major shift in EUV lithography and semiconductor patterning, addressing critical challenges such as stochastic defectivity, resolution limitations, and cost-efficiency. With recent qualifications for advanced DRAM and 2nm logic manufacturing, along with a growing ecosystem for high-volume production, dry resist is positioned to disrupt traditional chemically amplified resists (CARs) and enable future High-NA EUV adoption.

One of the most significant recent developments is Lam’s qualification of dry resist for 28nm pitch BEOL logic at 2nm and below in collaboration with imec. This qualification confirms that dry resist can eliminate multi-patterning steps, reducing complexity and improving EUV throughput. The process is designed to work with both low-NA and high-NA EUV scanners, ensuring its relevance for sub-2nm logic scaling. This represents a key milestone in extending direct EUV printing to future logic nodes, an approach that could significantly lower lithography costs while improving pattern fidelity.


In addition, a leading DRAM manufacturer has selected Lam’s Aether dry resist technology as its production tool of record for advanced DRAM nodes. This decision highlights dry resist’s low-defect, high-fidelity patterning capabilities, which are essential for scaling memory architectures. The technology enables lower exposure doses while reducing stochastic defects, which are a major concern in EUV-based DRAM production. Given that Samsung, SK Hynix, and Micron are all increasing their reliance on EUV for next-generation DRAM, Lam’s dry resist is well-positioned for widespread adoption in the memory sector.


To ensure a stable supply chain for dry resist materials, Lam Research has partnered with Entegris and Gelest, a Mitsubishi Chemical Group company. This collaboration ensures reliable dual-source precursor production, providing chipmakers with long-term process stability. The partnership also focuses on the development of next-generation high-NA EUV precursors, further strengthening dry resist’s role in future sub-2nm manufacturing.


SEM images of 28 nm pitch line/space patterns imaged with 0.33NA EUV in dry resist from Entegris precursor.

A critical enabler of dry resist technology is its atomic layer deposition (ALD) process, which replaces traditional spin-coating used in CARs. ALD-based vapor-phase deposition offers higher uniformity, eliminating polymer chain variations found in conventional resists. It also allows precise thickness control, which is essential for optimizing EUV photon absorption and etch selectivity. Unlike CARs, which rely on a complex mixture of polymers, dry resist materials are based on single-component metal-organic precursors such as organo-tin oxides. These materials provide higher EUV photon absorption, improving sensitivity and pattern resolution.

Another key advantage of dry resist is its anisotropic dry development process, which replaces wet solvent-based development. Traditional CAR-based EUV resists require organic solvents or aqueous bases, leading to stochastic defects, material loss, and waste. Dry resist, by contrast, is developed entirely in the gas phase, selectively removing unexposed regions and forming a negative-tone image. This eliminates line collapse and delamination issues, improving yield stability. Additionally, the elimination of wet chemistries significantly reduces chemical waste, making dry resist a more sustainable solution with five to ten times lower material consumption compared to traditional resists.

Lam’s dry resist technology is poised to disrupt traditional CAR-based EUV lithography, particularly as the industry moves toward High-NA EUV adoption. By reducing multi-patterning dependency, the technology enhances cost-effective EUV scaling, making it an attractive solution for both logic and memory manufacturers. This positions Lam as a key leader in next-generation EUV resist solutions, challenging conventional resist suppliers like JSR, TOK, and Inpria.

From a sustainability perspective, dry resist significantly lowers EUV exposure dose requirements, leading to higher scanner throughput and lower energy consumption. Its reduced defectivity translates to higher yield per wafer, further enhancing cost-efficiency. The collaboration with Entegris and Gelest ensures supply-chain stability, making dry resist a viable and scalable technology for sub-2nm nodes.

The patent US20220020584A1 mentions several Lam Research tools that play a role in the dry resist deposition, patterning, and development process for EUV lithography. The Altus system is referenced for deposition, likely for metal or dielectric films in the dry resist stack, while the Striker plasma-enhanced atomic layer deposition (PEALD) system may be used for precise resist or underlayer deposition. The Versys platform, known for plasma processing, is relevant to the dry development process, and the Syndion system, typically used for deep silicon etching, may have applications in pattern transfer. Additionally, the Reliant tool is designed for volume manufacturing, possibly adapted for integrating dry resist technology, and the Kiyo plasma etch system is likely involved in etching after the dry resist development stage. These tools collectively enable Lam’s dry resist process to achieve improved resolution, defect reduction, and cost efficiency in advanced EUV lithography.

The patent US20220020584A1, filed by Lam Research Corporation, describes an innovative dry development process for EUV photoresists, which eliminates the need for traditional wet chemical development methods. The patent details a dry resist system deposited via vapor-phase precursors, forming a highly uniform, single-component material that enhances EUV photon absorption and sensitivity. The dry development process selectively removes unexposed resist regions using plasma-based or plasma-free chemical methods, significantly reducing line collapse and defectivity while improving resolution at sub-2nm nodes. By integrating dry resist deposition, EUV exposure, and dry development into a single cluster tool, the patented technology enables scalable, high-volume EUV manufacturing with lower chemical consumption and improved process sustainability, positioning it as a key enabler for High-NA EUV lithography.

Lam Research’s dry resist technology represents a significant development in EUV lithography by addressing key challenges in stochastic defectivity, process cost, and sustainability. Its qualification for 2nm logic and advanced DRAM manufacturing confirms its readiness for high-volume production. By utilizing ALD for precise resist deposition and securing a stable precursor supply through partnerships with Entegris and Gelest, Lam has established a strong foundation for scaling the technology. 

Sources:

Lam Research Press Release on DRAM Adoption (Jan 2025): Lam Research
imec Qualification of Dry Resist for 2nm Logic (Jan 2025): imec
Entegris and Gelest Collaboration Announcement (July 2022): Entegris
Overview of Dry Resist ALD and Precursor Chemistry: SemiAnalysis
ASML High-NA EUV Roadmap and Implications for Dry Resist: ASML
Lam Reserach patent application US20220020584A1: US20220020584A1.pdf


Saturday, January 11, 2025

Integrating Metal-Oxide EUV Resists with Directed Self-Assembly for High-Resolution Chemical Patterning

Extreme ultraviolet (EUV) lithography struggles with resist materials that can deliver both high resolution and acceptable throughput, often resulting in rough patterns and printing defects that degrade semiconductor performance. To overcome this, researchers are exploring directed self-assembly (DSA) of block copolymers (BCPs), which can naturally rectify pattern defects when aligned to EUV-defined chemical guides. However, metal-oxide EUV resists (MORs), which provide high resolution, face challenges in converting their patterns into effective chemical guides for DSA integration.

This study presents a novel method using hydrogen silsesquioxane (HSQ), a negative tone resist, to create chemical patterns for integrating MORs with DSA. The process involves forming a sacrificial chromium pattern from HSQ, which is later replaced with a polyethylene oxide brush layer and a nonpolar polystyrene brush. These steps allow the successful assembly of polystyrene-block-poly(methyl methacrylate) BCPs, achieving 24 nm full-pitch resolution. This approach shows potential for producing sub-10 nm patterns by combining high-χ BCPs with MOR-based EUV lithography, advancing next-generation semiconductor fabrication.


DSA of BCPs is a promising nanofabrication technique that utilizes the phase separation properties of BCPs to create highly ordered nanoscale patterns with feature sizes below 10 nm. In DSA, BCPs self-organize into distinct microdomains, forming well-defined structures that can be guided using chemoepitaxy or graphoepitaxy. Chemoepitaxy involves chemically patterned surfaces that influence the alignment and orientation of BCP domains, while graphoepitaxy uses topographical features to achieve similar control. High-χ (chi) BCPs are often used to achieve finer pattern resolutions, and material optimizations such as selecting appropriate substrates and brush layers are crucial to improving pattern quality and reducing defects. DSA has been explored for various semiconductor applications, including the creation of dense line-space arrays, hole shrink patterns, and advanced memory devices, offering significant potential to enhance pattern fidelity, reduce defectivity, and lower manufacturing costs.

Sources:

High-resolution chemical patterns from negative tone resists for the integration of extreme ultraviolet patterns of metal-oxide resists with directed self-assembly of block copolymers | Journal of Vacuum Science & Technology B | AIP Publishing

https://www.spiedigitallibrary.org/conference-proceedings-of-spie/12956/3010817/Material-and-process-optimization-for-EUV-pattern-rectification-by-DSA/10.1117/12.3010817.full


https://journals.spiedigitallibrary.org/conference-proceedings-of-spie/12497/124970K/EUV-lithography-line-space-pattern-rectification-using-block-copolymer-directed/10.1117/12.2657990.full
https://www.mdpi.com/2073-4360/12/10/2432


https://www.spiedigitallibrary.org/conference-proceedings-of-spie/PC12054/PC1205402/Exploring-the-synergy-between-EUV-lithography-and-directed-self-assembly/10.1117/12.2622565.full
https://journals.aps.org/prb/abstract/10.1103/PhysRevB.101.085407

Sunday, November 17, 2024

ASML's 2024 Investor Day Highlights EUV-Driven Revenue Projections of €44-60 Billion by 2030 Amid AI, DRAM Scaling, and Advanced Semiconductor Growth

At its 2024 Investor Day, ASML projected annual revenue of €44 billion to €60 billion with gross margins of 56% to 60% by 2030, driven by double-digit growth in EUV lithography spending for Logic and DRAM, AI-driven semiconductor demand, and scalable EUV technology enabling cost-effective solutions for advanced nodes.

(Full video available here: Investor Day 2024)

DRAM scaling is undergoing a transformation fueled by the adoption of EUV lithography and the architectural shift to 3D DRAM, spearheaded by industry leaders Samsung, SK Hynix, and Micron. EUV lithography extends traditional DRAM scaling, enabling smaller cell sizes and higher densities. Micron plans to integrate EUV into DRAM production by 2025, marking a significant step toward cost-effective scaling. Samsung and SK Hynix are pioneering 3D DRAM architectures, which stack memory cells vertically to enhance density, performance, and energy efficiency. Samsung aims to commercialize 3D DRAM by 2030, while SK Hynix is targeting 2027-2028 for the introduction of vertical channel transistors (VCTs) with compact 4F² cell designs. These advancements represent a leap forward, with EUV lithography ensuring 2D scaling and 3D DRAM addressing physical and economic scaling limitations, paving the way for higher capacities and improved performance.


The progress and benefits of High-NA EUV lithography, with over 10,000 wafers exposed, including 1,300 DRAM and foundry customer wafers, and a target of 2,000 wafers by the end of 2024. Leading semiconductor companies like Micron, Intel, Samsung, SK Hynix, TSMC, and IBM are leveraging High-NA systems to enhance precision and scaling. Mark Philips from Intel highlights the readiness of High-NA EUV with robust tool availability and ecosystem support, enabling advancements like RibbonFETs, PowerVia, and "6x12" masks, which offer 23-50% productivity improvements over previous platforms. These developments underscore the role of High-NA EUV in enabling cost-effective scaling for DRAM and logic manufacturing.

ASML is pivotal in advancing EUV lithography for DRAM manufacturing. By 2024, memory manufacturers such as Samsung and SK Hynix had begun integrating EUV into production to enhance patterning precision and enable further scaling. ASML’s High-NA EUV systems, like the TWINSCAN EXE:5000, are expected to be production-ready by 2025, meeting stringent requirements for higher density and performance in memory technologies. Collaborations like the High-NA EUV Lithography Lab with imec have successfully demonstrated patterning for DRAM and logic structures, showcasing readiness for high-volume manufacturing by 2025-2026.


EUV lithography spending for DRAM is projected to grow at a CAGR of 15-25% through 2030. This growth is driven by the adoption of EUV for enhancing patterning precision and enabling further scaling in DRAM manufacturing. Key advancements include the integration of High-NA EUV systems, like ASML’s TWINSCAN EXE:5000, which is expected to be production-ready by 2025. These technologies support the development of 2D scaling and the transition to 3D DRAM architectures, addressing the physical and economic scaling challenges. Industry leaders Samsung, SK Hynix, and Micron are at the forefront of these efforts, incorporating EUV to achieve smaller cell sizes, higher densities, and improved energy efficiency.

Obviously, advanced logic drives EUV adoption. Spending in this sector is expected to grow at a CAGR of 10-20% through 2030, with High-NA systems playing a critical role in scaling logic nodes. Meanwhile, NAND benefits from advanced lithography solutions addressing the complexity of 3D NAND structures. Though it relies heavily on deposition and etch technologies, advanced DUV and EUV systems provide critical support for these applications.


The global semiconductor market is expected to grow significantly, driven by factors such as AI, high-performance computing, and 5G, which are fueling demand for advanced chips. Semiconductor sales are projected to reach $1 trillion by 2030, supported by the rapid adoption of AI technologies, growing automotive semiconductor needs for electric and autonomous vehicles, and the expansion of 5G networks and connected devices. Additionally, exponential growth in data generation is driving demand for robust data storage solutions, while continuous innovations in manufacturing, such as EUV lithography, enable smaller and more efficient chips. 

The global semiconductor market is expected to grow significantly, driven by AI, high-performance computing, and 5G. Sales are projected to reach $1 trillion by 2030, with wafer demand growing by 780,000 wafer starts per month annually. Strategic considerations, including geopolitical factors, are adding 5-8% extra wafer capacity by 2030. China’s role in the semiconductor industry remains vital, as the country invests heavily in advanced technologies to strengthen its manufacturing capabilities. However, due to export restrictions, China does not have access to ASML's EUV lithography tools. Instead, Chinese manufacturers focus on DUV technology and other innovative approaches to enhance their capabilities in advanced logic and DRAM production. Despite these limitations, China’s expanding wafer capacity contributes significantly to global growth projections, ensuring its relevance in the industry. The region’s efforts to integrate cutting-edge technologies, supported by partnerships with global leaders, highlight its ambitions to remain competitive and innovative in the semiconductor market.


ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030. Holistic lithography also plays a critical role in supporting front-end 3D integration by ensuring overlay control throughout pre-bonding, bonding, and post-bonding processes. Pre-bonding achieves <5 nm overlay error using scanner and offline metrology for correction and control, while bonding addresses large wafer deformation with extensive metrology (50-100 nm overlay error with over 5000 measurements per wafer). Post-bonding refines overlay error to <5 nm with over 2000 measurements per wafer, leveraging scanner actuators and lithography adjustments to bring errors within specifications.

ASML’s holistic lithography approach integrates computational models, metrology, and scanner optimization to maximize accuracy and yield. Innovations target reducing Edge Placement Errors (EPE) and enhancing defect inspections for 2D and 3D structures. The holistic lithography market is expected to grow at a CAGR exceeding 15% through 2030.

In conclusion, ASML’s strategy leverages its installed base, drives EUV and DUV advancements, and capitalizes on AI-driven demand. With projected annual revenue of €44-60 billion by 2030 and gross margins between 56% and 60%, ASML remains at the forefront of semiconductor innovation, enabling transformative progress in DRAM, logic, and NAND technologies.

Sources:

Investor Day 2024



Thursday, July 11, 2024

Tokyo Electron Introduces Acrevia Tool to Enhance EUV Lithography

Tokyo Electron has introduced Acrevia, a state-of-the-art gas cluster beam (GCB) system aimed at refining patterns created by EUV lithography. This advanced tool is set to reduce the necessity for EUV double patterning, thereby improving chipmaking yields and lowering production costs. Acrevia addresses critical challenges such as line edge roughness (LER), a common issue in lithography that affects the precision of pattern edges and overall chip performance. By optimizing pattern sidewalls through precise etching, Acrevia promises to significantly enhance within-wafer uniformity and mitigate LER, contributing to higher yield and better chip reliability. While not replacing High-NA EUV lithography, Acrevia marks a substantial leap forward in semiconductor manufacturing innovation.



Sources:

Tokyo Electron's new tool can reduce the necessity for EUV double patterning and improve yield | Tom's Hardware (tomshardware.com)

Tokyo Electron Launches Acrevia™, a Gas Cluster Beam System for Ultra-Fine Patterning in EUV Lithography | News Room | Tokyo Electron Ltd. (tel.com)

Sunday, June 16, 2024

ASML Unveils Hyper-NA EUV: Pioneering New Frontiers in Chip Innovation and Efficiency

ASML, the leader in lithography technology for semiconductor manufacturing, has launched its latest breakthrough: the Hyper-NA EUV tool and Intel being the first customer getting its first machine earlier this year. This leading-edge technology, which boosts the numerical aperture (NA) from 0.55 to 0.75, is poised to revolutionize chip design by enabling unprecedented levels of transistor density. Scheduled for introduction around 2030, Hyper-NA promises to extend the capabilities of chipmakers far beyond current limits, opening up new possibilities for intricate and powerful chip designs.

The presentation announcing ASML's Hyper-NA EUV technology was delivered by the company's former president, Martin van den Brink, at imec's ITF World event in Antwerp. 

Reduction in Double Patterning Complexity: Hyper-NA EUV technology simplifies the lithography process by reducing the need for double patterning, i.e., like Litho-Etch-Litho-Etch (LELE) etc., a method that involves aligning two masks perfectly to create intricate chip designs. By providing higher resolution and precision, Hyper-NA EUV minimizes the challenges and costs associated with double patterning, streamlining production and enhancing overall efficiency for chipmakers. However, there are a myriad of multi-patterning technologies deployed out there and SMIC, the main Chinese foundry, is reportedly using sextuple-patterning for its 5 nm technology.


Hyper-NA EUV technology is designed to significantly increase the productivity of semiconductor manufacturing, enabling the processing of 400 to 500 wafers per hour. This improvement will help chipmakers meet the growing demand for high-performance chips more efficiently, reducing production time and costs while maintaining high precision and quality.

The adoption of Hyper-NA EUV presents a myriad of opportunities for the semiconductor industry. As Intel has already installed the first High-NA systems, showcasing the potential of these advanced tools to enhance processor performance. As other industry leaders like TSMC, Samsung, Micron, and SK Hynix explore the adoption of High-NA and eventually Hyper-NA, the competitive landscape is set for a dynamic transformation. Innovations such as advanced polarizers to overcome light polarization issues and improvements in resist materials and etch selectivity will enable more precise and efficient chip manufacturing.

ASML’s Hyper-NA EUV technology is not just a short-term solution but part of a long-term roadmap that will sustain chip innovation for the next decade and beyond. Collaborative research and development efforts, including Imec’s simulations and Zeiss’s lens designs, highlight the cooperative spirit driving this technological advancement. As chip designers like Nvidia, Apple, and AMD leverage these tools at leading foundries such as TSMC, the future of chip design looks brighter than ever, promising enhanced productivity, technological leadership, and sustained growth. Hyper-NA EUV is set to redefine what is possible in the world of semiconductors, driving the industry towards new heights of efficiency and performance.

Friday, April 19, 2024

Intel's Strategic Leap with 14A Node and DSA: Pioneering Next-Gen Semiconductor Manufacturing

Semi Analysis recently published a deeper dive into of Directed Self Assembly (DSA) and prospects of Intel using it at their 14A node (Link below). Intel's latest efforts in semiconductor manufacturing have brought considerable attention to its 18A node, yet it's the 14A node that is most important according to the analysis for the success of Intel Foundry's IDM 2.0 strategy. While the industry watches the ongoing discussions around the merits of TSMC's N2 and Intel’s 18A technologies, Intel is quietly setting a foundational stage with its 14A node, aiming to solidify customer trust and secure critical, high-value chip projects for the future. A key element in Intel's strategy may be the adoption of DSA that could significantly reduce lithography costs. DSA utilizes the self-organizing properties of block copolymers (BCPs) that assemble into predetermined patterns when guided by an underlying template. This approach promises to lower the doses required in extreme ultraviolet (EUV) lithography, allowing for more efficient patterning at reduced costs.

However, integrating DSA into commercial manufacturing involves challenges such as defectivity and pattern limitations, which could hinder its adoption. So I looked more into historical patent filings and found that reveal a typical hype cycle with increased filings during periods of peak expectations, followed by a decline as practical challenges emerged. Intel and TSMC have been consistently filing DSA patents, indicating sustained investment and belief in DSA's potential. Merck, among other chemical suppliers, has significantly increased patent filings, aligning with technological advancements in DSA. Please find on overview below.


It is well known that Intel plans to be the first major company to implement ASML’s high-NA EUV lithography scanners in high volume, despite the higher costs associated with single exposure high-NA systems compared to low-NA double patterning. It was also recently reported on X and other places that ASML is delivering a High-NA System to another player. SemiAnalysis argues that, the economic challenge posed by high-NA technology is addressed through the integration of DSA, which can improve the final pattern quality and dramatically reduce the necessary dose, thus potentially making high-NA economically more viable.

The benefits of DSA are significant: 

  • The ability to produce finer features with lower line edge roughness and increased throughput, thanks to its ability to heal discrepancies in the EUV guide patterns. 
  • Substantial cost savings and improved yield, especially for layers critical to the performance of advanced logic chips (bigger dies like AI accelerators).

However, DSA's integration into a commercial manufacturing environment is not without risks. The risks associated with Intel's adoption of DSA include:

  • The primary risk with any new patterning technology is defectivity, for DSA it is linked to the chemical purity of the block copolymers (BCP). Synthesizing BCP to extremely high purities is challenging, and any inhomogeneity directly impacts the critical dimension (CD), leading to defects. Trace metals need to be below 10 parts-per-trillion, and filtering out organic impurities is difficult, impacting the viability of DSA for mass production. My assessment - Expect this to come from a MERCK or a Japanese chemical vendor.
  • DSA is inherently limited to producing 1D line/space patterns or contact hole arrays, restricted to a single pitch per layer. This complicates the integration with other process technologies that might require more diverse patterning capabilities. However, these issues have potential solutions similar to those used in multi-patterning schemes.
  • Despite the theoretical benefits and recent advances in DSA, it remains largely untested in high-volume, leading-edge manufacturing. Intel is pioneering the use in high-NA scenarios, but the broader adoption across the industry, including by competitors like TSMC who are also developing DSA, remains uncertain. 

Source: Intel’s 14A Magic Bullet: Directed Self-Assembly (DSA) (semianalysis.com)

So let´s do the Patbase Test - how does this hold out if we dig into historical and current patent filing by the suspects!

Yes indeed, we have seen much increased filing the past decade or so representing a typical hype cycle. The hype cycle is a model developed by Gartner that describes the progression of a technology from inception to widespread adoption and maturity. It typically consists of five phases: the Technology Trigger, Peak of Inflated Expectations, Trough of Disillusionment, Slope of Enlightenment, and Plateau of Productivity. So for DSA in semiconductor manufacturing, the technology first garnered attention when its potential applications in advanced lithography were identified (2000-2010), marking the Technology Trigger. Interest surged about 2011, leading to a Peak of Inflated Expectations around 2016/2017, evidenced by a spike in patent filings as companies raced to capitalize on the emerging technology. However, as practical and economic challenges such as defectivity and integration complexities became evident, the enthusiasm waned, and DSA entered the Trough of Disillusionment. During this phase, the technology's limitations led to a decline in interest as initial expectations were not met. Over time, as more sustainable applications and improvements are developed, DSA may progress into the Slope of Enlightenment, where understanding and optimization occur as described in the assessment by SemiAnalysis, before finally reaching the Plateau of Productivity in the years to come, where it becomes a standard part of semiconductor manufacturing processes. This progression through the hype cycle reflects the typical maturation path of innovative technologies in the industry. Please note that there is a delay in patent filing data of up to 18 months so 2022, 2023 and 2024 are not complete yet.

Patent filing since 2000 in DSA (Patbase, 2024-04-19)

2. Yes, Intel is actively filing DSA patents and in the lead, and so is TSMC, along with other key players in the ecosystem. Over the past decade, the pattern of DSA patent filings has been quite revealing. Initially, GlobalFoundries and IBM in Upstate New York were early filers. GlobalFoundries ceased their filings around the time they decided not to pursue 7 nm and nodes below. IBM also stopped filing after completing their 2 nm demonstration on 300 mm wafers in 2021. Main contenders Intel and TSMC have been consistently filing DSA patents throughout the hype cycle and have continued to do so. Notably, there has been a clear acceleration in Intel's patent filings since 2019, although there was a slight drop during the COVID-19 lockdowns. Looking at chemical suppliers, Merck has taken the lead, with increased filings beginning in parallel with Intel from 2019 onwards, and accelerating until today. Other suppliers such as JSR, Shin-Etsu, and Brewer Science are also active in the DSA space. In the segment of wafer equipment OEMs, Tokyo Electron and SCREEN have been dominant. However, SCREEN appears to have recently exited the game.

DSA Patent filing last decade (Patbase , 2024-04-19)

In Summary - good assessment by SemiAnalysis and i passes the Patbase Test!






Monday, April 15, 2024

SK hynix to Lead in Advanced DRAM Production, Overtaking Samsung with Earlier Start

Korean SK hynix is set to initiate mass production of its advanced 6th generation 10nm class DRAM (node 1c) in the third quarter of this year, ahead of its competitor Samsung Electronics. The move positions SK hynix to potentially lead in the DDR5 server memory market, which is needed for data centers operated by major tech companies. SK hynix has outlined a strategic internal roadmap that includes achieving necessary customer certifications in anticipation of a surge in demand, especially following compatibility approval with Intel's server platforms. This certification is crucial as Intel holds a dominant share in the global server CPU market. 

The DDR5 DRAM from SK hynix is designed to be compatible with Intel CPUs, a significant advantage given Intel’s extensive market presence. Meanwhile, Samsung plans to start its mass production of similar DRAM by the end of the year, having shared its development roadmap at the recent MemCon 2024 conference. Both companies are using leading-edge Extreme Ultraviolet (EUV) lithography in their processes, which enhances chip yield and power efficiency over previous generations.


SK hynix's new M16 DRAM plant in Icheon, Gyeonggi Province / Courtesy of SK hynix

Saturday, April 13, 2024

Applied Materials Pioneer® CVD film for EUV Sculpta and DRAM Sym3 Etch applications

Applied Materials continues to lead in semiconductor technology with its introduction of the Producer® XP Pioneer® CVD patterning film at the SPIE Advanced Lithography + Patterning conference. This latest innovation is critical for DRAM scaling and EUV lithography, offering improved etch selectivity and pattern fidelity due to enhanced film density and stiffness. Optimized for use with the Sculpta® pattern-shaping system, Pioneer allows for advanced patterning capabilities, crucial for maintaining precise feature dimensions. With its adoption by leading foundry-logic and memory manufacturers, the Pioneer system is set to significantly enhance Applied Materials' portfolio and revenue, affirming its leadership in CVD technologies.

Applied Materials' Draco™ hard mask and Sym3® Y HT etch system have revolutionized DRAM production by enabling the etching of perfectly cylindrical capacitor holes, significantly enhancing etch selectivity and improving critical dimension uniformity, which contributes to a notable increase in the company's market share in DRAM.



Demand for DRAM innovation continues to grow to feed the insatiable need for memory bandwidth in the AI era. The recently launched Pioneer CVD patterning film has already been adopted by leading memory manufacturers for DRAM patterning. Pioneer is a completely new CVD architecture based on a unique high-density carbon formula that is more resilient to etch chemistries used in the most advanced process nodes, permitting thinner film stacks with superior sidewall feature uniformity.

A thinner hard mask means less vertical distance is required for etch, resulting in a lower aspect ratio. This allows use of lower-power plasma and offers better control of the ratio of ions to radicals. A higher concentration of ions produces more efficient etches with better control, allowing desired patterns to be transferred to the wafer with exceptional fidelity. Pioneer is also being co-optimized with Applied’s new Sym3® Y Magnum® etch system to provide better control over conventional carbon films for critical etch applications in memory processing.



For EUV Lithography the Pioneer CVD patterning film developed by Applied Materials addresses the stringent demands of EUV lithography by increasing film density and stiffness, which enhances etch selectivity and allows for finer pattern control, vital for the ultra-fine dimensions required in advanced chip manufacturing.


Monday, January 8, 2024

Intel Receives ASML's First High-NA EUV Lithography Scanner, Pioneering Next-Gen Semiconductor Manufacturing

ASML has delivered its groundbreaking High-NA EUV lithography scanner, the Twinscan EXE:5000, to Intel Oregon. Marking a significant technological leap, this first-of-its-kind scanner boasts a 0.55 NA lens, enabling 8nm resolution for advanced semiconductor manufacturing. Designed for process technologies beyond 3nm, it promises to enhance chip production efficiency and reduce costs. Intel's early adoption of this state-of-the-art equipment, valued between $300-$400 million, positions them at the forefront of the industry, potentially setting new standards in High-NA manufacturing. This development represents a major milestone in semiconductor technology, signaling a new era of innovation and capability in chip production.



Friday, December 29, 2023

ASML's New Chapter: Navigating Tech Innovation and Geopolitical Shifts Under Christophe Fouquet's Leadership

In an era of significant technological and geopolitical changes, ASML, the number one player in the semiconductor industry, stands at a crossroads. The forthcoming retirement of Martin van den Brink and Peter Wennink, who have jointly steered ASML for over a decade, signals the end of a dynamic period. Van den Brink's leadership in technology development propelled ASML to unparalleled heights in the lithography sector, while Wennink’s diplomatic and financial acumen solidified its market dominance. ASML's impact extends beyond technology; it has become a geopolitical force, enhancing the Netherlands and Europe's strategic significance in global politics.


The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law.
 

As ASML approaches its 40th anniversary in April 2024, it confronts a changing landscape. The company has weathered various phases – from early struggles to market leadership, marked by innovations like the PAS 5500 and immersion lithography. Under Van den Brink, ASML prioritized technological advancement, often at the expense of other factors like reliability.

The appointment of Christophe Fouquet as the incoming CEO heralds a new era. Fouquet faces the challenge of maintaining ASML's technological edge while adapting to a market nearing the limits of Moore's Law. The shift in focus from chip performance to system-level advancements requires a nuanced approach. Additionally, as technology matures, reliability and predictability become crucial for maintaining ASML's competitive edge.

The transition from a "firefighter" engineering culture to one emphasizing process and reliability won't be easy. Fouquet must balance innovation with operational efficiency, ensuring ASML remains responsive to market and geopolitical dynamics. This requires a departure from the legacy of Van den Brink, focusing instead on a holistic, structured approach to development and engineering.

Fouquet's tenure will be pivotal in shaping ASML's future. His leadership must navigate the complexities of a highly competitive industry, geopolitical pressures, and the evolving technological landscape. The challenge lies in fostering a culture that values reliability and process without stifling the innovative spirit that has been ASML's hallmark. As the company moves into its fifth decade, its ability to adapt and evolve under Fouquet's guidance will determine its continued success in a rapidly changing world.

Advancing the Microchip Revolution: EUV Lithography's Challenges and Future Outlook

Extreme Ultraviolet (EUV) lithography represents a significant advancement in semiconductor manufacturing, enabling the production of more compact and efficient integrated circuits, particularly for 7 nm Logic process nodes and below and leading edge DRAM. This technology, developed and marketed primarily by ASML Holding, uses a highly specialized process involving laser-pulsed tin droplet plasma to etch patterns onto substrates at the 13.5 nm wavelength scale. The progression from early prototypes to more efficient models has been remarkable, with modern EUV systems capable of handling 200 wafers per hour, a substantial improvement from initial prototypes.

Looking into the future, EUV lithography is expected to play a critical role in advancing semiconductor technology, especially as the demand for smaller and more powerful chips increases. However, several technological challenges need addressing continiously to fully harness EUV's potential:

1. Optical Component Durability: The EUV process requires highly specialized and sensitive optical components, including mirrors and photomasks. These components are prone to degradation from exposure to high-energy photons and contaminants. Improving their durability and developing efficient cleaning and maintenance processes are crucial.

2. Throughput Efficiency: While significant improvements have been made, further enhancing the throughput of EUV systems is vital. This includes reducing setup times, increasing the speed of the lithography process, and minimizing downtime due to maintenance or component replacement.

3. Pattern Fidelity and Defect Reduction: As circuit patterns become increasingly smaller, maintaining pattern fidelity and reducing defects is challenging. This involves improving the resolution of EUV systems, enhancing photoresist materials to better respond to EUV exposure, and developing more effective methods to mitigate the impact of secondary electrons generated during the lithography process.

EUV Lithography - Balancing Technological Advancements with Energy Challenges

EUV lithography, pivotal in advanced semiconductor manufacturing, faces significant energy consumption challenges. The generation of EUV light, typically via laser-pulsed tin plasma, is inherently energy-intensive. Additionally, maintaining the necessary vacuum environment and cooling systems for these high-precision machines further escalates energy use. As EUV technology becomes more prevalent, especially for producing smaller, more efficient chips, optimizing energy efficiency is critical. Future developments are expected to focus on more efficient light sources, improved system design for energy conservation, and advanced thermal management, aiming to reduce the overall energy footprint of EUV lithography processes.


The semiconductor industry, traditionally known for its high environmental impact, is increasingly embracing sustainability. With the global demand for semiconductors rising, manufacturers face the challenge of scaling up production while addressing substantial water and electricity usage and managing hazardous waste from gases used in manufacturing. Historically, the focus has been on balancing power, performance, and cost. Recently, however, sustainability has emerged as a crucial consideration, with many facilities actively working to decarbonize their supply chains and reduce overall environmental impact (data from imec)

EUV Lithography's Hydrogen Demand: A Growing Concern in Chip Manufacturing

EUV Lithography, also raises concerns regarding its significant hydrogen consumption. The EUV process relies heavily on hydrogen gas to maintain the cleanliness of the optical elements, particularly for preventing tin deposition on the mirrors. The need for a continuous supply of hydrogen to facilitate this cleaning process contributes to the overall operational costs and resource demands of EUV systems. As EUV technology becomes more widespread in chip manufacturing, addressing the sustainability and efficiency of hydrogen usage will be essential, both from an environmental and economic perspective.



In EUV lithography, managing hydrogen usage presents distinct challenges. The technology requires hydrogen for removing contaminants from critical mirrors, demanding systems capable of handling high volumes while maintaining vacuum integrity. This necessity places a premium on innovative system designs that minimize the footprint and energy consumption associated with hydrogen management, directly impacting the cost and efficiency of semiconductor manufacturing. Safety considerations, given hydrogen's flammability, are paramount. Advanced, fuel-free hydrogen management strategies are employed to ensure safety and environmental compliance. These strategies focus on reducing flammability risks and eliminating the need for additional fuels, thereby minimizing carbon emissions and contributing to sustainable manufacturing practices.

Continued research and development in these areas are essential for the advancement of EUV lithography, ensuring it meets the rapidly evolving demands of the semiconductor industry.

Sources: 

Christophe Fouquet’s ASML must reinvent itself – Bits&Chips (bits-chips.nl)

www.imec.be

www.edwards.com

Wikipedia

Tuesday, September 26, 2023

TechInsights Discovers Micron's Cutting-Edge D1β LPDDR5 16 Gb DRAM Chips in Apple iPhone 15 Pro: Setting a New Standard in Memory Technology

TechInsights has confirmed Micron's cutting-edge D1β LPDDR5 16 Gb DRAM chips in the Apple iPhone 15 Pro, marking the industry's first venture into the D1β generation. These chips are smaller and denser than their predecessors, showcasing significant advancements in DRAM technology. Notably, Micron has achieved this without utilizing Extreme Ultraviolet Lithography (EUVL), a technique employed by competitors like Samsung and SK Hynix for their DRAM processes. This achievement highlights Micron's dedication to pushing the boundaries of DRAM technology, emphasizing innovation and efficiency in the tech landscape. Micron's groundbreaking D1β LPDDR5 16 Gb DRAM chip promises to reshape the future of memory technology, setting a new standard for the industry.

(Source Micron.com)

1-BETA includes cool stuff

High-k/Metal Gate

Micron's 1β fabrication process uses the company's 2nd generation high-K metal gate (HKMG) and is said to increase bit density of a 16Gb memory die by 35% as well as to improve power efficiency by 15% when compared to a similar DRAM device made on the company's 1α node

Pitch multiplication without the need for EUV Lithography

Micron's use of proprietary multi-patterning lithography involves advanced techniques for defining circuit patterns on semiconductor wafers with the highest precision. This approach allows Micron to create intricate patterns on the chips, achieving higher memory capacity in a smaller footprint. It enables the company to fit billions of memory cells on a chip that's roughly the size of a fingernail. 

While the semiconductor industry has been transitioning to extreme ultraviolet lithography (EUVL) to overcome technical challenges in patterning, Micron has opted for its multi-patterning lithography approach. This choice showcases Micron's expertise and innovation in lithography techniques, enabling them to continue shrinking circuit features and achieving greater memory capacity without relying on EUVL, which is still considered an emergent technology. 

By using proprietary multi-patterning lithography, Micron not only reduces the cost per bit of data but also enables devices with small form factors, such as smartphones and IoT devices, to incorporate more memory into compact spaces. This approach underscores Micron's commitment to staying at the forefront of memory technology innovation.
"While the industry has begun to shift to a new tool that uses extreme ultraviolet light to overcome these technical challenges, Micron has tapped into its proven leading-edge nano-manufacturing and lithography prowess to bypass this still emergent technology. Doing so involves applying the company’s proprietary, advanced multi-patterning techniques and immersion capabilities to pattern these minuscule features with the highest precision," Micron explains. Thy Tran, VP Process Integration, Micron



On the heels of the news that Micron has begun shipping QS-sample LPDDR5X components developed on the new 1-beta DRAM process node to its smartphone customers, host Jim Greene welcomes Thy Tran, Vice President of DRAM Process Integration, to the Chips Out Loud Podcast to discuss the emergent technology.

Sources:

Micron LPDDR5 16 Gb Non-EUVL Chip Found in Apple iPhone 15 Pro | TechInsights

LPDRAM | LPDDR | Micron Technology

Micron Ships World’s Most Advanced DRAM Technology With 1-Beta Node | Micron Technology


(Source: TechInsights.com)


Friday, September 22, 2023

ASML's 2023 Outlook: Surging Ahead in Semiconductor Equipment Despite Challenges and Export Controls

In 2023, ASML, the leading semiconductor lithography equipment supplier, is set to achieve remarkable success, outpacing its rivals and emerging as the number 1 provider of Wafer Fabrication Equipment. Boasting an impressive 30% revenue growth forecast for the year, ASML is thriving amidst an industry landscape marked by its consistent performance. With a substantial backlog of cutting-edge Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems and surging demand from China, ASML's growth continues despite hurdles like supply chain disruptions and regulatory changes, ASML remains a beacon of innovation and resilience in the semiconductor sector.

By Abhishek Kumar Thakur and Jonas Sundqvist

ASML, a leading supplier of semiconductor equipment, is poised for a significant year in 2023, projected to surpass Applied Materials (AMAT) as the top provider of Wafer Fabrication Equipment. This achievement is attributed to ASML's robust revenue growth, expected to reach a remarkable 30% increase in 2023, while Applied Materials faces a decline of 20% according to Seeking Alpha*. ASML's success can be attributed to a substantial backlog of Deep Ultraviolet (DUV) and Extreme Ultraviolet (EUV) systems, driven by heightened demand in China.

* Fact check: Due to strong DUV revenue and despite the increased uncertainties, ASML expects strong growth for 2023 with a net sales increase towards 30% and a slight improvement in gross margin, relative to 2022. ASML Holding revenue for the twelve months ending June 30, 2023 was $27.293B, a 25.97% increase year-over-year. AMAT revenue is estimated to increase by 2.6% to 26.33 B. Meaning ASML would pass bu end of 2023.

https://finance.yahoo.com/quote/AMAT/analysis/ 



Despite facing challenges like supply chain disruptions and a factory fire, ASML has consistently ranked among the top three semiconductor equipment suppliers since 2017. Their backlog of EUV systems, combined with growing acceptance of DUV tools, contributes to their strong performance.

However, potential headwinds include supply chain concerns, past issues like the Berlin factory fire, and looming sanctions affecting exports to China. While ASML has addressed some challenges, the possibility of US sanctions in 2024 poses a threat to its growth.

Furthermore, ASML now faces new export controls imposed by the Netherlands, impacting shipments to China. While the company downplays these controls' immediate financial impact, they are expected to affect specific DUV systems, adding to global efforts to limit China's semiconductor advancements.

In this volatile landscape, ASML's ability to adapt to evolving regulations and maintain its technological leadership will be crucial. The impact of these restrictions, especially on shipments to China, could influence the company's growth trajectory in the semiconductor industry. Despite these challenges, ASML remains a prominent player with significant potential in the semiconductor equipment market.

ASML is set to deliver the industry's first High-NA extreme ultraviolet (EUV) lithography scanner by the end of 2023, marking a significant development for advanced chip manufacturing. The Twinscan EXE:5000 pilot scanner with a 0.55 numerical aperture (NA) will enable chipmakers to explore High-NA EUV technology. This innovation is crucial for achieving an 8nm resolution, suitable for manufacturing technologies beyond 5nm nodes. Intel is expected to be the first customer, but integration and adoption details are still uncertain. This advancement requires substantial investments, with reports suggesting costs of $300-400 million per unit.

To add some colour, initially, Intel had plans to employ ASML's High-NA tools for its 18A (1.8 nm) production node, scheduled for high-volume manufacturing in 2025, aligning with ASML's Twinscan EXE:5200 delivery. However, Intel accelerated its 18A production, moving it to the latter part of 2024. This change in strategy involved the use of ASML's Twinscan NXE:3600D/3800E with two exposures and Applied Material's Endura Sculpta pattern-shaping system. The objective was to reduce reliance on EUV double patterning techniques. Applied Materials' Centura Sculpta is a pattern-shaping machine equipped with a unique algorithm that can manipulate patterns produced by an EUV scanner. It has the capability to stretch these patterns in a user-defined direction along the X-axis. This process effectively reduces the space between features and enhances pattern density. This means that moving ahead ASML and Applied Materials are entering an interesting competitive space previously not encountered.

ASMLs Products

As an background, ASML specializes in the production of cutting-edge lithography systems crucial for semiconductor manufacturing. Their product portfolio includes the following key offerings:

Extreme Ultraviolet (EUV) Lithography Machines: ASML's EUV lithography machines are at the forefront of semiconductor manufacturing technology. These machines use extremely short wavelengths of light to create intricate patterns on silicon wafers, enabling the production of advanced and smaller semiconductor chips. EUV technology is essential for next-generation processors and memory chips.

Deep Ultraviolet (DUV) Lithography Machines: DUV lithography systems are another vital component of ASML's product lineup. They use longer wavelengths of light compared to EUV and are employed for a wide range of semiconductor applications, including memory and logic chip production. ASML's DUV systems are known for their precision and reliability.

TWINSCAN Series: Within the DUV lithography category, ASML offers the TWINSCAN series, which includes machines like the TWINSCAN NXT:2000i, NXT:2050i, and NXT:2100i. These systems are designed for immersion lithography, where the wafer and the lens are submerged in a liquid, enhancing precision and resolution.

EUV High Numerical Aperture (NA) Systems: ASML has been advancing its lithography machines by increasing the numerical aperture (NA), a key parameter that affects resolution. High-NA systems are capable of printing even smaller features on semiconductor wafers, enabling the production of highly advanced chips.

ASML's lithography machines are considered critical infrastructure for semiconductor manufacturing, and the company's technological leadership in this area has positioned it as a dominant player in the industry. The company's ability to innovate and adapt its lithography systems to meet the ever-increasing demands of semiconductor manufacturers has been a key factor in its success and growth prospects. However, the recent export controls and geopolitical pressures, particularly concerning shipments to China, introduce additional challenges and uncertainties for ASML and its specialized products.

Sources:

ASML Hit With New Dutch Limits on Chip Gear Exports to China - Bloomberg

ASML To Top WFE Semiconductor Equipment In 2023, Topping Applied Materials | Seeking Alpha

ASML to ship first pilot tool in its next product line in 2023, CEO says | Reuters

ASML to Deliver First High-NA EUV Tool This Year (anandtech.com)

EUV Alternative Speeds Up Chip Production - EE Times

BALD Engineering - Born in Finland, Born to ALD: ASML Remains on Track to Deliver High NA EUV Machines in 2023

BALD Engineering - Born in Finland, Born to ALD: Netherlands' chip tool export controls take effect for DUV Lithography and ALD

BALD Engineering - Born in Finland, Born to ALD: Applied Materials’ Pattern-Shaping Technology - Centura Sculpta


Wednesday, September 6, 2023

ASML Remains on Track to Deliver High NA EUV Machines in 2023

ASML, the leading semiconductor equipment manufacturer, is set to ship the first pilot tool from its next product line in 2023, despite some supplier delays, according to CEO Peter Wennink. These High NA EUV machines, crucial for top chipmakers to create smaller and better chips in the coming decade, will cost over $300 million euros each and provide up to 70% better resolution. ASML currently dominates the lithography market, a pivotal step in chipmaking, and is seeing strong demand for its older DUV machines, with 30% sales growth forecasted in 2023, primarily driven by Chinese customers.

ASML's High NA EUV machines are used by a range of prominent semiconductor manufacturers, including TSMC, Intel, Samsung, SK Hynix, and Micron. These chipmakers rely on ASML's cutting-edge lithography equipment to manufacture semiconductor chips, from microprocessors to memory chips.

"High NA" stands for "High Numerical Aperture." Numerical Aperture (NA) is a measure of the ability of an optical system, such as a lens or mirror, to gather and focus light. A higher numerical aperture indicates a greater ability to capture light and provide finer detail and resolution in imaging or lithography processes. ASML's High NA EUV machines, are designed to gather light from a wider angle compared to their previous generation tools. This wider angle collection of light allows for significantly improved resolution in the semiconductor manufacturing process, making it possible to create smaller and more advanced semiconductor chips with greater precision required for the Ångström Era - basically the sub 2 nm nodes.

Source:





Thursday, August 24, 2023

TSMC Marks Major Milestone: First EUV Machine Installed in Arizona Fab, Job Opportunities Open

Taiwan Semiconductor Manufacturing Co. (TSMC) has achieved a significant milestone in its Arizona manufacturing venture by installing its inaugural extreme ultraviolet lithography (EUV) machine. This advanced machine, procured from Dutch semiconductor equipment leader ASML Holding NV, is a pivotal asset for TSMC's future high-end chip production endeavors.


EUV technology is a critical aspect of semiconductor fabrication, facilitating the printing of intricate designs on microchips significantly smaller than a human hair. TSMC's achievement underscores its commitment to innovation and technological leadership.

While the installation of the EUV machine marks a remarkable accomplishment, TSMC acknowledges that the setup of the new fab in Arizona involves numerous additional tasks. The company emphasized the need for approximately 2,000 skilled workers to handle the installation of various equipment pieces and services in the complex. This requirement stems from TSMC's unique tool configurations and specifications.

TSMC, recognized as the world's largest contract chip manufacturer, is channeling substantial investments amounting to $40 billion into constructing two wafer fabs in Phoenix. The first facility will employ the advanced 4-nanometer process, while the second, already under construction, will utilize the more sophisticated 3-nanometer process. This latter technology has already entered mass production in Taiwan.

The presence of skilled workers has been a contentious topic linked to the Arizona project. TSMC Chairman Mark Liu explained that a deficiency in experts capable of properly installing equipment at the Arizona site has led to a delay in mass production, now projected for 2025 rather than late 2024.

However, TSMC's approach to addressing this shortfall has sparked debates. The company's bid to bring in around 500 Taiwanese workers on temporary E-2 visas has faced resistance from local unions, who assert that prioritizing American jobs is paramount, especially considering the significant subsidies TSMC seeks under the CHIPS and Science Act. This legislation, signed by President Joe Biden, encourages semiconductor investments in the United States.

US Senator Mark Kelly of Arizona emphasized that the visa applications will be evaluated in accordance with established laws and procedures. As TSMC navigates these challenges, its progress in Arizona remains a focal point in the semiconductor industry's dynamic landscape.

TSMC installs first EUV machine in U.S.; job opening ads posted - Focus Taiwan

An Update on Directed Self-Assembly (DSA) for Advancing Micro and Nano Fabrication

Revolutionizing fabrication, Directed Self-Assembly (DSA) innovates micro to nano devices and materials. It leverages block co-polymer morphology for precise patterns and guides micro/nano particles, enhancing manufacturing. In semiconductors, DSA addresses lithography challenges, while Imec's research showcases DSA-EUV synergy for defect-free outcomes. Complex rectification processes, illustrated by Imec, spotlight improved Critical Dimension Uniformity and Pattern Placement Error control. As DSA advances, its collaboration with EUV promises precision, efficiency, and innovation across industries.

DSA has emerged as a groundbreaking technique for mass-producing micro to nano devices and materials with precision and efficiency. This method harnesses the inherent properties of materials to assemble them into intricate structures, revolutionizing manufacturing processes across various industries.

DSA leverages block co-polymer morphology to create patterns, enhancing feature control and shape accuracy. This involves guiding the assembly of micro and nano particles to achieve desired structures, made possible by the precise control of surface interactions and polymer thermodynamics. The key advantage of DSA is its ability to create structures at remarkably small scales, enabling advancements in diverse fields.

In the semiconductor industry, DSA offers a new perspective on lithography challenges. Despite initial setbacks, DSA is being revisited to address critical issues such as stochastic defects in extreme ultraviolet (EUV) lithography. These defects, which can contribute significantly to patterning errors, have led semiconductor manufacturers to explore DSA as a solution to rectify these problems. Notably, DSA is not replacing traditional methods but rather enhancing them. It is being integrated with existing manufacturing processes to enable increased resolution and precision, all while reducing costs.

However, challenges persist in integrating DSA into high-volume manufacturing. Defect control remains a primary concern, as the technology strives to meet industry standards of minimal defectivity. Common defects include line bridging, collapse, bubbles, and dislocations. Efforts are ongoing to optimize annealing temperature, etching methods, and film thickness to reduce these defects. Another challenge is the complexity of pattern inspection, which demands accurate metrology methods. Researchers are exploring machine learning-based approaches to automate the inspection process and achieve higher throughput.

Despite these challenges, DSA is being applied to various applications beyond semiconductors. Tissue engineering benefits from the precision of directed assembly, enabling the controlled organization of cells into desired micro-structures. In nanotechnology, DSA facilitates the creation of precise nanostructures, leading to advancements in areas such as graphene nanoribbon arrays and thin-film quantum materials.

Revolutionizing EUV Lithography with Directed Self-Assembly (DSA)

EUV lithography has revolutionized semiconductor manufacturing but comes with its share of challenges, particularly in addressing line roughness and stochastic defects. DSA has now gained attention as a potential game-changer to tackle these issues in EUV lithography.

Recent research from Imec sheds light on the promising synergy between EUV and DSA in overcoming lithography challenges. In the study titled "EUV Lithography Line Space Pattern Rectification Using Block Copolymer Directed Self-Assembly: A Roughness and Defectivity Study," led by Julie Van Bel and team, the researchers explored the combination of DSA with EUV. Their findings indicate that this integration surpasses DSA processes based on Immersion lithography, offering lower line width roughness and freedom from dislocation defects.

Another study, "Mitigating Stochastics in EUV Lithography by Directed Self-Assembly," led by Lander Verstraete and collaborators, delved into the application of DSA to mitigate stochastic defects in EUV processing.

Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in Figures below. In the top Figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using DSA. Meanwhile, the lower Figure details the rectification process for defects in EUV Contact Patterns.


Imec's approach to rectify defects in EUV lithography involves intricate processes, as illustrated in the figures below. In the top figure, the team outlines the process for rectifying defects in EUV Line/Space Patterns using Directed Self-Assembly (DSA). Meanwhile, the lower figure details the rectification process for defects in EUV Contact Patterns. These illustrations highlight the potential of DSA in enhancing lithographic precision, addressing challenges related to line roughness and stochastic defects, and achieving improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error control in semiconductor manufacturing.

The results are particularly promising for line/spaces at a 28nm pitch, primarily addressing bridge defects. However, at a 24nm pitch, further improvement is necessary due to an excess of bridge defects. Notably, the type and frequency of defects correlate with the formulation of the block copolymer and the duration of the annealing process.

For contact arrays, the combination of EUV and DSA demonstrates improved Local Critical Dimension Uniformity (LCDU) and Pattern Placement Error. This advancement also enables the use of a lower dose, contributing to enhanced precision and efficiency in semiconductor manufacturing.

Imec's research underscores the potential of DSA to revolutionize EUV lithography by addressing line roughness and stochastic defects. The successful integration of EUV and DSA holds the promise of enhancing semiconductor manufacturing processes, achieving higher precision, and enabling the production of advanced devices with improved quality. As researchers continue to refine these methods, the collaboration between EUV and DSA is set to shape the future of lithography and microfabrication.

In conclusion, DSA is revitalizing micro and nano fabrication by offering accurate and efficient methods for mass production. While challenges like defect control and metrology persist, DSA's potential to shape the future of industries such as semiconductors, biomedicine, and nanotechnology is undeniable. As research continues to refine DSA processes and overcome hurdles, its role in advancing technology and innovation is set to expand further.

Directed Self-Assembly Finds Its Footing (semiengineering.com)

SPIE 2023 – imec Preparing for High-NA EUV - SemiWiki

Directed assembly of micro- and nano-structures - Wikipedia