Showing posts with label Imec. Show all posts
Showing posts with label Imec. Show all posts

Wednesday, May 5, 2021

Imec and AIXTRON Demonstrate 200 mm GaN Epitaxy on AIX G5+ C

Imec and AIXTRON Demonstrate 200 mm GaN Epitaxy on AIX G5+ C for 1200V Applications with Breakdown in Excess of 1800V

LEUVEN (Belgium), APRIL 29, 2021 — Imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, and AIXTRON, the leading provider of deposition equipment for compound semiconductor materials, have demonstrated epitaxial growth of gallium-nitride (GaN) buffer layers qualified for 1200V applications on 200mm QST® substrates, with a hard breakdown exceeding 1800V. The manufacturability of 1200V-qualified buffer layers opens doors to highest voltage GaN-based power applications such as electric cars, previously only feasible with silicon-carbide (SiC)-based technology. The result comes after the successful qualification of AIXTRON’s G5+ C fully automated metal-organic chemical vapor deposition (MOCVD) reactor at imec, Belgium, for integrating the optimized material epi-stack.

AIX G5+ C reactor module with cassette-to-cassette wafer handler (

Wide-bandgap materials gallium-nitride (GaN) and silicon-carbide (SiC) have proved their value as next-generation semiconductors for power-demanding applications where silicon (Si) falls short. SiC-based technology is the most mature, but it is also more expensive. Over the years tremendous progress has been made with GaN-based technology grown on for example 200mm Si wafers. At imec, qualified enhancement mode high-electron-mobility transistors (HEMTs) and Schottky diode power devices have been demonstrated for 100V, 200V and 650V operating voltage ranges, paving the way for high-volume manufacturing applications. However, achieving operating voltages higher than 650V has been challenged by the difficulty of growing thick-enough GaN buffer layers on 200mm wafers. Therefore, SiC so far remains the semiconductor of choice for 650-1200V applications – including for example electric cars and renewable energy.

For the first time, imec and AIXTRON have demonstrated epitaxial growth of GaN buffer layers qualified for 1200V applications on 200mm QST® (in SEMI standard thickness) substrates at 25°C and 150°C, with a hard breakdown exceeding 1800V. Denis Marcon, Senior Business Development Manager at imec: “GaN can now become the technology of choice for a whole range of operating voltages from 20V to 1200V. Being processable on larger wafers in high-throughput CMOS fabs, power technology based on GaN offers a significant cost advantage compared to the intrinsically expensive SiC-based technology.”

Key to achieving the high breakdown voltage is the careful engineering of the complex epitaxial material stack in combination with the use of 200mm QST® substrates, executed in scope of the IIAP program The CMOS-fab friendly QST® substrates from Qromis have a thermal expansion that closely matches the thermal expansion of the GaN/AlGaN epitaxial layers, paving the way for thicker buffer layers – and hence higher voltage operation.

Dr. Felix Grawert, CEO and President of AIXTRON “The successful development of imec’s 1200V GaN-on-QST® epi-technology into AIXTRON’s MOCVD reactor is a next step in our collaboration with imec. Earlier, after having installed AIXTRON G5+C at imec’s facilities, imec’s proprietary 200mm GaN-on-Si materials technology was qualified on our G5+ C high-volume manufacturing platform, targeting for example high-voltage power switching and RF applications and enabling our customer to achieve a rapid production ramp-up by pre-validated available epi-recipes. With this new achievement, we will be able to jointly tap into new markets.” Currently, lateral e-mode devices are being processed to prove device performance at 1200V, and efforts are ongoing to extend the technology towards even higher voltage applications. Next to this, imec is also exploring 8-inch GaN-on-QST® vertical GaN devices to further extend the voltage and current range of GaN-based technology.

Thursday, February 11, 2021

Imec Demonstrates 20nm Pitch Line/Space Resist Imaging with High-NA EUV Interference Lithography

Imec, Belgium, reports for the first time the use of a 13.5 nm High Harmonic Generation source for the printing of 20nm pitch line/spaces using interference lithographic imaging of an Inpria metal-oxide resist under high-numerical-aperture (high-NA) conditions. 

The demonstrated high-NA capability of the EUV interference lithography using this EUV source presents an important milestone of the AttoLab, a research facility initiated by imec and KMLabs to accelerate the development of the high-NA patterning ecosystem on 300 mm wafers. The interference tool will be used to explore the fundamental dynamics of photoresist imaging and provide patterned 300 mm wafers for process development before the first 0.55 high-NA EXE5000 prototype from ASML becomes available.

Source: LINK

By Abhishekkumar Thakur

Friday, December 18, 2020

Imec demonstrate BEOL compatible architecture that paves the way to high-density 3D-DRAM memories

LEUVEN (Belgium), 15 December 2020 — This week, at the 2020 International Electron Devices Meeting, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents a novel dynamic random-access memory (DRAM) cell architecture that implements two indium-gallium-zinc-oxide thin-film transistors (IGZO-TFTs) and no storage capacitor. DRAM cells in this 2T0C (2 transistor 0 capacitor) configuration show a retention time longer than 400s for different cell dimensions – significantly reducing the memory’s refresh rate and power consumption. The ability to process IGZO-TFTs in the back-end-of-line (BEOL) reduces the cell’s footprint and opens the possibility of stacking individual cells. These breakthrough results pave the way towards low-power and high-density monolithic 3D-DRAM memories.

(image: Imec)

Scaling traditional 1T1C (one transistor one capacitor) DRAM memories beyond 32Gb die density faces two major challenges. First, difficulties in Si-based array transistor scaling make it challenging to maintain the required off-current and world line resistance with decreasing cell size. Second, 3D integration and scalability – the ultimate path towards high-density DRAM – is limited by the need for a storage capacitor. Imec presents a novel DRAM architecture that responds to both challenges, thereby offering a scaling path towards low-power high-density 3D-DRAM memories.

The new architecture implements two IGZO-TFTs – which are well known for their very low off-current – and no storage capacitor. In this 2T0C configuration, the parasitic capacitance of the read transistor serves as the storage element. Resulting DRAM cells exhibit a retention time >400s thanks to an extremely low (extracted) off-current of 3x10-19A/µm. These breakthrough results were obtained for optimized scaled IGZO transistors (with 45nm gate length) processed on 300mm wafers. Optimization was directed towards suppressing the impact of oxygen and hydrogen defects on both on-current and threshold voltage – one of the main challenges for developing IGZO-TFTs.

Gouri Sankar Kar, Program Director at imec: “Besides the long retention time, IGZO-TFT-based DRAM cells present a second major advantage over current DRAM technologies. Unlike Si, IGZO-TFT transistors can be fabricated at relatively low temperatures and are thus compatible with BEOL processing. This allows us to move the periphery of the DRAM memory cell under the memory array, which significantly reduces the footprint of the memory die. In addition, the BEOL processing opens routes towards stacking individual DRAM cells, hence enabling 3D-DRAM architectures. Our breakthrough solution will help tearing down the so-called memory wall, allowing DRAM memories to continue playing a crucial role in demanding applications such as cloud computing and artificial intelligence.”

Thursday, December 17, 2020

Imec introduces 2D materials in the logic device scaling roadmap

[IEDM 2020 Virtual, Imec Belgium LINK] At the 2020 IEDM conference, imec proposes that 2D semiconductors like tungsten disulfide (WS2) can further extend the logic transistor scaling roadmap. The team laid the groundwork for integrating 2D semiconductors in a 300mm CMOS fab, and worked towards improved device performance. These findings are presented in four IEDM papers, one of which was selected as IEDM highlight.

More details can be found in 4 papers presented at the 2020 IEDM conference:

[1] ‘Introducing 2D-FETs in device scaling roadmap using DTCO’, Z. Ahmed et al.
[2] ‘Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab’, I. Asselberghs et al.
[3] ‘Dual gate synthetic WS2 MOSFETs with 120µS/µm Gm 2.7µF/cm2 capacitance and ambipolar channel’, D. Lin et al.
[4] ‘Sources of variability in scaled MoS2 FETs’, Q. Smets et al. (IEDM highlight paper)

TEM image of a 2D device fabricated with 300mm processes. (Source: Imec)

Wednesday, December 11, 2019

Imec shows excellent performance in ultra-scaled FETs with 2D-material channel

[Press release, imec, LINK] SAN FRANCISCO (USA), December 8, 2019 — At this year’s IEEE International Electron Devices Meeting (Dec 7-11 2019), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, reports an in-depth study of scaled transistors with MoS2 and demonstrates best device performance to date for such materials. 

TEM pictures showing (a) 3 monolayers MoS2 channel, with contact length 13nm and channel length 29nm Transfer characteristics have improved sub-threshold swing (SS) with thinner HfO2. (

MoS2 is a 2D material, meaning that it can be grown in stable form with nearly atomic thickness and atomic precision. Imec synthesized the material down to monolayer (0.6nm thickness) and fabricated devices with scaled contact and channel length, as small as 13nm and 30nm respectively. These very scaled dimensions, combined with scaled gate oxide thickness and high K dielectric, have enabled the demonstration of some of the best device performances so far. Most importantly, these transistors enable a comprehensive study of fundamental device properties and calibration of TCAD models. The calibrated TCAD model is used to propose a realistic path for performance improvement. The results presented here confirm the potential of 2D-materials for extreme transistor scaling – benefiting both high-performance logic and memory applications.

Saturday, November 23, 2019

Imec updates semiconductor miniaturization roadmap to 1nm-ITF Japan 2019

Imec held an annual research result presentation event “imec Technology Forum Japan 2019 (ITF Japan 2019)” in Tokyo on October 11.

This is what we are to expect coming next for Logic scaling: Nanosheet transistors (Gate All Around transistors), Buried Power Rails, Ruthenium incorporation, Forksheet transistor architecture, CFET (complementary FET by 3D stacking of nanosheet PFET and NFET), deployment of 2D materials, spintronics, and quantum computing as the way to continued chip scaling for keeping a modified Moore's Law alive.
Source: LINK

By Abhishekkumar Thakur

Friday, June 21, 2019

Aixtron partners in UltimateGaN project to make power semiconductors available for broad applications at competitive cost

[Semicondutor Today] Deposition equipment maker Aixtron SE of Herzogenrath, near Aachen, Germany says that it is a partner in the European research project UltimateGaN (research for GaN technologies, devices and applications to address the challenges of the futureGaN roadmap). In addition to Aixtron, 25 other companies and institutions from nine countries have come together to research the next generation of energy-saving chips based on gallium nitride (GaN) over the next three years. The aim is to make these power semiconductors available for a wide range of applications at globally competitive costs.

The UltimateGaN consortium consists of 26 well-established participants originating from 9 European member states and associated countries constituting a balanced mix of industry and research with complementary skills and expertise. The multidisciplinary partners cover the entire value chain technology – packaging – reliability – application.

UltimateGaN is one of the largest existing European research projects in semiconductor development. The €48m in funding consists of investment by industry, subsidies from the individual participating countries and the Electronic Components and Systems for European Leadership (ECSEL) Joint Undertaking (JU).

Efficient use of energy for climate protection

“By developing intelligent technologies, we are making a key contribution to the global challenge of climate change,” says Aixtron president Dr Felix Grawert. “New materials and efficient chip solutions play a key role here. With this research project, we are creating the conditions for making innovative energy-saving chips available for many future-oriented everyday applications,” he adds.

“Gallium nitride semiconductor devices are revolutionizing energy use on many levels,” says professor Michael Heuken, Aixtron’s VP Research & Development. “The research project opens up an enormous global market potential,” he adds. “It enables better performance and efficiency in a wide range of applications and significantly improves user comfort. Efficient operation of servers and data centers, fast and wireless charging of smartphones, data exchange between machines in real time, or lightning-fast video streaming become reality.”
Source: Semiconductor Today LINK

Wednesday, January 2, 2019

IEDM 2018 Imec on Interconnect Metals Beyond Copper

At IEDM in December 2018 Imec presented recent results from their interconnect program “Interconnect metals beyond copper – reliability challenges and opportunities”, which was recently covered by Scotten Jones (SemiWiki).

The electrical current in interconnect lines haven’t scaled down as fast as the lines' cross sectional area, which has enhanced the current density in the lines. Initial wide aluminum (Al) interconnects were first replaced by narrower aluminum-copper (AlCu) alloys and eventually by Cu to reduce the interconnects line resistance. Now even Cu needs to be replaced by alternate materials for the narrowest lines due to the following limits:

  • Higher resistivity with shrinking line width – below 20nm exponential increase in line resistance.
  • Via resistance also goes up strongly due to the liner.
  • Thinner lines see more grains from electroplating – around 10nm line can’t meet electromigration.
Imec commenced their work on alternative materials for M0 and M1 interconnects by screening based on the two metrics—resistivity multiplied by electron mean free path and melting point. The work reflects Rhodium and Iridium as the best candidate materials for the lowest interconnects that can be reasonably integrated. Ruthenium (Ru) and Cobalt (Co) exhibit similar performance. These materials can be deposited using ALD, CVD or electroplating. Co needs a thin adhesion layer but not a barrier layer. Ru also doesn’t require any seed or barrier layer. Imec is still working on reliability tests of these materials.

Meanwhile, TSMC has been using Co capping on Cu interconnects since 16 nm due to improved electromigration. Co (TSMC) and Ru (Intel) seed layers were introduced. Intel has introduced Co contacts at 10 nm and TSMC at 7 nm. Intel has also introduced Co interconnects for metals 0 and 1 at 10 nm.

Source: SemiWiki, Scotten Jones : LINK
By Abhishekkumar Thakur

Friday, November 16, 2018

4th Area Selective Deposition (ASD) workshop April 4th – 5th, 2019 in IMEC

[Announcment LINK] ASM and IMEC are proud to announce that the 4th Area Selective Deposition (ASD) Workshop will be held on April 4th – 5th, 2019 in IMEC, Leuven (Belgium).

News tip by Henrik Pedersen - Tack så mycket

This workshop will bring together leading experts from both academia and industry to share their vision and results about: fundamental aspects of surface chemistry, new processes, metrology, fields of applications, technology needs and integration challenges for ASD. Based on a series of successful workshops at the North Carolina State University in 2018, Eindhoven University of Technology in 2017 and at IMEC in 2016, the two-days program will include invited and contributed speakers, a poster session and a reception on the evening of April 4th.

Friday, November 9, 2018

Imec to present scaled Superduper High-k Ruthenium/Strontium titanate capacitor at IEDM

Here is another interesting IEDM 2018 paper from Imec. It is a classical paper obn DRAM capacitor scaling featuring the almost impossible Superduper High-k Ruthenium/Strontium titanate capacitor! It is an ALD integration, the patterning the capacitor everything - no need to involve anyone else - it is up to the Litho and ALD people to get the job done.

Paper #2.7, "High-Performance (EOT<0.4nm, Jg~10-7 A/cm2) ALD-Deposited Ru/SrTiO3 Stack for Next-Generation DRAM Pillar Capacitor," M. Popovici et al, Imec)

I have not seen the abstract but it has been reviewed by CDRInfo (see paragraph below) and I am sure there will be more details available soon (LINK):

"Scaling DRAM Technology To 16nm And Beyond: DRAM memory technology is used in virtually all electronic systems because of its speed and density. DRAM memory comprises arrays of capacitor-transistor pairs which store data as electrical charge in the capacitor; the presence of charge indicates "1" and its absence "0." Manipulation of these digits is the basis of computer programming. It’s difficult to scale DRAM to the 16nm generation and beyond because of space limitations which make it hard to pack enough capacitance within the pitch. Imec researchers used an atomic layer deposition (ALD) process to pattern and build a novel 11nm pillar-shaped capacitor using new dielectric materials (SrTiO3, or STO). By tailoring the material properties of the capacitor and the SrRuO3 (SRO) epitaxial template on which it was grown, the researchers achieved a very high dielectric constant (k~118) and low electrical leakage (10-7 A/cm2 at ±1V). This means that pillar-shaped capacitors can be used instead of existing cup-shaped capacitors, without paying too great a penalty in terms of reduced data-storage capability. These results make the STO capacitors suitable for continued scaling for 16nm and smaller DRAMs."
Construction work at Imec, Leuven, June 2013. The tower looks a bit like a DRAM Capacitor but somehow I do not think that the architect know that and I bet they were working on Ru/STO ALD well before that!

Imec to present Highest-Density 3DS Stacked FinFETs at IEDM 2018

Here is an interesting paper to be presented by Imec at the upcoming IEDM 2018 in San Fransisco. Imec has managed to stack the complete FinFET front end module on top of a "standard" bulk silicon FinFET Module demonstrating also good threshold voltage tuning, reliability and low-temperature performance. 

So just imagine if this would be used in high volume manufacturing - it would mean that all those ALD processes used in patterning and for the high-k metal gate module, spacers, local interconnect etc. etc. would come twice meaning a 2X need for ALD process chambers. And lets say you can run this twice - is there any reasons why you can´t run it yet another time? Woah!

Also as a note, Imec is here using a LaSiOx layer an a dipole inserted in the HKMG stack - presumably it is an ALD process since it will have to conformally coat this fins and ensure precise thickness control and uniformity.

So just enjoy seeing double - it is Friday!

Paper #7.1, “First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec

Highest-Density 3DS Stacked FinFETs: Imec researchers will report on 3D stacked FinFETs that have the tightest pitches ever reported in such a stacked architecture – 45nm fin pitch and 110nm gate pitch. The 3D architecture makes use of a sequential integration process yielding tight alignment between very thin top and bottom Si layers. The junction-less devices in the top layer were fabricated and transferred using low-temperature (≤525ºC) processes to avoid performance degradation, and a 170nm dielectric was used to bond the two wafers. The top layer is so thin that the bottom layer could be patterned right through it by means of 193nm immersion lithography, which connects the two via local interconnect. The researchers evaluated various gate stacks, ultimately choosing TiN/TiAl/TiN/HfO2 with a LaSiOx dipole inserted into the stack. The combination demonstrated good threshold voltage tuning, reliability and low-temperature performance.

At left above is a cross-sectional electron microscope image of the fabricated 3D stacked FinFETs along fins and across gates, showing the tight alignment achieved by the top processed layers (Gate Li1, Li2) toward the bottom layers. At right is a cross-sectional image of the final devices across fins with the gates covering the fins.

“First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec (IEDM 2018 Press kit)

Source: IEDM Press kit (LINK)

Tuesday, October 23, 2018

Imec and ASML Enter Next Stage of EUV Lithography Collaboration

Intensified collaboration will advance high-volume production with current EUV lithography and develop future EUV systems

LEUVEN (Belgium) & VELDHOVEN (The Netherlands), OCTOBER 22, 2018 (LINK) —Today, world-leading research and innovation hub in nanoelectronics and digital technologies imec, and ASML Holding N.V. (ASML), the technology and market leader in lithographic equipment, announce the next step in their extensive collaboration. Together, they will accelerate the adoption of EUV lithography for high-volume production, including the current latest available equipment for EUV (0.33 Numerical Aperture, NA). Moreover, they will explore the potential of the next-generation high-NA EUV lithography to enable printing of even smaller nanoscale devices advancing semiconductor scaling towards the post 3 nanometer Logic node. To this end, they will establish a joint high-NA EUV research lab.

Imec and ASML have been conducting joint research for almost thirty years. In 2014, they created a joint research center, the Advanced Patterning Center, to optimize lithography technology for advanced CMOS integration and to prepare the ecosystem to support advance patterning requirements. Now, they bring this cooperation to the next stage with the installation of ASML’s most advanced and high-volume production dedicated EUV scanner (NXE:3400B) in imec’s cleanroom. Utilizing imec’s infrastructure and advanced technology platforms, imec and ASML researchers and partner companies can pro-actively analyze and solve technical challenges such as defects, reliability and yield, and as such accelerate the EUV technology’s industrialization.

Wednesday, June 6, 2018

Imec Extends Damascene Metallization Towards the 3nm Technology Node

LEUVEN, June 4, 2018 – At this week’s 2018 IEEE International Interconnect Technology Conference (IITC 2018), imec, the world-leading research and innovation hub in nanoelectronics and digital technology, will present 11 papers on advanced interconnects, ranging from extending Cu and Co damascene metallization, all the way to evaluating new alternatives such as Ru and graphene. After careful evaluation of the resistance and reliability behavior, imec takes first steps towards extending conventional metallization into to the 3nm technology node.

For almost two decades, Cu-based dual damascene has been the workhorse industrial process flow for building reliable interconnects. But when downscaling logic device technology towards the 5nm and 3nm technology nodes, meeting resistance and reliability requirements for the tightly pitched Cu lines has become increasingly challenging. The industry is however in favor of extending the current damascene technology as long as possible, and therefore, different solutions have emerged. 
Via resistance for Co, Cu, Ru (left); and comparison of damascene line resistance versus total conductor cross-sections area of Ru, Co and Cu nanowires (right)
To set the limits of scaling, imec has benchmarked the resistance of Cu with respect to Co and Ru in a damascene vehicle with scaled dimensions, demonstrating that Cu still outperforms Co for wire cross sections down to 300nm2 (or linewidths of 12nm), which corresponds to the 3nm technology node. To meet reliability requirements, one option is to use Cu in combination with thin diffusion barriers such as tantalum nitride (TaN)) and liners such as Co or Ru. It was found that the TaN diffusion barrier can be scaled to below 2nm while maintaining excellent Cu diffusion barrier properties.

For Cu linewidths down to 15–12nm, imec also modeled the impact of the interconnect line-edge roughness on the system-level performance. Line-edge roughness is caused by the lithographic and patterning steps of interconnect wires, resulting in small variations in wire width and spacing. At small pitches, these can affect the Cu interconnect resistance and variability. Although there is a significant impact of line-edge roughness on the resistance distribution for short Cu wires, the effect largely averages out at the system level.

An alternative solution to extend the traditional damascene flow is replacing Cu by Co. Today Co requires a diffusion barrier – an option that recently gained industrial acceptance. A next possible step is to enable barrierless Co or at least sub-nm barrier thickness with careful interface engineering. Co has the clear advantage of having a lower resistance for smaller wire cross-secions and smaller vias. Based on electromigration and thermal storage experiments, imec presents a detailed study of the mechanisms that impact Co via reliability, showing the abscence of voids in barrierless Co vias, demonstrating a better scalability of Co towards smaller nodes. The research is performed in cooperation with imec’s key nano interconnect program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, SanDisk/Western Digital, Sony Semiconductor Solutions, TOSHIBA Memory and TSMC.

Monday, January 22, 2018

Imec present roadmap down to 20 Ångström logic devices

From now on I think that it is time to start using Ångström instead of Nanometer (nm) when talking about leading edge CMOS and Memory.  At SEMI:s ISS 2018 (Industry Strategy Symposium) last week Luc van den Hove, Chief Executive Officer and President of Interuniversity MicroElectronics Center (IMEC) presented their roadmap for what future Logic nodes might look like going down to 2 nm that is 20 Ångström.

Key interconnect technologies named "scaling boosters" to reach down to 2 nm may be :
  • Continued scaling of self-aligned contacts
  • Cobalt "Super Via" 20 nm wide
  • Burried Ruthenium Rails only 10 nm wide, which seems to be a evolution of the tungsten burried Word Lines and Bitlines introduced by Qimonda for DRAM (65nm in 2009) except offcourse these rails are burried in a dielectric which will  make it stackable. 

Imec Logic roadmap and technologies, Picture from Twitter (LINK)

Besides the interconnect technologies the presentation showed evolution from FinFETs to nanowire FETs and Imecs latest technology development in 300 mm wafer processing technology:
  • Introduction of triple pattering (Much More ALD!)
  • EUV Litography and the introduction Carbon Nano Tube CNT Pellicle for EUV mask protection
  • Smoothening technology in patterning like Atomic Layer Etching for improving the local critical dimension uniformity (LCDU) down from 2.7 to 1.4 nm
In the case of memory technology Imec now focuses on 4 non-volatile types of memory cells besides DRAM and 3DNAND Flash:
  • STTRAM - spin transfer torque magnetoresistive random-access memory
  • RRAM - resistive random-access memory
  • FeRAM - ferroelectric random-access memory (should be renamed DD-RAM for Dresden)
  • SOTRAM - Spin Orbit Torque random-access memory

Wednesday, June 7, 2017

Another breakthrough in CMOS-compatible ferroelectric memory

Imec, the world-leading research and innovation hub in nanoelectronics and digital technology, announced today at the 2017 Symposia on VLSI Technology and Circuits the world's first demonstration of a vertically stacked ferroelectric Al doped HfO2 device for NAND applications. Using a new material and a novel architecture, imec has created a non-volatile memory concept with attractive characteristics for power consumption, switching speed, scalability and retention. The achievement shows that ferro-electric memory is a highly promising technology at various points in the memory hierarchy, and as a new technology for storage class memory. Imec will further develop the concept in collaboration with the world's leading producers of memory ICs.

Full story : LINK

Tuesday, July 14, 2015

Advanced Metallization Scheme for 3 x 50 um TSV Middle Process – IMEC

Here are some highly interesting insights to the latest Imec process technology for TSVs using a number of advanced Lam Research processing platforms including ALD - As reported by Solid State Technology, By Dr. Phil Garrou, Contributing Editor (I spiced it up with some nice Lam  Research chamber pictures): 

Scaling down the TSV diameter from 5μm to 3μm is very attractive for the 3D IC implementation in more advanced CMOS nodes. For instance, stress caused by the mismatch between the coefficient of thermal extension (CTE) of Si and Cu may generate strain in the Si around the TSV, degrading the device performance of transistors located close to a TSV. To reduce the impact on transistors, a so called keep-out-zone (KOZ), is generally defined around the 3D TSVs. This keepout-zone is however significantly smaller when scaling down the TSV diameter from 5μm to 3μm. When increasing the aspect ratio of the TSV from 10:1 to 17:1 (for 3μm diameter and 50μm depth), the conventional PVD barrier and seed options reach their conformality limits. Very thick barrier/seed layers need to be deposited in order to assure a continuous film at the bottom of the TSV. This not only fundamentally limits the extendibility of this integration scheme, but also increases the PVD deposition cost itself and the required CMP time, among other technical challenges. For these reasons, a new advanced and scalable TSV metallization scheme was developed.

Atomic layer deposition (ALD) has emerged as a key enabling technology for conformal film applications such as TSV oxide liner. Typical step coverage or conformality of other CVD oxide films is only 60-75% for high aspect ratio TSVs . In contrast, the VECTOR ALD oxide film shows 100% con formality.

Lam Research VECTOR ALD process chambers (

ALD WN serves as a barrier layer and is deposited on the Altus Max tool. It is highly conformal with >90% step coverage regardless of geometry. ALD WN is deposited at 375°C and has excellent adhesion to ALD oxide and subsequent ELD NiB. The conformality of the ALD process results in a pinhole-free WN layer, as opposed to barriers deposited by PVD, which potentially struggle with pinholes at the bottom of high aspect ratio TSV.

Lam Research Altus Max Chambers (

NiB electroless deposition on WN barrier was carried out on a Lam ELD2300 tool using a plating chemistry developed at Lam. The entire deposition process was made of several sequential steps such as a brief pre-clean, activation, deposition, rinse and dry. The concentration of reducing agent and nickel ions as well as the pH and temperature are controlled to maintain optimum deposition condition for seed formation during the NiB deposition. After deposition of ELD NiB, TSV copper electrofill is processed on a Lam SABRE 3D electroplating system using an industry standard acid copper sulfate electrolyte with a Lam

Lam Research SABRE 3D Electroplating system (

exclusive organic additive package. The conductivity and corrosion resistance of the Lam ELD NiB film enable compatibility with the electrofill process on 300mm wafer scale. Bottom-up fill of the vias proceeds without the need for the additional copper seed film that has been used with other conformal metal liners (e.g. Co or Ru).

Because of the high conformality of liner, barrier and seed layers, this proposed Via-middle metallization scheme is believed to be scalable to even higher aspect ratio TSVs with 2μm diameter.