Imec to present Highest-Density 3DS Stacked FinFETs at IEDM 2018

Here is an interesting paper to be presented by Imec at the upcoming IEDM 2018 in San Fransisco. Imec has managed to stack the complete FinFET front end module on top of a "standard" bulk silicon FinFET Module demonstrating also good threshold voltage tuning, reliability and low-temperature performance. 

So just imagine if this would be used in high volume manufacturing - it would mean that all those ALD processes used in patterning and for the high-k metal gate module, spacers, local interconnect etc. etc. would come twice meaning a 2X need for ALD process chambers. And lets say you can run this twice - is there any reasons why you can´t run it yet another time? Woah!

Also as a note, Imec is here using a LaSiOx layer an a dipole inserted in the HKMG stack - presumably it is an ALD process since it will have to conformally coat this fins and ensure precise thickness control and uniformity.

So just enjoy seeing double - it is Friday!

Paper #7.1, “First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec

Highest-Density 3DS Stacked FinFETs: Imec researchers will report on 3D stacked FinFETs that have the tightest pitches ever reported in such a stacked architecture – 45nm fin pitch and 110nm gate pitch. The 3D architecture makes use of a sequential integration process yielding tight alignment between very thin top and bottom Si layers. The junction-less devices in the top layer were fabricated and transferred using low-temperature (≤525ºC) processes to avoid performance degradation, and a 170nm dielectric was used to bond the two wafers. The top layer is so thin that the bottom layer could be patterned right through it by means of 193nm immersion lithography, which connects the two via local interconnect. The researchers evaluated various gate stacks, ultimately choosing TiN/TiAl/TiN/HfO2 with a LaSiOx dipole inserted into the stack. The combination demonstrated good threshold voltage tuning, reliability and low-temperature performance.

At left above is a cross-sectional electron microscope image of the fabricated 3D stacked FinFETs along fins and across gates, showing the tight alignment achieved by the top processed layers (Gate Li1, Li2) toward the bottom layers. At right is a cross-sectional image of the final devices across fins with the gates covering the fins.

“First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec (IEDM 2018 Press kit)

Source: IEDM Press kit (LINK)