Showing posts with label High-k. Show all posts
Showing posts with label High-k. Show all posts

Thursday, April 8, 2021

ALD/CVD Metal Precursors US$640M Market Booming to US$910M in 2024

San Diego, CA, April 1, 2021: TECHCET—the electronic materials advisory firm providing business and technology information—announces that the global market for atomic layer deposition (ALD) and chemical vapor deposition (CVD) metal precursors for semiconductor manufacturing in 2020 was worth ~US$640M. Driven by advanced logic and 3D-NAND memory chip fabrication needs, demand for ALD and CVD metal precursors is forecast to see a 2020-2024 compound annual growth rate (CAGR) of ~10% as shown in the Figure (below) from the most recent quarterly update to TECHCET's Critical Materials Report (CMR) on CVD, ALD, and SOD Precursors.

All ALD/CVD metal precursors are in healthy demand since ALD is critical for fabs running 22-45nm nodes as well as for fabs at the leading edge. In particular, cobalt (Co) and hafnium (Hf) precursors saw 18-20% year-over-year (YoY) growth in 2020, and are forecasted to see strong demand through 2024.

Critical Materials Reports™ and Market Briefings:

For more information:

Saturday, March 6, 2021

ASM International confirms that ALD HKMG is in High Volume Manufacturing for DRAM - The 2nd Switch is on!

I get this question continuously and also use it for modeling the high-k precursor forecast as provided by TECHCET - has ALD High-k/Metal Gate stacks moved into DRAM peripheral transistors?

When at Qimonda (R.I.P) we developed a HfSiO process or the peripheral Logic and qualified a number of OEMs for this one including ASM Pulsar 3000, Jusung Cyclone+ Spatial ALD, and TEL Furnace ALD. ASM has since Intel 45 nm been the leader in the HKMG module. Later they also fended off the competition from Applied Materials and Tokyo Electron MOCVD option trying to enter the foundries that were just too hot for the integration moving to lower thermal budgets. 

So now finally I can give an answer with a public reference to the question - yes ALD is in HVM for DRAM HKMG peripheral transistors! The Switch is on also for DRAM - have a nice weekend!

Benjamin Loh (ASMI CEO), answers on financial analyst question about if ASM has ALD tools in the field for DRAM high-k/metal gate:

"Mark thanks. So, of course, first of all, maybe let's talk about the memory parts of, in DRAM we started quite some time ago, we have been qualified for the high-k/metal gate in the DRAM periphery transistor. So right now, what you see for example, and what is called in the industry as high-performance DRAM. I think they are using our ALD for the mass for the high-volume manufacturing." 

Please find the full Q4/2020 investor call transcript here provided by Seeking Alpha: LINK (you have to create a profile to get full access)

TEM images of (A) 30 nm and (B) 65 fin height, of 15nm fin width, as used in a recent Imec study of HKMG FinFETs for peripheral DRAM Logic. DOI: 10.1109/IIRW47491.2019.8989914 Conference: IEEE International Integrated Reliability Workshop, IIWR'19 At: Stanford Sierra Conference Center Fallen Leaf Lake Tahoe, CA, USA

ASM’s Pulsar uses ALD to deposit the high-k dielectric materials required for advanced CMOS transistor gates ​and other applications. Pulsar is the benchmark ALD high-k tool for the industry. It was the first ALD system to be used for high-volume production at advanced customers for high-k metal gate transistors. (

Thursday, October 15, 2020

Swedish NordAmps has developed InGaAs nanowire transistors with GAA high-k/metal gate

NordAmps in Lund, Sweden, has developed InGaAs nanowire transistors with GAA high-k /metal gate (HKMG) capable of the high frequencies required for 5G and 6G data transfer and logic data processing, with significantly lower energy consumption.

The structures are fully compatible with a standard 300 mm standard Si CMOS flow and require less mask steps compared with conventional technology.

NordAmps represents the convergence of research by global leaders in nanotechnology with leading edge application needs. 

Source: NordAmps LINK




Tuesday, May 19, 2020

Hafnium, Zirconium: Australian Strategic Materials a step closer to completing commercial pilot plan

Recent semiconductor materials related trade issues between Japan and South Korea have led South Korea to secure alternative sourcing of photoresists and metals for their semiconductor industry. This includes essential minerals for hafnium and zirconium ALD precursors that are used in the manufacturing of DRAM and Foundry logic at SK Hynix and Samsung fabs.

Besides the tension with Japan, China's dominance in the supply of zirconium chemicals and materials has highlighted the additional risk in the critical materials supply change for its important semiconductor and high tech industries.

One such action has been setting up a pilot plant in South Korea for hafnium and zirconium metal in joint development with Australias Alkane and its subsidiary Australian Strategic Materials (ASM). The joint undertaking has now moved to the next phase for a commercial operation of a pilot plant as reported by Alkaine below.

Australian Strategic Materials a step closer to completing commercial pilot plan

Australian Strategic Materials (ASM), a wholly owned subsidiary of Alkane Resources is getting closer to completing the construction of a commercial pilot plant facility in South Korea that will enable critical metal oxides, including zirconium and hafnium, to be converted into metals in clean, carbon-free way.

As the Covid-19 pandemic continues to highlight weaknesses in critical minerals supply chains globally, ASM has confirmed in Alkane Resources' quarterly recently it has received interest in both potential future supply and partnership from a number of parties in South Korea and elsewhere. ...

Read more.

Read more about previous blog about the Alkane Dubbo project in New South Wales, Austrailia:

The Dubbo Project - The High-k mine in Dubbo, NSW Australia

Hafnium product breakthrough consolidates Dubbo Project business case

China’s water crisis stems the flow of zirconium and rare earths for global industries

Alkane Resources reports that zirconium oxychloride (ZOC) prices are up 40% since January 2017

Monday, May 18, 2020

IBM has adopted 14 nm FD-SOI FinFET with an ALD deep trench capacitor as eDRAM for its Power9 Processor

EET Asia reports that IBM has adopted 14 nm FD-SOI FinFET combined with a deep trench capacitor for eDRAM L3 cache memory for its Power9 Processors. Thes enables an ultra-dense eDRAM cell array and reportedly IBM is aiming to scale down the next-generation Power10 to 10 nm or even 7 nm for more performance improvement and latency reduction.

Some of the goodiesfabed at Globalfoundries (14HP FD-SOI, I am assuming Fab Malta NY, USA) include:
  • 3rd HKMG eDRAM
  • 1st FinFET eDRAM with RMG
  • 4th Deep Trench Capacitor (DTC) eDRAM
  • 0174 µm2 SOI DRAM bit cell with 8F2
  • DTC eDRAM cell capacitance (estimated) ~8.1 fF/cell with ULK HfO/SiON high-k dielectrics and DTC depth 3.5 µm
  • DTC process for both cell capacitors and decoupling capacitors
  • Dual epitaxial layers for eSiC (eDRAM cell word lines and NMOS gates) and eSiGe (PMOS Gates)
  • 17 metal levels in total (excluding Al UBM connection layer)
  • 64 nm 1X M1 through M5 pitch, 2X M6 through M9, and 4X M10 and M11
  • ULK dielectrics for M1 through M9 ILDs, while LK ILDs for M10 through M15
So this is a pretty cool chip using a HfO2 ALD dielctric twice, and I am assuming that the high aspect ration deep rench capacitors is done using a MO-Hf precursor like TEMHf or similar and the HKMG FinFET high-k in a standar ASM Pulsar 3000 chamber using HfCl4. Then the metal electrodes for the DRAM capacitors ar TiN using Batch ALD or pulsed CVD process mode. COuld also be TEL Trias SFD-style process like Qimonda (R.I.P.) would have done it. As for the Metal Gates for the FinFET also ALD based as commonly done in the foundry industry.

Please finde here the link to the article presents a summary of an analysis performed by TechInsights on the IBM 14HP HKMG FD-SOI FinFET eDRAM cell architecture, process, and design recently used in the IBM Power9 processor.


DT capaciror (Wikichip)

Saturday, January 11, 2020

A comparasion of Hafnium and Zirconium ALD precursor comparison

Here is a very nice review paper from Uwe Schröder and co-workers at NaMLab in Dresden on comparing Hafnium and Zirconium ALD precursors published in the past decades and the selection for mixed HfO2 and ZrO2 ALD high-k and ferroelectric applications.

HfxZr1 − xO2 thin films for semiconductor applications: An Hf- and Zr-ALD precursor comparison editors-pick

Journal of Vacuum Science & Technology A 38, 022402 (2020);
Monica Materano, Claudia Richter, Thomas Mikolajick, and Uwe Schroeder
In the last few years, hafnium oxide (HfO2), zirconium oxide (ZrO2), and their intermixed system (HfxZr1 − xO2) have aroused more and more interest due to their outstanding properties in the frame of semiconductor applications. Different mixtures of these two sister materials, i.e., different Hf:Zr ratios in HfxZr1 − xO2 layers, as well as different crystal arrangements come with a wide set of structural and electrical properties, making this system extremely versatile. Starting from an amorphous layer, the different crystalline phases are easier to be targeted through subsequent thermal treatment. A correct understanding of the deposition process could help in obtaining films showing the addressed material properties for the selected application. In this paper, a comparison of Hf- and Zr-atomic layer deposition precursors is conducted, with the goal of depositing an almost amorphous HfxZr1 − xO2 layer. Material composition is tuned experimentally in order to address the properties that are relevant for the semiconductor industry. The observed trends are examined, and guidelines for applications are suggested. 

Growth per cycle for the most common HfO2 metal precursors as a function of deposition temperature. Except for the Hf[N(CH3)(C2H5)]4 precursor used in this work, the data have been extracted from other sources. (Reference for HfI4-O2 is wrong, should read ref. 28.)

Thursday, January 2, 2020

Picosun’s ALD technology enables 3D silicon-integrated microcapacitors with unprecedented performance

ESPOO, Finland, 2nd January 2020 (LINK) – Picosun Group, global provider of leading AGILE ALD® (Atomic Layer Deposition) thin film coating solutions, reports record performance of silicon-integrated, three-dimensional deep trench microcapacitors manufactured using its ALD technology.

Increasing efficiency and performance demands of portable and wearable electronics, along with their shrinking size in accordance with the Moore’s law, set new challenges to the power management of these devices as well. A solution is further integration of the devices’ key components into so-called SiP (systems-in-package) or SoC (systems-on-chip) architectures, where everything, including the energy storage such as batteries or capacitors, is packed close to each other into one compact, microscale-miniaturized assembly. This calls for novel techniques to increase the performance and shrink the size of the energy storage unit as well. Three-dimensional, high aspect ratio and large surface area deep trench microcapacitors where ultra-thin, alternating layers of conducting and insulating materials form the energy storing structure, provide a potential solution.

Figures above: Main technological steps of 3D microcapacitor fabrication. 1: patterning of a square lattice of holes on the silicon surface; 2: high aspect ratio trenching of silicon by electrochemical micromachining (ECM); 3: atomic layer deposition (ALD) of conformal metal-insulator-metal (MIM) stack; 4: aluminium deposition and contact patterning (*).

Picosun’s ALD technology has now realized unprecedented performance of these 3D microcapacitors. PICOSUN® ALD equipment were used to deposit film stacks of conductive TiN and insulating dielectric Al2O3 and HfAlO3 layers into high aspect ratio (up to 100) trenches etched into silicon. Up to 1 µF/mm2 areal capacitance was obtained, which is the new record for this capacitor type. Also power and energy densities, 566 W/cm2 and 1.7 µWh/cm2, were excellent and surpassing the values achieved with the most of the other capacitor technologies. The ALD microcapacitors showed also outstanding voltage and temperature stability, up to 16 V and 100 oC, over 100 hours continuous operation (*).

Figures above: b) SEM cross-section of an array of cylindrical trenches with a pitch of 4 μm, diameter of 2 μm and aspect ratio of 100, conformally coated with an ALD stack consisting of 40 nm of TiN, 40 nm of Al2O3, and 40 nm of TiN. Insets show a detail of the MIM stack at the top and bottom of a single trench; d) high-resolution TEM image of an MIM stack consisting of 40 nm of TiN, 40 nm of Al2O3, and 40 nm of TiN taken at the bottom of ALD-coated trenches with aspect ratio of 100; e) TEM-EDX elemental maps of Ti (yellow), N 14 (cyan), Al (red), and O (green) of the MIM stack in (d) (*).

These excellent performance indicators pave the way to industrial applications of this capacitor technology. This is further facilitated by ALD’s mature position in modern semiconductor industries, where the technology is already integrated into practically all advanced microchip component manufacturing lines.

“We exploited the room available on the bottom of silicon wafers, of which only a few micrometers of silicon are used for electronic components in integrated circuits, to fabricate silicon-integrated 3D microcapacitors with unprecedented areal capacitance. The electrochemical micromachining technology, developed at the University of Pisa over the past decade, enabled etching of high density trenches with aspect ratios up to 100 in silicon, a value otherwise not achievable with deep reactive ion etching. This posed the basis for increasing the areal capacitance of our 3D microcapacitors upon conformal coating with an ALD metal-insulator-metal stack,” says Prof. Giuseppe Barillaro, group leader at the Information Engineering Department of the University of Pisa, Italy.

“The suberb results achieved with our 3D silicon-integrated microcapacitors show again how imperative ALD technology is to modern microelectronics. We are happy that we can offer our unmatched expertise and decades of cumulative know-how in the field to develop novel solutions for the challenges the industry is facing, when the requirements for system performance and integration level increase inversely to the system size. The environmental aspect is also obvious, when smaller, more compact devices manufactured in the same line mean also smaller consumption of materials and energy,” says Juhana Kostamo, deputy CEO of Picosun Group.
(*) “Three-dimensional silicon-integrated capacitor with unprecedented areal capacitance for on-chip energy storage”, Lucanos M. Strambinib,1, Alessandro Paghia,1, Stefano Mariania, Anjali Soodc, Jesse Kalliomäkic, Päivi Järvinenc, Fabrizio Toiad, Mario Scuratid, Marco Morellid, Alessio Lampertie, Giuseppe Barillaroa,b,, accepted for publication in Nano Energy,
a Dipartimento di Ingegneria dell’Informazione, Università di Pisa, via G. Caruso 16, 57122, Pisa, Italy
b Istituto di Elettronica e di Ingegneria dell’Informazione e delle Telecomunicazioni, Consiglio nazionale delle Ricerche, via G. Caruso 16, 57122, Pisa, Italy
c Picosun Oy, Tietotie 3, Espoo, FI-02150, Finland
d ST Microelectronics, via Olivetti 1, Agrate Brianza, Italy
e IMM-CNR, Unit of Agrate Brianza, Via C. Olivetti 2, 20864, Agrate Brianza, MB, Italy
(Funding from the ECSEL Joint Undertaking through the R2POWER300 project, grant no. 653933)

Thursday, August 22, 2019

Micron has started volume production of 10 nm-class DRAM (1z nm)

Micron announced on Thursday that it had started volume production of memory chips using its 3rd Generation 10 nm-class fabrication technology (also known as 1Z nm). The first DRAMs to be made using Micron’s 1Z nm process are 16 Gb monolithic DDR4 and LPDDR4X devices. 
The company claims that its 16 Gb DDR4 device consumes 40% less power than two 8 Gb DDR4 DRAMs (presumably at the same clocks). Meanwhile, Micron’s 16 Gb LPDDR4X ICs will bring an up to 10% power saving. One of the first products to use the company’s 16 Gb DDR4 devices will be high-capacity (e.g., 32 GB and higher) memory modules for desktops, notebooks, and workstations.
Source: Anandtech LINK
By Abhishekkumar Thakur

Wednesday, March 6, 2019

Achtung High-k - Novel High-k Workshop 2019 at NaMLab

High k Workshop 2019

NaMLab invites to the Novel High-k Application Workshop on June 11th and 12th, 2019. New challenges offered by the application of high-k dielectric materials in micro– and nanoelectronics were discussed by more than 90 participants from industry, research institutes and universities. 
In this series of annual workshops NaMLab has created a stimulating platform for application-oriented scientists to exchange ideas and discuss latest experimental results on MIM-capacitors, process technology, leakage & reliability as well as characterization of high-k dielectrics integrated in silicon based micro– and nanoelectronics. The ferroelectric properties of doped HfO2 and ZrO2 were discovered more than 10 years ago. On the second day of the workshop, root causes for the formation of this so far unknown phase will be discussed together with the application of these films.
For more information: LINK

Friday, November 9, 2018

Imec to present scaled Superduper High-k Ruthenium/Strontium titanate capacitor at IEDM

Here is another interesting IEDM 2018 paper from Imec. It is a classical paper obn DRAM capacitor scaling featuring the almost impossible Superduper High-k Ruthenium/Strontium titanate capacitor! It is an ALD integration, the patterning the capacitor everything - no need to involve anyone else - it is up to the Litho and ALD people to get the job done.

Paper #2.7, "High-Performance (EOT<0.4nm, Jg~10-7 A/cm2) ALD-Deposited Ru/SrTiO3 Stack for Next-Generation DRAM Pillar Capacitor," M. Popovici et al, Imec)

I have not seen the abstract but it has been reviewed by CDRInfo (see paragraph below) and I am sure there will be more details available soon (LINK):

"Scaling DRAM Technology To 16nm And Beyond: DRAM memory technology is used in virtually all electronic systems because of its speed and density. DRAM memory comprises arrays of capacitor-transistor pairs which store data as electrical charge in the capacitor; the presence of charge indicates "1" and its absence "0." Manipulation of these digits is the basis of computer programming. It’s difficult to scale DRAM to the 16nm generation and beyond because of space limitations which make it hard to pack enough capacitance within the pitch. Imec researchers used an atomic layer deposition (ALD) process to pattern and build a novel 11nm pillar-shaped capacitor using new dielectric materials (SrTiO3, or STO). By tailoring the material properties of the capacitor and the SrRuO3 (SRO) epitaxial template on which it was grown, the researchers achieved a very high dielectric constant (k~118) and low electrical leakage (10-7 A/cm2 at ±1V). This means that pillar-shaped capacitors can be used instead of existing cup-shaped capacitors, without paying too great a penalty in terms of reduced data-storage capability. These results make the STO capacitors suitable for continued scaling for 16nm and smaller DRAMs."
Construction work at Imec, Leuven, June 2013. The tower looks a bit like a DRAM Capacitor but somehow I do not think that the architect know that and I bet they were working on Ru/STO ALD well before that!

Imec to present Highest-Density 3DS Stacked FinFETs at IEDM 2018

Here is an interesting paper to be presented by Imec at the upcoming IEDM 2018 in San Fransisco. Imec has managed to stack the complete FinFET front end module on top of a "standard" bulk silicon FinFET Module demonstrating also good threshold voltage tuning, reliability and low-temperature performance. 

So just imagine if this would be used in high volume manufacturing - it would mean that all those ALD processes used in patterning and for the high-k metal gate module, spacers, local interconnect etc. etc. would come twice meaning a 2X need for ALD process chambers. And lets say you can run this twice - is there any reasons why you can´t run it yet another time? Woah!

Also as a note, Imec is here using a LaSiOx layer an a dipole inserted in the HKMG stack - presumably it is an ALD process since it will have to conformally coat this fins and ensure precise thickness control and uniformity.

So just enjoy seeing double - it is Friday!

Paper #7.1, “First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec

Highest-Density 3DS Stacked FinFETs: Imec researchers will report on 3D stacked FinFETs that have the tightest pitches ever reported in such a stacked architecture – 45nm fin pitch and 110nm gate pitch. The 3D architecture makes use of a sequential integration process yielding tight alignment between very thin top and bottom Si layers. The junction-less devices in the top layer were fabricated and transferred using low-temperature (≤525ºC) processes to avoid performance degradation, and a 170nm dielectric was used to bond the two wafers. The top layer is so thin that the bottom layer could be patterned right through it by means of 193nm immersion lithography, which connects the two via local interconnect. The researchers evaluated various gate stacks, ultimately choosing TiN/TiAl/TiN/HfO2 with a LaSiOx dipole inserted into the stack. The combination demonstrated good threshold voltage tuning, reliability and low-temperature performance.

At left above is a cross-sectional electron microscope image of the fabricated 3D stacked FinFETs along fins and across gates, showing the tight alignment achieved by the top processed layers (Gate Li1, Li2) toward the bottom layers. At right is a cross-sectional image of the final devices across fins with the gates covering the fins.

“First Demonstration of 3D Stacked FinFETs at a 45nm Fin Pitch and 110nm Gate Pitch Technology on 300mm Wafers,” A. Vandooren et al, Imec (IEDM 2018 Press kit)

Source: IEDM Press kit (LINK)

Tuesday, August 28, 2018

Stress-free ALD High-k from Picosun

ESPOO, Finland, 28th August, 2018 – Picosun Group, a leading supplier of advanced Atomic Layer Deposition (ALD) thin film coating solutions, reports a method to control and eliminate stress in ALD films.

Various stresses are easily formed in ALD films during the deposition process, either inside the film or between the film and the underlying substrate. As all modern microelectronic devices are basically built by stacking ultra-thin layers of various materials on top of each other, these stresses can be detrimental not only to the film itself but to the other functional layers and structures beneath. Especially in MEMS devices, where cavities and free-standing membranes are often employed, stress-free ALD films, or films where the stress is exactly controlled, are very much sought after. Same applies for IC components, where film strains and tensions can lead to material layers detaching from each other, or bending and buckling of the whole structure. 
Picosun has now developed a method with which zero stress and controlled stress ALD films can be produced. This sophisticated method is based on intricate tuning of process chemistry and deposition conditions. The desired effect is obtained with right selection of precursor chemicals and process temperature, so no additional process steps such as heat or plasma treatments (which might cause structural damage to the film) are required. Replacing a single material film with carefully designed nanolaminate of materials with opposite stress properties is another way to achieve zero stress layers. These methods have been validated with e.g. HfO2, which is one of the key materials in microelectronics industry. Other ALD materials tested include SiO2, Ta2O5, and TiO2 (*). 

“We are very pleased that we can now offer stress-free ALD HfO2 process to our customers in MEMS and IC industries. Especially medical MEMS is an important market for us, and a prime example of an application area where controlled stress ALD films are needed to enable a whole platform of novel products. Thanks to our unmatched ALD expertise, we have now developed a solution to one of the fundamental challenges in ALD. This will facilitate the implementation of ALD to yet new, exciting applications in health technology and future IC manufacturing,” summarizes Dr. Jani Kivioja, CTO of Picosun Group.

Thursday, April 5, 2018

FREE webinar: Optimising ALD high-k oxides for novel applications

FREE webinar: Optimising ALD high-k oxides for novel applications, 19 April 2018, 15:50 UTC [LINK]

Dr Harm Knoops and special guest speaker, Dr Uwe Schroeder, Deputy Scientific Director from NaMLab GmbH Dresden, Germany, will talk you through the ALD of ferroelectric HfO2 for novel memory applications and the tuning properties of TiO2 and HfO2 by substrate biasing during Plasma ALD.

The webinar will comprise of two talks, with a Q&A session at the end. Register here Knoops is the Atomic Scale Segment Specialist  for Oxford Instruments Plasma Technology and holds a part-time researcher position at the Eindhoven University of Technology. His work covers the fields of (plasma-based) synthesis of thin films, advanced diagnostics and understanding and developing plasma ALD and similar techniques. His main goals are to improve and advance ALD processes and applications for Oxford Instruments and its customers. He has authored and co-authored more than 30 technical papers in peer-reviewed journals.  

Dr Uwe Schroeder has held the Deputy Scientific Director position at NaMLab GmbH, Dresden, Germany since 2009. His main research topics are material properties of ferroelectric hafnium oxide and the integration of the material into future devices.

Prior to joining NaMLab, Schroeder was in a Senior Staff Scientist position at Qimonda, previously known as Infineon Technologies (Memory Division) and Siemens Semiconductor before.  At Infineon’s Memory Development Center in Dresden, his research included work on high k dielectric and its integration into DRAM capacitors as a project manager. During this work the so far unknown ferroelectric properties of doped HfO2 based dielectrics were found. He focused on a detailed understanding of these new material properties and their integration into memory devices. 

Schroeder received a Master degree in Physics and a PhD degree in Physical Chemistry field from University of Bonn, Germany including a research visit at UC California, Berkeley and worked at University of Chicago as a post-doctoral researcher.

Wednesday, April 4, 2018

ALD of ZrO2 from zirconium tetraiodide and ozone

Please use the free month at ECS and download this excellent paper by Kaupo Kukli et al on probably the best zirconium ALD precursor in the world - behold the Zirconium tetraiodide (ZrI4)! Previously ZrO2 ALD employing ZrI4 has been proven using H2O, H2O/H2O2 and O2 so now the reies is almost compelte - just O2+ missing.

Wikipedia states "The compound was once prominent as an intermediate in the purification of zirconium metal." Refereing to the van Arkel Process, taht is Pyrolysis of zirconium tetraiodide gas by contact of hot wire and that was the first industrial process for the commercial production of pure ductile metallic zirconium. The process was developed by Anton Eduard van Arkel and Jan Hendrik de Boer in 1925, both Dutch chemists. By many this process is a chemical transport process and it relies on two basic chemical reactiosn at elevated temperatures:
M + 2I2 (>400 °C) → MI4
MI4 (1700 °C) → M + 2I2
... and that´s about all the information you need to go ahead and move on to HVM with this one ;-)

Atomic Layer Deposition of Zirconium Dioxide from Zirconium Tetraiodide and Ozone
Kaupo Kukli, Marianna Kemell, Kenichiro Mizohata, Marko Vehkamäki, Kristjan Kalam, Helena Castán, Salvador Dueñas, Joosep Link, Raivo Stern, Mikko Ritala, and Markku Leskelä
Abstract : ZrO2 thin films were grown by atomic layer deposition using alternate surface reactions of ZrI4 and O3 precursors in the temperature range of 250–400°C to the thickness in the range of 5–100 nm. The films were dense, continuous, and consisted of mixed monoclinic and metastable polymorphs with significant contribution from cubic ZrO2. The ZrO2 films possessed permittivity up to 19. The capacitor structures based on these films also demonstrated tendency to resistive switching behavior. The ZrO2 films exhibited saturative magnetization under external magnetic fields.

Saturday, January 27, 2018

Scaling proven for embedded Super Fast Non-volatile Memory from Dresden

Ferroelectric hafnium oxide and related materials have been developed in Dresden, Germany for over 10 years now. At the IEDM2017 in December Globalfoundries Fab1 and their partners (NaMLab, Fraunhofer and Ferroelectric Memory GmbH) presented their latest results using the Fab1 22nm FDSOI technology with embedded NVM cells embedded as adopted "standard" high-k / metal gate stacks in the front end process module as so called FeFETs.

Previously much of the work was based on Globalfoundries Fab1 28 nm technology so the move to 22 nm really proves that scalig is back to ferroelectric memory technologies as shown on LinkedIn by Prof. Mikolajick (NaMLab) below.. Since the high-k (doped HfO2) is deposited by ALD this technology is scalable also for FinFETs so don´t be surprised if Globalfoundries would soon present also FeFinFETs.

A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond

IEEE Xplore: 25 January 2018 DOI: 10.1109/IEDM.2017.8268425  

Abstract: We show the implementation of a ferroelectric field effect transistor (FeFET) based eNVM solution into a leading edge 22nm FDSOI CMOS technology. Memory windows of 1.5 V are demonstrated in aggressively scaled FeFET cells with an area as small as 0.025 μm2 At this point program/erase endurance cycles up to 105 are supported. Complex pattern are written into 32 MBit arrays using ultrafast program/erase pulses in a 10 ns range at 4.2 V. High temperature retention up to 300 °C is achieved. It makes FeFET based eNVM a viable choice for overall low-cost and low-power IoT applications in 22nm and beyond technology nodes.

Thursday, January 25, 2018

High Dielectric Constant Materials for Nanoscale Devices and Beyond

Here is a nice review on the introduction of high-k materials in the semiconductor industry and a future outlook by Prof. Hiroshi Iwai at Tokyo and Prof. Akira Toriumi Institute of Technology and their partner Prof. Durga Misra at New Jersey Institute of Technology. Thank you for sharing this one Rob Clark! The paper is part of a winter special issue in Interface (by ECS) with focus on "Importance of dielectric science"  and is free for download.

The authors conclude that:
  • The step coverage advantage of atomic layer deposition (ALD and is possible for, high‑k migration to FinFET CMOS technology.
  • The use of high‑k on new semiconductor substrates such as III-V, Ge and 2D materials is currently being investigated and faces many challenges. 
  • The discovery of ferroelectric properties of HfO2 makes it viable for more potential applications.

High Dielectric Constant Materials for Nanoscale Devices and Beyond
Hiroshi Iwai, Akira Toriumi and Durga Misra

Electrochem. Soc. Interface Winter 2017 volume 26, issue 4, 77-81

Abstract: Tremendous progress of CMOS integrated circuits have been conducted by the down-scaling or the miniaturization of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Ten years, ago, the huge direct-tunneling gate leakage current through the thin gate SiO2 film of 1 nm thickness made it impossible to further scale-down the MOSFETs, and replacing the SiO2 by HfO2-based higher-dielectric constant (high-k) material was the solution. In this paper, the history of high-k gate insulator film development and two topics from recent research results regarding ferroelectricity and reliability are described.

Wednesday, November 29, 2017

Transparent flexible capacitors by ALD high-k, ALD AZO and graphene electrodes

Transparent and flexible flat panel displays manufactured on plastic substrates and flexible substrates involve key technologies like ALD manufacturing of transparent electrodes and barriers. In addition, for the pixel-drive circuit of displays, capacitors are used for charging and discharging at very high speed. Having a high capacitance enables also a high color brightness for each pixel. Now researchers at Wuhan University, China has developed an capacitor technology that is has an excellent transparency and flexibility using the latest ALD and graphene processing technology. Please find the Open Access publication below.

In this study used comercially available graphene in the form of single-layer graphene that had been grown by CVD on copper foil from 2D Carbon Tech Inc. LTD, Changzhou, China. The ALD ZrO2 high-k and AZO was grown in an TSF 200 from Beneq.

Transparent and Flexible Capacitors with an Ultrathin Structure by Using Graphene as Bottom Electrodes
by Tao Guo, Guozhen Zhang, Xi Su, Heng Zhang, Jiaxian Wan, Xue Chen, Hao Wu and Chang Liu
Nanomaterials 2017, 7(12), 418; doi:10.3390/nano7120418  (registering DOI) - 28 November 2017
(Left) The schematic diagram of the ultrathin, transparent and flexible capacitors; (Right) The optical transmittance spectra of the capacitors on PEN substrates. The inset shows the optical photograph of the actual capacitor device with the characters “TFS 200” in the background, and the optical transmittance spectra of graphene and capacitors on quartz substrates. 
Ultrathin, transparent and flexible capacitors using graphene as the bottom electrodes were directly fabricated on polyethylene naphthalate (PEN) substrates. ZrO2 dielectric films were deposited on the treated surface of graphene by atomic layer deposition (ALD). The deposition process did not introduce any detectible defects in the graphene, as indicated by Raman measurements, guaranteeing the electrical performances of the graphene electrodes. The Aluminum-doped zinc oxide (AZO) films were prepared as the top electrodes using the ALD technique. The capacitors presented a high capacitance density (10.3 fF/μm2 at 10 kHz) and a relatively low leakage current (5.3 × 10−6 A/cm2 at 1 V). Bending tests revealed that the capacitors were able to work normally at an outward bending radius of 10 mm without any deterioration of electrical properties. The capacitors exhibited an average optical transmittance of close to 70% at visible wavelengths. Thus, it opens the door to practical applications in transparent integrated circuits. Full article

This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (CC BY 4.0).

Monday, November 20, 2017

Annual High-k Workshop 2018 goes on excursion to Wroclaw Poland

This coming year the classic Dresden NaMLab annual High-k Workshop 2018 organized by Dr. Uwe Schröder (ALD2012, Co-Chair) will make an excursion to Wroclaw Poland. The webpage just came online so please check it out for further details on the event.

Conference "High-k oxides by ALD"

Hotel Jasek Premium, Wrocław, Poland, March 7th - 10th, 2018 

In collaboration with the EU COST networking project HerALD, Institute of Physics, Polish Academy of Sciences and Polish Vacuum Society invite you to the next edition of the conference "High-k oxides by ALD", which will be held in Wroclaw, Poland, on March 7-10, 2018. New challenges offered by the application of ALD based high-k dielectric materials in nanotechnology will be discussed by more than 80 participants from industry, research institutes and universities.

The conference is continuation of NaMLab workshops - a stimulating European platform for application-oriented scientists to exchange ideas and discuss latest experimental results on process technology, new results in the field of ALD-grown dielectrics for solar cells, transparent conduction oxides (TCOs), and for silicon based micro- and nano-electronics. The 2018 edition is organized in Poland to increase integration between Eastern and Western Europe countries. 

Beautiful Ostrów Tumski ("Cathedral Island", German: Dominsel) is the oldest part of the city of Wrocław in south-western Poland. It was formerly an island (ostrów in Old Polish language) between branches of the Oder River [Wikipedia].

Friday, September 22, 2017

High-k oxides by ALD Workshop Wroclaw, Poland, on March 7-10, 2018

In collaboration with the EU COST networking project HerALD, Polish Vacuum Society, Institute of Physics, Polish Academy of Sciences invites you to the next edition of the conference "High-k oxides by ALD", which will be held in Wroclaw, Poland, on March 7-10, 2018. New challenges offered by the application of ALD based high-k dielectric materials in nanotechnology will be discussed by more than 80 participants from industry, research institutes and universities.
The conference is continuation of NaMLab workshops - a stimulating European platform for application-oriented scientists to exchange ideas and discuss latest experimental results on process technology, new results in the field of ALD-grown dielectrics for solar cells, transparent conduction oxides (TCOs), and for silicon based micro- and nano-electronics. The 2018 edition is organized in Poland to increase integration between Eastern and Western Europe countries.
Important dates
In 2018 the Conference will take place in Wrocław on
March 7th - 10th (Wednesday evening to Saturday morning).

Early Regisration & payment deadline:
December 15th 2017

Regisration & Abstract submission deadline:
January 12th 2018