Monday, May 18, 2020

IBM has adopted 14 nm FD-SOI FinFET with an ALD deep trench capacitor as eDRAM for its Power9 Processor

EET Asia reports that IBM has adopted 14 nm FD-SOI FinFET combined with a deep trench capacitor for eDRAM L3 cache memory for its Power9 Processors. Thes enables an ultra-dense eDRAM cell array and reportedly IBM is aiming to scale down the next-generation Power10 to 10 nm or even 7 nm for more performance improvement and latency reduction.

Some of the goodiesfabed at Globalfoundries (14HP FD-SOI, I am assuming Fab Malta NY, USA) include:
  • 3rd HKMG eDRAM
  • 1st FinFET eDRAM with RMG
  • 4th Deep Trench Capacitor (DTC) eDRAM
  • 0174 µm2 SOI DRAM bit cell with 8F2
  • DTC eDRAM cell capacitance (estimated) ~8.1 fF/cell with ULK HfO/SiON high-k dielectrics and DTC depth 3.5 µm
  • DTC process for both cell capacitors and decoupling capacitors
  • Dual epitaxial layers for eSiC (eDRAM cell word lines and NMOS gates) and eSiGe (PMOS Gates)
  • 17 metal levels in total (excluding Al UBM connection layer)
  • 64 nm 1X M1 through M5 pitch, 2X M6 through M9, and 4X M10 and M11
  • ULK dielectrics for M1 through M9 ILDs, while LK ILDs for M10 through M15
So this is a pretty cool chip using a HfO2 ALD dielctric twice, and I am assuming that the high aspect ration deep rench capacitors is done using a MO-Hf precursor like TEMHf or similar and the HKMG FinFET high-k in a standar ASM Pulsar 3000 chamber using HfCl4. Then the metal electrodes for the DRAM capacitors ar TiN using Batch ALD or pulsed CVD process mode. COuld also be TEL Trias SFD-style process like Qimonda (R.I.P.) would have done it. As for the Metal Gates for the FinFET also ALD based as commonly done in the foundry industry.

Please finde here the link to the article presents a summary of an analysis performed by TechInsights on the IBM 14HP HKMG FD-SOI FinFET eDRAM cell architecture, process, and design recently used in the IBM Power9 processor.


DT capaciror (Wikichip)

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