Wednesday, December 17, 2014

Picosun Enables ALD Production on Powders

Picosun Oy Logo





Picosun's large scale POCA™ 300 powder cartridge is designed to fit the industry-standard PICOSUN™ P-300 reactor frame. Its patented construction is based on Picosun's successful R&D scale POCA™ 200 powder coating system with which top quality ALD coatings have been manufactured on several types of powderous carriers. These coatings enable applications such as functionalization of catalysts, solid state batteries, and light-emitting phosphors. The POCA™ 300 system is equipped with Picosun's innovative Picovibe™ feature, ensuring highly uniform and conformal ALD film formation around every single particle in the batch.

"ALD opens up new possibilities for next generation material manufacturing in e.g. energy storage, catalyst, pharmacological, and lighting industries. Our POCA™ 300 large scale powder coating system with the Picovibe™ feature meets the ever-increasing demand for efficient particle ALD processing from several of our production customers in various fields of industry," states Juhana Kostamo, Managing Director of Picosun.

Picosun provides the most advanced ALD thin film technology and enables the industrial leap into the future by novel, cutting-edge coating solutions, with four decades of continuous expertise in the field. Today, PICOSUN™ ALD systems are in daily production use in numerous major industries around the world. Picosun is based in Finland, with subsidiaries in USA, China, and Singapore, and a world-wide sales and support network.

Thursday, December 11, 2014

Atomic Layer Lithography - Creation of nanogaps by ALD

A team led by Sang-Hyun Oh of the University of Minnesota is now saying that it has produced SEIRA (surface-enhanced infrared absorption) enhancements as high as 105 for nanogaps just 3 nm across arranged in a dense array of millimetre-long hotspots.

“In our scheme, we create the nanogaps by depositing thin layers of aluminium oxide on the sidewalls of metal patterns using a well known technique called atomic layer deposition,” Oh tells nanotechweb.org. “We can use this technique to control the thickness of the film, which then defines the gap width on the Angstrom scale. And since thin-film deposition is a fast batch process, we can also make dense arrays of nanogaps over an entire wafer in a quick and easy way.”

The researchers use standard photolithography to pattern gold films on a 4 inch silicon wafer. These patterns are conformally encapsulated with a thin alumina spacer using atomic layer deposition (ALD). Next, a silver film is deposited conformally on the pattern, and the whole structure is stripped off from the silicon substrate using UV cured epoxy and a glass slide. f) Cross-sectional schematic of a buried nanocavity. g) Contact mode AFM line scan across a 5 nm nanogap cavity showing a height difference between the gold and silver films due to the 5 nm thick Al<sub>2</sub>O<sub>3</sub> film. h) Photograph of a 4 inch wafer-containing metal stripes after lift-off. Each square is approximately 1.5 by 1.5 mm. i) SEM image of an array of buried nanogaps on a chip. Further zoomed-in images show a single cavity and a 5 nm nanogap on one side of the cavity. j and k) SEM of buried disks and wedges. Courtesy: <i>Nano Lett.</i>

The researchers use standard photolithography to pattern gold films on a 4 inch silicon wafer. These patterns are conformally encapsulated with a thin alumina spacer using atomic layer deposition (ALD). Next, a silver film is deposited conformally on the pattern, and the whole structure is stripped off from the silicon substrate using UV cured epoxy and a glass slide. f) Cross-sectional schematic of a buried nanocavity. g) Contact mode AFM line scan across a 5 nm nanogap cavity showing a height difference between the gold and silver films due to the 5 nm thick Al2O3 film. h) Photograph of a 4 inch wafer-containing metal stripes after lift-off. Each square is approximately 1.5 by 1.5 mm. i) SEM image of an array of buried nanogaps on a chip. Further zoomed-in images show a single cavity and a 5 nm nanogap on one side of the cavity. j and k) SEM of buried disks and wedges. Pictures from: Nano Lett.

Wednesday, December 10, 2014

Intel shows porous silicon 3.5 mF/cm2 super caps using ALD TiN

As reported by Chip Works Blog: For those interested in energy storage, Intel have fabricated porous silicon capacitors (8.2) that can potentially be integrated on-die or onto solar cells, taking advantage of the extreme conformal deposition capabilities of atomic-layer deposition (ALD). The image below shows a top-down view of the porous silicon before and after ALD TiN deposition; the wall of the pore walls get thicker, but the pore structure doesn’t change. Capacitances of up to 3 milliFarads/cm2 are claimed.

IEDM: http://www.his.com/~iedm/program/program.html
Session 8: Sensors, MEMS, and BioMEMS– NEMS and Energy Harvesters

Monday, December 15, 1:30 p.m.
Imperial Ballroom B
Co-Chairs: Rainer Minixhofer, AMS
Kea-Tiong Tang, National Tsing Hua University
2:00 p.m.
8.2 Integrated On-Chip Energy Storage Using Porous-Silicon Electrochemical Capacitors, D.S. Gardner, C.W. Holzwarth, Y. Liu, S.B. Clendenning, W. Jin, B.K. Moon, C.L. Pint, Z. Chen, E. Hannah, R. Chen, C.P. Wang, C. Chen*, E. Mäkilä**, and J.L. Gustafson, Intel Corp., *Florida Int'l Univ., **University of Turku
Capacitors are favored over batteries for energy harvesting and certain energy storage applications. Electrochemical capacitors based on porous-silicon nano¬structures were synthesized and passivated using either ALD TiN or CVD carbon. Highly stable high density capacitances are achieved and are fabricated using silicon process methods with the potential of on-die integration.



8.2 Fig 5_Gardner

Sunday, December 7, 2014

sprayLD - New technique offers spray-on solar power

Dr. Illan Kramer of The Edward S. Rogers Sr. Department of Electrical & Computer Engineering and IBM has invented a new way to spray solar cells onto flexible surfaces using miniscule light-sensitive materials known as colloidal quantum dots (CQDs)—a major step toward making spray-on solar cells easy and cheap to manufacture.

Thumbnail image of graphical abstract

Kramer, I. J., Minor, J. C., Moreno-Bautista, G., Rollny, L., Kanjanaboos, P., Kopilovic, D., Thon, S. M., Carey, G. H., Chou, K. W., Zhitomirsky, D., Amassian, A. and Sargent, E. H. (2014), Efficient 

Spray-Coated Colloidal Quantum Dot Solar Cells. Adv. Mater.. doi: 10.1002/adma.201403281

A colloidal quantum dot solar cell is fabricated by spray coating under ambient conditions. By developing a room temperature spray coating technique and implementing a fully automated process with near monolayer control—an approach termed as sprayLD—an electronic defect is eliminated resulting in solar cell performance and statistical distribution superior to prior batch-processed methods along with hero performance of 8.1%.

Thursday, December 4, 2014

Altatech introduces new Fast ALD Technology

As reported by Soitec - Altatech : Altatech, a division of Soitec, has introduced the AltaCVD 3D Memory Cell(TM), a new member of its AltaCVD product line designed to deposit ultra-thin semiconductor films that enable the manufacturing of high-density, low-power memory ICs used throughout mobile electronics. The new system performs atomic-layer deposition 10 times faster than conventional ALDsystems, helping to meet global market demands for both high-volume production and cost efficiency in fabricating advanced memories.


"The performance of today's pervasive mobile devices, which many of us now take for granted, would not be possible without atomic-layer deposition technology, such as enabled by our newest CVD solution," said Jean-Luc Delcarri, general manager of Soitec's Altatech Division.

As the global semiconductor industry turns to 3D device architectures to increase memory capacity and boost IC performance for mobile applications, advanced material deposition is needed to create atomic-layer films with high uniformity and stoichiometry control. Altatech's AltaCVD 3D Memory Cell can deposit the needed layers of chalcogenide materials by using a combination of precursors.

In addition to working with conventional gaseous or solid precursors, Altatech's new tool uses patented pulsed technology to take advantage of advanced CVD precursors that are available only in liquid form. This versatility allows the system to achieve exceptional step coverage over features with very high aspect ratios, a key performance requirement in creating the vertical integration that enables high-density memory circuits.

The AltaCVD 3D Memory Cell also can perform advanced pre-treatment of semiconductor surfaces to improve circuit functionality as well as post-treatment of surfaces to enhance memory cells' electrical performance.

Designed to process 200-mm or 300-mm substrates, the AltaCVD 3D Memory Cell uses a single-wafer, multi-chamber architecture to deliver both single-wafer process control and volume-manufacturing capability.

The system is currently demonstrating its unique capabilities and performance at one of Altatech's key customers and production units are available.