Showing posts with label III/V. Show all posts
Showing posts with label III/V. Show all posts

Thursday, October 15, 2020

Swedish NordAmps has developed InGaAs nanowire transistors with GAA high-k/metal gate

NordAmps in Lund, Sweden, has developed InGaAs nanowire transistors with GAA high-k /metal gate (HKMG) capable of the high frequencies required for 5G and 6G data transfer and logic data processing, with significantly lower energy consumption.

The structures are fully compatible with a standard 300 mm standard Si CMOS flow and require less mask steps compared with conventional technology.

NordAmps represents the convergence of research by global leaders in nanotechnology with leading edge application needs. 

Source: NordAmps LINK




Saturday, February 13, 2016

TSMC Belgium & Sweden demonstrate first un-strained InAs FinFETs

Researchers led by TSMC R&D Europe B.V. in Leuven Belgium (Imec) and Lund Sweden (Lund Nano Lab), claim the first demonstration of an unstrained indium arsenide (InAs) fin field-effect transistor (finFET) with 20nm fin height (Hfin) [R. Oxland et al, IEEE Electron Device Letters, published online 29 January 2016]. The team also included researchers from University of Glasgow in the UK, Texas State University in the USA, and TSMC in Taiwan.

The gate insulation consisted of 5nm ZrO2 deposited by ALD, yielding an 1.2 nm equivalent oxide thickness (EOT). 

(a) Layer structure used, showing the pseudomorphic InAlAs etch-stop layer and (b) process flow for fabrication of InAs finFETs, starting with first step after wafer growth. (Figure from Semiconductor Today)

Full story here by Mike Cooke in Semiconductor Today and the IEEE Electron Devices abstract below.

InAs FinFETs with Hfin = 20 nm fabricated using a top-down etch process

Oxland, R. Li, X. ; Chang, S. ; Wang, S. ; Vasen, T. ; Ramvall, P. ; Contreras-Guerrero, R. ; Rojas-Ramirez, J. ; Holland, M. ; Doornbos, G. ; Chang, Y. ; Macintyre, D. ; Thoms, S. ; Droopad, R. ; Yeo, Y. ; Diaz, C. ; Thayne, I. ; Passlack, M.

 IEEE Electron Device Letters, published online 29 January 2016

We report the first demonstration of InAs FinFETs with fin width Wfin in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height Hfin = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length Lg = 1 nm, peak transconductance gm,peak = 1430 µS/µm is measured at Vd = 0.5 V demonstrating that electron transport in InAs fins can match planar devices.

Wednesday, January 27, 2016

IBM Research present InGaAs on insulator FinFET process using Plasma Enhanced ALD HKMG

IBM Research GmbH in Switzerland has developed an n-channel indium gallium arsenide (InGaAs) on insulator fin field-effect transistor (FinFET) process and claims the highest on-current to date for CMOS-compatible InGaAs devices integrated on silicon (Si) [Vladimir Djara et al, IEEE Electron Device Letters, published online 1 January 2016].

According to the paper, the devices were fabricated using a replacement metal gate (RMG) flow, including ultra-thin SiN spacers, scaled high-k/metal gate (HKMG), and highly-doped raised source and drain (RSD) modules for improved electrical performance.

ALD Inside:
  • 12-nm-thick SiN spacers were deposited by plasma-enhanced atomic layer deposition (PEALD)
  • After dummy gate removal, a HKMG, featuring a scaled Al2O3/HfO2 dielectric stack with a capacitance equivalent thickness (CET) of ∼1.5 nm, was deposited using a highly conformal and uniform PEALD process. the process has previously been published here.  The tool used is a FlexAL ALD from Oxford Instruments and the PEALD processes are TMA and O2 plasma for Al2O3 and TEMAH and O2 plasma for HfO2.
The FlexAL® systems provide a new range of flexibility and capability in the engineering of nanoscale structures and devices by offering remote plasma atomic layer deposition (ALD) processes and thermal ALD within a single ALD system.

Pretty cool if you ask me to see that PEALD is used for gate dielectric, which is usually not the case on silicon channels where thermal HfCl4/H2O process is dominating and also that TEMAHf can perform this good as a gate dielectric. Please read the full report in Semiconductor Today here.

Monday, August 31, 2015

Japanese researchers provide record low Dit in ALD Al2O3/La2O3/InGaAs gate stacks

InGaAs is one of the most promising III/V semiconductor materials for n-channel MOSFETs because of its extremely high electron mobility of ∼13 800 cm2/V s. However, there  is a major issue with InGaAs not having a high quality native oxide like Silicon resulting in a high interface state density at InGaAs MOS interfaces degrades the MOSFET performance because of Ga dangling bonds and/or As-As dimers created during the oxidation process at InGaAs surfaces. It has been reported that the passivation of trivalent oxides such as Gd2O3 or Al2O3 with InGaAs surfaces can eliminate such dangling bonds and dimers because of the abrupt and chemical-bond-well-arranged interface between the trivalent oxides and InGaAs.

TEM image of Au/AlO (3.5 nm)/LaO (0.4 nm)/InGaAs gate stacks. Citation: J. Appl. Phys. 118, 085309 (2015);

ALD HfO2 has already been introduced at 45 nm CMOS and is still the dominating high-k material in high performance CMOS including recent Si FinFET technologies. Therefore, many have chosen to combine HfO with the AlO/InGaAs structure by continuously ALD has been employed for CET scaling. Thin CET of ∼1.08 nm and low of ∼5 × 1012 cm−2 eV−1 have been realized in the HfO/AlO/InGaAs gate stacks.

Another high-k that has commonly been used and is used e.g. as a dopant in the IBM Alliance 28 nm planar CMOS technology is LaO, which is also trivalent oxide. It has been shown on InGaAs that La2O3 can further improve the MOS interface quality by the formation of Ga-O-La and In-O-La bonds. [ref]

In a very good study presented below by University of Tokyo, JST-CREST and Sumitomo Chemicals a high quality LaO films were deposited on InGaAs by ALD. It was found that the LaO/InGaAs interfaces provide recorded-low of ∼3 × 1011 cm−2 eV−1 as the InGaAs MOS interfaces, which is attributable probably to the intermixing reaction between LaO and InGaAs. It is concluded, as a result, that the AlO/LaO/InGaAs gate stacks can realize lower than in the conventional AlO/InGaAs MOS interfaces with maintaining small hysteresis and low gate leakage by optimizing the thickness of AlO and LaO.

For me now some questions remains - why not combine the best of the best in one stack, i.e., HfO2/La2O3/InGaAs? Perhaps with only a slight touch of blend with Al2O3. Another question that worries me when reading HKMG InGaAs papers is the very low thermal budget that has to be used.  The first high-k layer is deposited at 150 deg. C not destroy the super sensitive InGaAs interface. Most high-k materials needs to be deposited in the ranger 250 to 300 deg.C in order to perform at its best in addition PDAs or PMAs will bring out even more out of the material. Here and in other studies that I have seen a PMA of only 300 deg. C is used. Just imagine bringing this stack on to a silicon based channel material and it will not perform too much better than old poly/SiON with respect to CET / Leakage performance. I guess in the end it is all about the higher mobility given by a III/V channel. It just hurts every time seeing all these smart guys using a relatively low performing high-k.

Please find the OPEN ACCESS publication below!

Impact of La2O3 interfacial layers on InGaAs metal-oxide-semiconductor interface properties in Al2O3/La2O3/InGaAs gate stacks deposited by atomic-layer-deposition [OPEN ACCESS]

C.-Y. Chang, O. Ichikawa, T. Osada, M. Hata, H. Yamada, M. Takenaka and S. Takagi 
J. Appl. Phys. 118, 085309 (2015);

(a) of the AlO (3.5 nm)/LaO/InGaAs gate stacks as a parameter of the LaO ALD cycle numbers, and (b) the LaO ALD cycle number dependence of of AlO (3.5 nm)/LaO/InGaAs at the surface energy of 0.1 eV from midgap ( ). Citation: J. Appl. Phys. 118, 085309 (2015);

We examine the electrical properties of atomic layer deposition (ALD) LaO/InGaAs and AlO/LaO/InGaAs metal-oxide-semiconductor (MOS) capacitors. It is found that the thick ALD LaO/InGaAs interface provides low interface state density ( ) with the minimum value of ∼3 × 1011 cm−2 eV−1, which is attributable to the excellent LaO passivation effect for InGaAs surfaces. It is observed, on the other hand, that there are a large amount of slow traps and border traps in LaO. In order to simultaneously satisfy low and small hysteresis, the effectiveness of AlO/LaO/InGaAs gate stacks with ultrathin LaO interfacial layers is in addition evaluated. The reduction of the LaO thickness to 0.4 nm in AlO/LaO/InGaAs gate stacks leads to the decrease in hysteresis. On the other hand, of the AlO/LaO/InGaAs interfaces becomes higher than that of the LaO/InGaAs ones, attributable to the diffusion of AlO through LaO into InGaAs and resulting modification of the LaO/InGaAs interface structure. As a result of the effective passivation effect of LaO on InGaAs, however, the AlO/10 cycle (0.4 nm) LaO/InGaAs gate stacks can realize still lower with maintaining small hysteresis and low leakage current than the conventional AlO/InGaAs MOS interfaces.

Friday, July 31, 2015

High-pressure anneal for indium gallium arsenide transistors with ALD HKMG

As reported by Semiconductor Today : Researchers in the USA and Korea have developed a hydrogen high pressure annealing (HPA) process for an ALD aluminium oxide/hafnium dioxide (Al2O3/HfO2) gate stacks on indium gallium arsenide (InGaAs) quantum wells [Tae-Woo Kim et al, IEEE Electron Device Letters, vol36, p672, 2015]. The aim of the team, from SEMATECH Inc in the USA, the Korea Advanced Nano Fab Center in South Korea, Poongsan Inc in the USA, and Kyungpook National University in South Korea, was to reduce interface and border traps that adversely affect transistor performance and threshold voltage reliability.

(a) Schematic cross-section for InGaAs MOSCAPs and MOSFETs with HPA, (b) energy-band diagram with interfacial and border traps, and (c) cross-sectional TEM images for ALD Al2O3/HfO2 gate stack before and after HPA.

Full story:

Thursday, June 18, 2015

Imec presents successors to FinFET for 7nm and beyond at VLSI Technology Symposium 2015

Leuven (Belgium)– June 17, 2015 – At this week’s VLSI 2015 Symposium in Kyoto (Japan), imec reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions. 

The Technology roadmap as presented recently by Imec at the EWMOVPE workshop in Lund, Sweden.

As the major portion of the industry adopts FinFETs as the workhorse transistor for 16nm and 14nm, researchers worldwide are looking into the limits of FinFETs and potential device solutions for the 7nm node and beyond. Two approaches, namely Gate-All-Around Nanowire (GAA NW) FETs, which offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels), which achieve high carrier mobility, are promising options. 

For the first time, imec demonstrated the integration of these novel device architectures with state-of-the-art technology modules like Replacement-Metal-Gate High-k (RMG-HK) and Self (Spacer)-Aligned Double-Patterned (SADP) dense fin structures. By building upon today’s advanced FinFET technologies, the work shows how post-FinFET devices can emerge, highlighting both new opportunities as well as complexities to overcome. 

Imec and its technology research partners demonstrated SiGe-channel devices with RMG-HK integration. Besides SiGe FinFET, a unique GAA SiGe nanowire channel formation during the gate replacement process has been demonstrated. The novel CMOS-compatible process converts fin channels to nanowires by sacrificial Si removal during the transistor gate formation. The process may even enable future heterogeneous co-integration of fins and nanowires, as well as Si and SiGe channels. The work also demonstrates that such devices and their unique processing can lead to a drastic 2x or more improvement in reliability (NBTI) with respect to Si FinFETs. 

Moreover, imec demonstrated Si GAA-NW FETs based on SOI with RMG-HK. The work compares junction-based and junction-less approaches and the role of gate work function for multi-Vt implementations. New insights into the improved reliability (PBTI) with junction-less nanowire devices have been gained.

Extending the heterogeneous channel integration beyond Si and SiGe, imec demonstrated for the first time strained Ge QW FinFETs by a novel Si-fin replacement fin technique integrated with SADP process. Our results show that combining a disruptive approach like fin replacement with advanced modules like SADF-fin, RMG-HK, direct-contacts can enable superior QW FinFETs. The devices set the record for published strained Ge pMOS devices, outperforming by at least 40% in drive current at matched off-currents.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, SK hynix, Sony and TSMC.

Monday, June 8, 2015

IBM Zurich present III-V on silicon wafers breakthrough technology using ALD

IBM has done it - a method of depositing ultra-fast III-V nanowires suitable for transistor channels and other structures on silicon-on-insulator (SOI) substrates -  and for sure ALD was involved in one of the early crucial processing steps to create the template for TASE - Template Assisted Selective Epitaxy. 

"A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) " 

Check out the details below and in the Open Access paper!

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si (Open Access)

H. Schmid, M. Borg, K. Moselund, L. Gignac, C. M. Breslin, J. Bruley, D. Cutaia and H. Riel
Appl. Phys. Lett. 106, 233101 (2015); 

Schematic (a) and SEM images (b)–(d) illustrating stacking of Si and III-V NWs. (b) SEM image shows a tilted view of three stacked template structures. (c) SEM cross-section image of the Si NW stack and (d), TEM image of the GaAs NW stack (Appl. Phys. Lett. 106, 233101 (2015);

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.

SEM images illustrating epitaxial filling of complex nano structures. (a) Evolution of the growth during filling of three templates, each having a lithographically pre-defined constriction. (b) Formation of an InAs cross-junction for the later fabrication of a Hall structure. The InAs film thickness is 23 nm (Appl. Phys. Lett. 106, 233101 (2015);

The fabrication steps of TASE : a (100)-oriented SOI substrates (Soitec) with a device layer thickness of 25–50 nm were patterned using e-beam lithography and reactive ion etching. A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) and annealed at 850 °C in Ar/H2. The SiO2 cap on one end of the Si structure was opened by patterning polymethylmethacrylate (PMMA) by e-beam lithography and buffered hydrofluoric acid (BHF) etching to expose the Si device layer. Next the Si was back-etched to the desired length using either XeF2 dry etching followed by tetramethylammoniumhydroxide (TMAH) wet etching or TMAH etching only, to result in well-defined {111} planes. The orientation of the {111} planes with respect to the channel direction was controlled by the alignment of the channel patterns. All structures reported here were patterned along the 〈110〉 direction. The as-prepared substrate was dipped in diluted (2.5%) HF to remove the native oxide on the exposed Si surfaces within the channels and was immediately loaded into the MOCVD reactor. Selective epitaxy of InGaAs was carried out using trimethylindium (TMIn), tertiarybutylarsine (TBAs), and trimethygallium (TMGa) at V/III ratio = 40 with TMIn/(TMIn+TMGa) = 0.5 at 580 °C. Chemical analysis was obtained from electron energy loss spectroscopy (EELS) analysis and indicated an In0.50Ga0.50As composition. InAs epitaxy was carried out at 520 °C using TMIn and TBAs with a V/III ratio = 80 and V/III ratio = 40 for the MuGFETs, respectively. Optionally, the dielectric template was removed after growth by wet etching in diluted HF, to expose the Si–III-V nano-structure on the SiO2 layer (BOX). 

Sunday, May 31, 2015

Epitaxial growth of GaN nanowires on metallic TiN by Paul-Drude-Institut, Berlin

Paul-Drude-Institut für Festkörperelektronik in Berlin has recently published a paper (below) on how to grow GaN Nanowires on TiN. From a silicon based semiconductor device perspective this is very interesting results since TiN can be used to make ohmic contact to silicon. For instance the is used in most DRAM Capacitor cells today where the word line is connected by a TiN/Ti/TiSi/Si ohmic contact. This technology was invented by Qimonda - The buried Word Line technology that was introduced at 65 nm and has been transferred to many other companies since then (Winbond, Micron, Elpida, ...). Or as the researchers at the Paul-Drude-Institut states:  

"The freedom to employ metallic substrates for the epitaxial growth of semiconductor nanowires in high structural quality may enable novel applications that benefit from the associated high thermal and electrical conductivity as well as optical reflectivity."

Epitaxial Growth of GaN Nanowires with High Structural Perfection on a Metallic TiN Film 

M. Wölz , C. Hauswald , T. Flissikowski , T. Gotschke , S. Fernández-Garrido , O. Brandt , H. T. Grahn , L. Geelhaar *, and H. Riechert 
Nano Lett., Article ASAP DOI: 10.1021/acs.nanolett.5b00251 
Publication Date (Web): May 22, 2015

Vertical GaN nanowires are grown in a self-induced way on a sputtered Ti film by plasma-assisted molecular beam epitaxy. Both in situ electron diffraction and ex situ ellipsometry show that Ti is converted to TiN upon exposure of the surface to the N plasma. In addition, the ellipsometric data demonstrate this TiN film to be metallic. The diffraction data evidence that the GaN nanowires have a strict epitaxial relationship to this film. Photoluminescence spectroscopy of the GaN nanowires shows excitonic transitions virtually identical in spectral position, line width, and decay time to those of state-of-the-art GaN nanowires grown on Si. Therefore, the crystalline quality of the GaN nanowires grown on metallic TiN and on Si is equivalent. The freedom to employ metallic substrates for the epitaxial growth of semiconductor nanowires in high structural quality may enable novel applications that benefit from the associated high thermal and electrical conductivity as well as optical reflectivity.

Wednesday, May 6, 2015

ALD oxides used in vertical gallium nitride MOSFETs with reduce on-resistance

As reported by Semiconductor Today: Toyoda Gosei Co Ltd in Japan has developed a vertical trench metal-oxide-semiconductor field-effect transistor (MOSFET) on free-standing gallium nitride (GaN) combining 1.2kV blocking voltage with low specific on-resistance [Tohru Oka et al, Appl. Phys. Express, vol8, p054101, 2015]. The researchers comment: "To the best of our knowledge, this is the first report on vertical GaN-based MOSFETs with a specific on-resistance of less than 2mΩ-cm2." 

Interestingly the integration employs a 80 nm ALD SiO2gate dielectric and a100 nm ALD Al2O3 800 nm PECVD SiO2 combo interdielectric. This basically shows two things:

1) Oxides by ALD is not all about high-k
2) ALD is also used for relatively thick layers and not only 10 to 100 Å in microelectronics

Figure 1

Transistor fabrication (Figure 1) involved inductively couple plasma (ICP) etching for mesa isolation, p-body contact recessing, and gate trenching. The gate dielectric was 80nm silicon dioxide, grown using atomic layer deposition (ALD). Interlayer dielectrics of 100nm aluminium oxide and 800nm silicon dioxide were produced by atomic layer deposition and plasma-enhanced chemical vapor deposition (PECVD)(Picture from Semiconductor Today).

Friday, May 1, 2015

InAs Nanowire Transistors with Multiple Independent Wrap-Gate Segments

The Nanometer Structure Consortium (nmC) at, Lund University Sweden and School of Physics, University of New South Wales, Australia demonstrate a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments
A. M. Burke, D. J. Carrad, J. G. Gluschke, K. Storm, S. Fahlvik Svensson, H. Linke, L. Samuelson, and A. P. Micolich
Nano Lett., Article ASAP, DOI: 10.1021/nl5043243

Abstract Image

AN InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments (Graphical Abstracts Nano Lett., Article ASAP, DOI: 10.1021/nl5043243)

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

Friday, March 27, 2015

Stanford GaAs process could yield better solar cells, faster chips

New Stanford manufacturing process could yield better solar cells, faster chips
Silicon isn't the only chip-making material under the sun, just the cheapest. But a new process could make the alternative material, gallium arsenide, more cost effective.

Silicon is typically used in solar cells and computer chips. Gallium arsenide is an alternative material with many advantages. But it costs too much. A new process would reduce manufacturing costs.

"Solar cells that use gallium arsenide hold the record when it comes to the efficiency at which they convert sunlight into electricity," said Bruce Clemens, the professor of materials science and engineering who led this work.

"Once it becomes possible to make gallium arsenide more cost-effectively, other people will jump in to improve other parts of the process,'' Clemens said. "And with each advance, more uses will open up, especially in solar energy generation where gallium arsenide has clear efficiency advantages."

Friday, March 20, 2015

Sol Voltaics makes record-breaking III-V nanowire solar cell

As reported in Compund Semiconductor: Sol Voltaics, based in Lund, Sweden, has announced that it has doubled the previously reported world-record for photovoltaic (PV) conversion efficiency using a GaAs nanowire array (NWA).

As independently verified by Fraunhofer-ISE, Sol Voltaics has demonstrated a 1-sun conversion efficiency of 15.3 percent in a GaAs NWA solar cell, representing a significant milestone towards providing the solar industry with an efficiency boosting tandem film.

This is the highest efficiency reported to date in a III-V NWA solar cell, and twice the prior record for GaAs NWA technology. Control of the high density of surface states of native GaAs is essential for PV applications, and these results, says Sol Voltaics, prove that it has has resolved this challenge in the growth of solar cell nanowires.

"The efficiency of our GaAs nanowires is a critical component of our low cost film. The use of III-V materials in the PV industry has always been a goal but the costs have been prohibitive. Using Sol Voltaic's Aerotaxy nanowire production methodology allows our III-V film to be produced at competitive cost at efficiencies that are industry changing," said Erik Smith, CEO of Sol Voltaics. "We look forward to working with industrial partners on the integration of our technology on to silicon cells so they may make the leap to 27 percent efficiency and beyond."

GaAs has been used in performance-category solar modules for years because of its high conversion efficiencies. The challenge has always been its high cost relative to other solar materials.

The low cost Aerotaxy process invented by Sol Voltaics' founder and Lund University professor Lars Samuelson, reduces the amount of GaAs and other expensive materials required to generate electricity. Nanowires are created by suspending active materials in gases intermingled in precisely controlled environment. The suspended materials bond to form larger, uniform structures: nanowires are literally grown in space.

Aerotaxy generates nanowires within milliseconds, according to the company, and can produce them on a continuous basis at comparatively low temperatures.

The finished nanowire film can be integrated into solar panels or stored indefinitely. A 2012 paper published in Nature details how Samuelson and his team manufactured GaAs nanowires with Aerotaxy.

Magnus Heurlin, Martin H. Magnusson, David Lindgren, Martin Ek, L. Reine Wallenberg, Knut Deppert & Lars Samuelson

Nature 492, 90–94

Semiconductor nanowires are key building blocks for the next generation of light-emitting diodes1, solar cells2 and batteries3. To fabricate functional nanowire-based devices on an industrial scale requires an efficient methodology that enables the mass production of nanowires with perfect crystallinity, reproducible and controlled dimensions and material composition, and low cost. So far there have been no reports of reliable methods that can satisfy all of these requirements. Here we show how aerotaxy, an aerosol-based growth method4, can be used to grow nanowires continuously with controlled nanoscale dimensions, a high degree of crystallinity and at a remarkable growth rate. In our aerotaxy approach, catalytic size-selected Au aerosol particles induce nucleation and growth of GaAs nanowires with a growth rate of about 1micrometre per second, which is 20 to 1,000 times higher than previously reported for traditional, substrate-based growth of nanowires made of group III–V materials5, 6, 7. We demonstrate that the method allows sensitive and reproducible control of the nanowire dimensions and shape—and, thus, controlled optical and electronic properties—through the variation of growth temperature, time and Au particle size. Photoluminescence measurements reveal that even as-grown nanowires have good optical properties and excellent spectral uniformity. Detailed transmission electron microscopy investigations show that our aerotaxy-grown nanowires form along one of the four equivalent left fence111right fenceB crystallographic directions in the zincblende unit cell, which is also the preferred growth direction for III–V nanowires seeded by Au particles on a single-crystal substrate. The reported continuous and potentially high-throughput method can be expected substantially to reduce the cost of producing high-quality nanowires and may enable the low-cost fabrication of nanowire-based devices on an industrial scale.

Wednesday, March 18, 2015

European Researchers grow InGaN layers directly on Silicon by PA-MBE

Researchers from Spain, Germany and Italy grows InGaN layers grown directly on Silicon by PA-MBE.

Pavel Aseev, Paul E. D. Soto Rodriguez, Víctor J. Gómez, Naveed ul Hassan Alvi1, José M. Mánuel, Francisco M. Morales, Juan J. Jiménez, Rafael García, Alexander Senichev, Christoph Lienau, Enrique Calleja and Richard Nötzel
Appl. Phys. Lett. 106, 072102 (2015);

The authors report compact and chemically homogeneous In-rich InGaN layers directly grown on Si (111) by plasma-assisted molecular beam epitaxy. High structural and optical quality is evidenced by transmission electron microscopy, near-field scanning optical microscopy, and X-ray diffraction. Photoluminescence emission in the near-infrared is observed up to room temperature covering the important 1.3 and 1.55 μm telecom wavelength bands. The n-InGaN/p-Si interface is ohmic due to the absence of any insulating buffer layers. This qualitatively extends the application fields of III-nitrides and allows their integration with established Si technology.

(a) HRTEM image of the In0.73Ga0.27N/SiNx/Si interface and (b) HAADF image of the InGaN layer, both taken along the [11–20] III-N zone axis. (c) Corresponding SEM image.

Wednesday, March 11, 2015

Chalmers and Thales reduce low-frequency noise in AlInN/GaN HEMTs by ALD/PEALD passivation

As reported by Semiconductor Today, researchers based in Sweden* and France** have been exploring various passivations for reducing low-frequency noise (LFN) in gallium nitride (GaN) high-electron-mobility transistors (HEMTs) with aluminium indium nitride (AlInN) barriers [Thanh NgocThi Do etal, IEEE Electron Device Letters, published online 6 February 2015]. The researchers claim that one of their passivation processes produced the best reported LFN for AlInN/GaNHEMTs.
Effects of surface passivation and deposition methods on the 1/f noise performance of AlInN/AlN/GaN HEMTs

Do, T., Malmros, A. ; Horberg, M. ; Rorsman, N. ; Kuylenstierna, D. ; Gamarra, P. ; Lacam, C. ; Poisson, M. ; Tordjman, M. ; Aubry, R.

Electron Device Letters, IEEE  (Volume:PP ,  Issue: 99 )

This paper reports on effects of Si3N4 and Al2O3 surface passivation as well as different deposition methods on the Low Frequency Noise (LFN) characteristics for AlInN/AlN/GaN High Electron Mobility Transistors (HEMTs). Two samples are passivated with Al2O3, deposited by two different methods: thermal Atomic Layer Deposition (ALD) and plasma-assisted ALD. The third sample is passivated with Si3N4 using Plasma-Enhanced Chemical Vapor Deposition (PECVD). The LFN of the three samples is measured under a bias condition relevant for amplifier and oscillator applications. It is found that the surface passivation has a major impact on the noise level. The best surface passivation, with respect to LFN, is the thermal ALD Al2O3 for which the noise current spectral density measured at 10kHz is 1×10-14 Hz-1 for a bias of Vdd/Idd = 10V/80mA. To the authors’ best knowledge this result sets a standard as the best reported LFN of AlInN/GaN HEMTs. It is also in the same order as good commercial AlGaN/GaN HEMTs reported in literature and thus demonstrates that AlInN/GaN HEMTs, passivated with thermal ALD Al2O3, is a good candidate for millimetre-wave power generation. 
Figure 1: Drain noise current spectra of the three AlInN/AlN/GaN HEMTs versus frequency at 10V, 17mA operating point.

Drain noise current spectra of the three AlInN/AlN/GaN HEMTs versus frequency at 10V, 17mA operating point. (Semiconductor Today, Electron Device Letters, IEEE  (Volume:PP ,  Issue: 99 ) )
* Microwave Electronics Laboratory, Department of Microtechnology and Nanoscience (MC2), Chalmers University of Technology, , Sweden
** The Wide Band Gap Materials Laboratory and the GaN process Laboratory of 3-5 Lab/Thales Research & Technology, Marcoussi, France

Monday, February 16, 2015

US and South Korean researchers claim record performing tri-gate InGaAs MOSFET

According to a report in Semiconductor Today, researchers based in USA and South Korea claim a record combination of subthreshold swing (82mV/decade, 0.5V drain bias), transconductance (1800μS/μm) and on-current (0.41mA/μm) for any tri-gate quantum well indium gallium arsenide (InGaAs) metal-oxide-semiconductor field-effect-transistor (MOSFET) [Tae-Woo Kim et al, IEEE Electron Device Letters, published online 20 January 2015]. 
The gate insulation consisted of 0.7nm of aluminium oxide (Al2O3) and 2nm of hafnium dioxide (HfO2) deposited by atomic layer deposition (ALD).
Process flow, cross-sectional schematic and TEM image of a tri-gate InGaAs MOSFET, from longitudinal and horizontal direction.

Process flow, cross-sectional schematic and TEM image of a tri-gate InGaAs MOSFET, from longitudinal and horizontal direction.
The team was based at SEMATECH Inc in the USA, KANC in South Korea, and GLOBALFOUNDRIES in the USA.

Friday, February 21, 2014

HfO2 still going strong for Post-Silicon Channel Materials

According to a recent article HfO2 still going strong for Post-Silicon Channel Materials!
"Once device-grade channel materials are achieved, formation of a high quality gate dielectric is the next step. Here, recent results offer reason for optimism. As previously discussed, an initial Al2O3 deposition does not appear to be needed to passivate the InGaAs interface. While a clean surface is essential for successful gate oxide deposition, and atomic layer deposition appears to be an enabling technology for surface preparation, D. Hassan Zadeh and coworkers also obtained good results with La2O3 dielectrics. This material, along with HfO2, offers much a higher dielectric constant than Al2O3, improving ultimate scalability of alternative channel devices."
Read all about it on "New Challenges For Post-Silicon Channel Materials", by Katherine Derbyshire, Semiconductor Engineering:

As reported by CompoundSemiconductor, Engineers from MIT are claiming to have fabricated the first tunnel FET with a double quantum well InGaAs/GaAsSb structure. This work has been published in: IEEE Electron Dev. Lett. 34 1503 (2013). MIT demonstrate employing HfO2 high-k on an InGaAs channel.

Engineers from MIT have fabricated a double quantum well FET (a). Cross-sectional tunnelling electron microscopy provides images of the tunnelling junction and gate stack in the gated region (b), and the edge of the InGaAs air bridge (c). A top view of the air-bridge, after suspension, is provided by a scanning tunnelling microscope (d) [as reported by].