Monday, June 8, 2015

IBM Zurich present III-V on silicon wafers breakthrough technology using ALD

IBM has done it - a method of depositing ultra-fast III-V nanowires suitable for transistor channels and other structures on silicon-on-insulator (SOI) substrates -  and for sure ALD was involved in one of the early crucial processing steps to create the template for TASE - Template Assisted Selective Epitaxy. 

"A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) " 

Check out the details below and in the Open Access paper!

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si (Open Access)

H. Schmid, M. Borg, K. Moselund, L. Gignac, C. M. Breslin, J. Bruley, D. Cutaia and H. Riel
Appl. Phys. Lett. 106, 233101 (2015); 

Schematic (a) and SEM images (b)–(d) illustrating stacking of Si and III-V NWs. (b) SEM image shows a tilted view of three stacked template structures. (c) SEM cross-section image of the Si NW stack and (d), TEM image of the GaAs NW stack (Appl. Phys. Lett. 106, 233101 (2015);

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.

SEM images illustrating epitaxial filling of complex nano structures. (a) Evolution of the growth during filling of three templates, each having a lithographically pre-defined constriction. (b) Formation of an InAs cross-junction for the later fabrication of a Hall structure. The InAs film thickness is 23 nm (Appl. Phys. Lett. 106, 233101 (2015);

The fabrication steps of TASE : a (100)-oriented SOI substrates (Soitec) with a device layer thickness of 25–50 nm were patterned using e-beam lithography and reactive ion etching. A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) and annealed at 850 °C in Ar/H2. The SiO2 cap on one end of the Si structure was opened by patterning polymethylmethacrylate (PMMA) by e-beam lithography and buffered hydrofluoric acid (BHF) etching to expose the Si device layer. Next the Si was back-etched to the desired length using either XeF2 dry etching followed by tetramethylammoniumhydroxide (TMAH) wet etching or TMAH etching only, to result in well-defined {111} planes. The orientation of the {111} planes with respect to the channel direction was controlled by the alignment of the channel patterns. All structures reported here were patterned along the 〈110〉 direction. The as-prepared substrate was dipped in diluted (2.5%) HF to remove the native oxide on the exposed Si surfaces within the channels and was immediately loaded into the MOCVD reactor. Selective epitaxy of InGaAs was carried out using trimethylindium (TMIn), tertiarybutylarsine (TBAs), and trimethygallium (TMGa) at V/III ratio = 40 with TMIn/(TMIn+TMGa) = 0.5 at 580 °C. Chemical analysis was obtained from electron energy loss spectroscopy (EELS) analysis and indicated an In0.50Ga0.50As composition. InAs epitaxy was carried out at 520 °C using TMIn and TBAs with a V/III ratio = 80 and V/III ratio = 40 for the MuGFETs, respectively. Optionally, the dielectric template was removed after growth by wet etching in diluted HF, to expose the Si–III-V nano-structure on the SiO2 layer (BOX). 

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