Showing posts with label nanowires. Show all posts
Showing posts with label nanowires. Show all posts

Thursday, October 15, 2020

Swedish NordAmps has developed InGaAs nanowire transistors with GAA high-k/metal gate

NordAmps in Lund, Sweden, has developed InGaAs nanowire transistors with GAA high-k /metal gate (HKMG) capable of the high frequencies required for 5G and 6G data transfer and logic data processing, with significantly lower energy consumption.

The structures are fully compatible with a standard 300 mm standard Si CMOS flow and require less mask steps compared with conventional technology.

NordAmps represents the convergence of research by global leaders in nanotechnology with leading edge application needs. 

Source: NordAmps LINK




Monday, November 19, 2018

Isotropic Atomic Layer Etching of ZnO Using Acetylacetone and O2 Plasma

Plasma atomic layer etching (ALE) is typically know as an anisotropic etch method (directional), which is very useful property in many cases but sometimes not good at all, e.g, when you want to conformally (sorry for the reverse ALD expression) etch an high aspect ratio feature like a deep hole or a pillar.

Here is a fresh publication from TU Eindhoven and TNO/Holst Center in the Netherlands on their recent development of a Plasma ALE process capable of isotropical etch, i.e, conformal etching, of very high aspect ratio ZnO nanowires. Its is Open Access so go ahead and download it for free.

Fred, heel erg bedankt voor het delen van deze!

Isotropic Atomic Layer Etching of ZnO Using Acetylacetone and O2 Plasma

A. Mameli, M. A. Verheijen, A. J. M. Mackus, W. M. M. Kessels, and F. Roozeboom
ACS Appl. Mater. Interfaces, 2018, 10 (44), pp 38588–38595
DOI: 10.1021/acsami.8b12767
Atomic layer etching (ALE) provides Ångström-level control over material removal and holds potential for addressing the challenges in nanomanufacturing faced by conventional etching techniques. Recent research has led to the development of two main classes of ALE: ion-driven plasma processes yielding anisotropic (or directional) etch profiles and thermally driven processes for isotropic material removal. In this work, we extend the possibilities to obtain isotropic etching by introducing a plasma-based ALE process for ZnO which is radical-driven and utilizes acetylacetone (Hacac) and O2 plasma as reactants. In situ spectroscopic ellipsometry measurements indicate self-limiting half-reactions with etch rates ranging from 0.5 to 1.3 Å/cycle at temperatures between 100 and 250 °C. The ALE process was demonstrated on planar and three-dimensional substrates consisting of a regular array of semiconductor nanowires (NWs) conformally covered using atomic layer deposition of ZnO. Transmission electron microscopy studies conducted on the ZnO-covered NWs before and after ALE proved the isotropic nature and the damage-free characteristics of the process. In situ infrared spectroscopy measurements were used to elucidate the self-limiting nature of the ALE half-reactions and the reaction mechanism. During the Hacac etching reaction that is assumed to produce Zn(acac)2, carbonaceous species adsorbed on the ZnO surface are suggested as the cause of the self-limiting behavior. The subsequent O2 plasma step resets the surface for the next ALE cycle. High etch selectivities (∼80:1) over SiO2 and HfO2 were demonstrated. Preliminary results indicate that the etching process can be extended to other oxides such as Al2O3.

Thursday, August 30, 2018

How to split nanowires by Atomic Layer Etching

The master thesis by Sabbir A. Khan based on work completed at Lund Nano Lab, Lund University Sweden, has finally been released from secrecy [Patent application WO2017157902A1]. Please find below the abstract and link to the full version. Sabbir is now a Ph.D. candidate in Quantum Materials at Microsoft Quantum Materials Lab (MQML) and Center for Quantum Devices, Niels Bohr Institute, University of Copenhagen, Denmark. There his research focuses on as-grown epitaxial nanowire based networks for scalable quantum computation. The main goal is to develop innovative fabrication techniques that can realize new device concepts based on as-grown nanowire networks.

Evaluation of Atomic Layer Etching Possibility at Lund Nano Lab [LINK PDF]
Next you will have a chance to meet Sabbir at the PSE 2018 Tutorial, Plasma assisted atomic level processing – PEALD & ALE Sunday, September 16, 2018 in Garmisch-Partenkirchen, Germany.
In modern electronics, device downscaling demands atomic precision control and Atomic Layer Etching (ALE) can provide this prime capability with minute device damage. ALE, also known as layer-by-layer etching, is a technique of removing atomically thin layers from the surface of materials in a controlled way. This technique is now very crucial for nanofabrication and semiconductor industry in order to achieve atomic scale resolution. This is why the overall goal of this diploma project was to investigate the possibility for ALE at Lund Nano Lab and to reveal different limitations with our current equipment. In order to achieve this goal we have done experiments with conventional system used for reactive ion etching. In addition, the ALE has been done on GaP nanowires and on Si surface patterned with high-resolution Electron Beam Lithography (EBL). The results of these experiments indicate that the process can be used to make stamps for nanoimprint lithography in a highly controlled way and that the low ion energy etching process can be used for direct nanowire splitting. We show different limitations for ALE with our current equipment and provide recommendations for new equipment dedicated for this process. In this way, the work presented here opens up the possibility for further studies of ALE with conventional equipment, shows some aspects of it’s importance for nanofabrication and suggests new applications for the ALE processes.
Popular Abstract
Nowadays electronic devices are getting smaller and much more efficient. However, it’s getting much harder to fabricate such small devices. Specifically, device fabrication with feature sizes below 10 nm (a human hair is 100,00 nm wide) is a big challenge. For this, atomic level control is needed. Atomic layer etching (ALE) is one of the key technologies that can provide atomic controlled etching of different materials by a cyclic etching, where an (sub) atomically thick layer is etched in every cycle. There are also other technologies, which have a potential for the sub 10 nm fabrication. For instance nanoimprint lithography, which is alike book printing but for extremely small features in nanometer range, and epitaxial semiconductor nanowires grown from seed catalytic particles by different epitaxial techniques have a very big potential for extremely fine fabrication of nanostructures. These techniques are also very active research areas in Lund and have already enabled many important applications. This is why the combination of ALE with these techniques may open up many new interesting opportunities. For example, the nanoimprint lithography can be only as good as the stamps, which are used for the nanoimprint, and ALE may provide a very good mean of the stamp fabrication with subatomic precision.

Sabbir A. Khan splitting Nanowires at Lund Nanolab using the Oford Instruments Plasmalab 100 System.

Different III-V semiconductor nanowires are very important for their electrical and optical properties. Diameter of the usual nanowires lies in the 40-100 nm range and with ALE it might be potentially possible to shrink the nanowire diameter to the sub 10 nm range. In this research work we used a system for reactive ion etching, similar to the systems, which are widely used in semiconductor industry for semiconductor device fabrication, for testing ALE possibility in Lund Nano Lab. We demonstrated that with this equipment it is possible to perform ALE and used this process for etching semiconductor horizontal nanowires and to make stamps for nanoimprint lithography. Surprisingly, we found that, due to some specific properties of the ALE process and a hexagonal cross section of nanowires, which we used in our experiments, after ALE each nanowire is split in to two very thin nanowires. We believe that here the inclined nanowire surfaces act as a mask for the etch process and that potentially this technique can enable fabrication of ever smaller semiconductor devices in a controllable and industrially relevant way. For instance, a core part of every transistor is a transistor channel and we can foresee that this technique may enable splitting of the transistor channel into two channels without additional expensive and challenging lithographic steps. In this way we may enable further downscaling of transistors in a very economical and practical way by this helping further downscaling of electronic devices

Friday, February 3, 2017

Germanium outperforms silicon in energy efficient gate all around NW transistors

A team of scientists from the Nanoelectronic Materials Laboratory (NaMLab gGmbH) and the Cluster of Excellence Center for Advancing Electronics Dresden (cfaed) at the Dresden University of Technology have demonstrated the world-wide first transistor based on germanium that can be programmed between electron- (n) and hole- (p) conduction.

Full story: LINK

The publication can be found online under:

Tuesday, January 10, 2017

Nanowire week in Lund, Sweden 29th May - 2nd June, 2017

10th Nanowire Growth Workshop + 9th NANOWIRES = Nanowire Week

5 days of lively discussion on all areas of nanowire research, from growth to applications

The Nanowire Week will take place in Lund, Sweden from May 29 – June 2, 2017. Nanowire Week is the merger of two well-established and highly successful annual workshops: NANOWIRES and the Nanowire Growth Workshop. Nanowire Week will cover all topics of nanowire-related research, from fabrication and fundamental properties to applications.