Showing posts with label nanowires. Show all posts
Showing posts with label nanowires. Show all posts

Friday, July 22, 2016

Lund Nano Lab to present new maskless technology for nano device patterning at ALE 2016 Ireland

Semiconductor device scaling requires atomic level precision processing and Atomic Layer Etching (ALE) has a great potential for this. ALE is a cyclic etching process in which a well-defined atomically thin layer is etched in each cycle. [HERALD White Paper on Atomic Level Processing]

Lund Nano Lab at NanoLund, Lund University to present new maskless technology for nano device patterning at ALE 2016 Ireland. Here you can have a preview and we welcome all of you to enjoy the opening pleanary talk by Prof. Lars Samuelson and later the contributed talk by Dr. Dmitry Suyatin in the ALE Workshop. Later you may also want to come and stop by and visit us in the Exhibition at the joint stand NanoLund and ALD Lab Saxony - table 45 right next to the coffee.

Nanowire-based Technologies for Electronics, LEDs and Solar-cells
Lars Samuelson
Lund University, Sweden

Dr. Dmitry Suyatin from Lund university presenting initial groundbreaking work on splitting Nanowires by ALE at the Novel High-k Workshop in Dresden 2016. At ALE 2016 more details will be revealed.

Longitudinal nanowire splitting by atomic layer etching
Lund University, Sweden


We provide an ALE-based maskless method of manufacturing nanostructures with characteristic size below 20 nm


  • IP & licencing 
  • ALE Process development 
  • Device fabrication 
  • Process transfer

Friday, March 25, 2016

Lund Univeristy in Sweden moves ahead with Phase 1 for the Nano Pilot Production facility - ProNano

Lund University, Sweden, is the largest university in the Nordic Countries situated across the bridge from Copenhagen. ProNano is a pilot study of the market potential for a pilot production facility for nanotechnology and nano materials in Lund. The facility is aimed at researchers and companies wants to develop pilot production and products with industry standard, without having to invest in expensive equipment by themselves.

The project was initiated by NanoLund at Lund University, Sweden and is conducted in collaboration with Lund University, Region Skåne, RISE and Medicon Village with representation from industry, academia and authorities and Yvonne Mårtensson, former CEO Cellavision AB is the project manager of ProNano. This week the next steps have been announced by a press release from Lund University.
Science Village Scandinavia will consist of buildings aimed at research facilities, research institutes, research institutes for Lund University and other universities, companies related to innovation and research, a Science Centre and Business Centre, premises for laboratories, administration, service and accommodation (
Prof. Lars Samuelson, founder of NanoLund and the nanowire growth research and also founder of a number of spin-off companies and the driver of commercialization of nano materials at Lund University stated: "An effort for the industrialization of nano materials in Lund is a natural result of the world leading materials research with the establishment of a number of companies where the research is channeled all the way to the market". As a note for the readers here, Prof. Samuelson is the Keynote Speaker of ALD 2016 in Dublin, Ireland 24-27th of July.

Prof. Lars Samuelson (left) and Prof. Heiner Linke (right), the founder resp. the Director of NanoLund.
Prof. Heiner Linke, Director of NanoLund added "The goal with ProNano is to create a vertical integrated system around Swedish nanotechnology that stretches from education through basic and applied research all the way to production. The vision is to realize the foundation for a Swedish industry based on advanced nano materials"

The regional authorities of Skåne (Region Skåne, Southern part of Sweden part of greater Copenhagen) has now decided to fund the project ProNano Phase 1 with additional funds of 4 million SEK for 2016 and 2017.

Pontus Linberg (regional conservative politician) put it in a context by saying: "The world class infrastructure of ESS and MAX IV currently being constructed in Lund has to be followed up by additional support for the foundation for business development and commercialization. ProNano will be the first bid establishment of infrastructure placed between MaxIV and ESS. ProNano will be targeting developing existing and new companies and is a natural and highly important part of the push for smart materials."

The Region of Skåne will except for financially supporting ProNano facilitate the process and connect the player on the nano materials and nano technology arena.

The recently published white paper can be downloaded here (in Swedish)

Tuesday, February 16, 2016

A nanolaser for fast and efficient data processing with light from TU München

As reported by TU Munich in EurekAlert!: Physicists at the Technical University of Munich (TUM) have developed a nanolaser, a thousand times thinner than a human hair. Thanks to an ingenious process, the nanowire lasers grow right on a silicon chip, making it possible to produce high-performance photonic components cost-effectively. This will pave the way for fast and efficient data processing with light in the future.

"Today already, transistors are merely a few nanometers in size. Further reductions are horrendously expensive," says Professor Jonathan Finley, Director of the Walter Schottky Institute at TUM. "Improving performance is achievable only by replacing electrons with photons, i.e. particles of light."

This news release is available in German.


Monolithically Integrated High-beta Nanowire Lasers on Silicon
B. Mayer, L. Janker, B. Loitsch, J. Treu, T. Kostenbader, S. Lichtmannecker, T. Reichert, S. Morkötter, M. Kaniber, G. Abstreiter, C. Gies, G. Koblmüller, and J. J. Finley;
Nano Letters, 2016, 16 (1), pp 152-156 - DOI: 10.1021/acs.nanolett.5b03404

Coaxial GaAs-AlGaAs core-multishell nanowire lasers with epitaxial Gain control
T. Stettner, P. Zimmermann, B. Loitsch, M. Döblinger, A. Regler, B. Mayer, J. Winnerl, S. Matich, H. Riedl, M. Kaniber, G. Abstreiter, G. Koblmüller, and J. J. Finley;
Applied Physics Letters, 108, 011108 (2016) - DOI: 10.1063/1.4939549

Continuous wave lasing from individual GaAs-AlGaAs core-shell nanowires
B. Mayer, L. Janker, D. Rudolph, B. Loitsch, T. Kostenbader, Abstreiter, G. Koblmüller, and J. J. Finley; Applied Physics Letters 108, Vol. 8, to appear on Feb. 22nd (2016)


Saturday, January 23, 2016

Gartner says that 7nm will be delayed and 5nm will be pushed out ot 2023

10 nm FinFET may start to ship as early as end of 2016. However, according to a recent article by Mark Lapedus (at Semiconductor Engineering) Bob Johnson, an analyst at Gartner, projects that 7nm could get pushed out to 2020. "This, in turn, could impact the potential timing of 5nm, if the industry decides to move forward with the technology. “I assume 5nm will happen, but not by 2020,” Johnson said, adding that a viable 5nm process may not appear until the next decade, possibly 2023."

The slow down in scaling is not something new and has been seen for some time now. Above is a forecast presented at 2014 Semicon West with conclusions of the SEMI’s World Fab Forecast - Technology Node Transitions Slowing Below 32 nm. Her you can clearly see that the node transitions has paced slower since 28/32 nm.  The question now is then if the pace will come to a halt.

The current 3 main options for 5nm logic FETs are :
  • Gate-All-Around FETs based on III/V Nanowires
  • To extend FinFET
  • Monolithic 3D and other 2.5D/3D IC technologies

Wednesday, January 13, 2016

Double-Layered Nanowire to Develop High-Speed Transistor Channel by NIMS and Georgia Institute of Technology

The future of highly scaled semiconductor devices is reaching oout in the third dimension like form DRAM, 3DNAND, 3D Stacking of chips. Recently also Logic made the move by the introduction of FinFETs at 22 nm. It wil be realy interesting to follow this progressing and there are just less limitations than for planar devices. Here is a recent report by AZO Nano on a novel dual layer nanowire transistor that looks like it can be produced by almost standard semiconductor processing methods.

A team of researchers, from the International Center for Materials Nanoarchitectonics of National Institute for Materials Science (NIMS) and the Georgia Institute of Technology, have developed a dual-layered nanowire that comprises a silicon (Si) shell and a germanium (Ge) core.

 Schematic of a vertical transistor and an expanded view of its core-shell nanowire part. (

Full story: here

Wednesday, October 28, 2015

Imec FinFET to Vertical Nanowire FET Movie

Here is a cool video from Imec showing the transition from FinFET via horizontal Nanowires to ultimately vertical Nanowire channel transistors. The movie and the whole article is available in the Imec monthly magazine on page 6 (!preferred/1/package/69/pub/75/page/6)

Screendump showing the ultimate goal of integration III/V vertical nanowire transistors.
"Driven by the growing demand for increased communication and increased mobile and server data traffic, CMOS technologies will require continuous innovations in the field of ultra-low power operation, performance and density scaling. And this at an affordable cost. In this movie, we visualize the evolution of a FinFET architecture into the next technology generations: from tall Si fins and source/drain stressors over "

Monday, July 20, 2015

Nanowires from TU/e give ‘solar fuel cell’ efficiency a tenfold boost

As published by TU Eindhoven - A solar cell that produces fuel rather than electricity. Researchers at Eindhoven University of Technology (TU/e) and FOM Foundation today present a very promising prototype of this in the journal Nature Communications. The material gallium phosphide enables their solar cell to produce the clean fuel hydrogen gas from liquid water. Processing the gallium phosphide in the form of very small nanowires is novel and helps to boost the yield by a factor of ten. And does so using ten thousand times less precious material.

Array of nanowires gallium phosphide made with an electron microscope. Photo: Eindhoven University of Technology.

The electricity produced by a solar cell can be used to set off chemical reactions. If this generates a fuel, then one speaks of solar fuels – a hugely promising replacement for polluting fuels. One of the possibilities is to split liquid water using the electricity that is generated (electrolysis). Among oxygen, this produces hydrogen gas that can be used as a clean fuel in the chemical industry or combusted in fuel cells – in cars for example – to drive engines.

Solar fuel cell

To connect an existing silicon solar cell to a battery that splits the water may well be an efficient solution now but it is a very expensive one. Many researchers are therefore targeting their search at a semiconductor material that is able to both convert sunlight into an electrical charge and split the water, all in one; a kind of ‘solar fuel cell’. Researchers at TU/e and FOM see their dream candidate in gallium phosphide (GaP), a compound of gallium and phosphide that also serves as the basis for specific colored leds.

A tenfold boost

GaP has good electrical properties but the drawback that it cannot easily absorb light when it is a large flat surface as used in GaP solar cells. The researchers have overcome this problem by making a grid of very small GaP nanowires, measuring five hundred nanometers (a millionth of a millimeter) long and ninety nanometers thick. This immediately boosted the yield of hydrogen by a factor of ten to 2.9 percent. A record for GaP cells, even though this is still some way off the fifteen percent achieved by silicon cells coupled to a battery.

Ten thousand times less material

According to research leader and TU/e professor Erik Bakkers, it’s not simply about the yield – where there is still a lot of scope for improvement he points out: “For the nanowires we needed ten thousand less precious GaP material than in cells with a flat surface. That makes these kinds of cells potentially a great deal cheaper,” Bakkers says. “In addition, GaP is also able to extract oxygen from the water – so you then actually have a fuel cell in which you can temporarily store your solar energy. In short, for a solar fuels future we cannot ignore gallium phosphide any longer.”

Anthony Standing et al., Efficient water reduction with gallium phosphide nanowires, Nature Communications (17 July 2015)
DOI: 10.1038/ncomms8824

Thanks to TG Techno to for posting this one! (

Wednesday, July 8, 2015

MIT develops Supercapacitors from Niobium Nanowire Yarns for wearable electronics

As reported by MIT News : Wearable electronic devices for health and fitness monitoring are a rapidly growing area of consumer electronics; one of their biggest limitations is the capacity of their tiny batteries to deliver enough power to transmit data. Now, researchers at MIT and in Canada have found a promising new approach to delivering the short but intense bursts of power needed by such small devices.

The key is a new approach to making supercapacitors — devices that can store and release electrical power in such bursts, which are needed for brief transmissions of data from wearable devices such as heart-rate monitors, computers, or smartphones, the researchers say. They may also be useful for other applications where high power is needed in small volumes, such as autonomous microrobots.

The new approach uses yarns, made from nanowires of the element niobium, as the electrodes in tiny supercapacitors (which are essentially pairs of electrically conducting fibers with an insulator between). The concept is described in a paper in the journal ACS Applied Materials and Interfaces by MIT professor of mechanical engineering Ian W. Hunter, doctoral student Seyed M. Mirvakili, and three others at the University of British Columbia.

Here below is the abstract for the publication or you can continue reading the story from MIT News.

High-Performance Supercapacitors from Niobium Nanowire Yarns

Seyed M. Mirvakili, Mehr Negar Mirvakili, Peter Englezos, John D. W. Madden, and Ian W. Hunter

ACS Appl. Mater. Interfaces, 2015, 7 (25), pp 13882–13888
DOI: 10.1021/acsami.5b02327

The large-ion-accessible surface area of carbon nanotubes (CNTs) and graphene sheets formed as yarns, forests, and films enables miniature high-performance supercapacitors with power densities exceeding those of electrolytics while achieving energy densities equaling those of batteries.1−7 Capacitance and energy density can be enhanced by depositing highly pseudocapacitive materials such as conductive polymers on them.3,8−15 Yarns formed from carbon nanotubes are proposed for use in wearable supercapacitors.3,16 In this work, we show that high power, energy density, and capacitance in yarn form are not unique to carbon materials, and we introduce niobium nanowires as an alternative. These yarns show higher capacitance and energy per volume and are stronger and 100 times more conductive than similarly spun carbon multiwalled nanotube (MWNT) and graphene yarns.6,17−22 The long niobium nanowires, formed by repeated extrusion and drawing,17 achieve device volumetric peak power and energy densities of 55 MW·m–3 (55 W·cm–3) and 25 MJ·m–3 (7 mWh·cm–3), 2 and 5 times higher than that for state-of-the-art CNT yarns, respectively.3 The capacitance per volume of Nb nanowire yarn is lower than the 158 MF·m–3 (158 F·cm–3) reported for carbon-based materials such as reduced graphene oxide (RGO) and CNT wet-spun yarns,5 but the peak power and energy densities are 200 and 2 times higher, respectively.5 Achieving high power in long yarns is made possible by the high conductivity of the metal, and achievement of high energy density is possible thanks to the high internal surface area. No additional metal backing is needed, unlike for CNT yarns and supercapacitors in general, saving substantial space. As the yarn is infiltrated with pseudocapacitive materials such as poly(3,4-ethylenedioxythiophene) (PEDOT), the energy density is further increased to 10 MJ·m–3 (2.8 mWh·cm–3). Similar to CNT yarns, niobium nanowire yarns are highly flexible and show potential for weaving into textiles and use in wearable devices.

Friday, June 26, 2015

CVD of vertically aligned silicon nanowires in MEMS using silane as a precursor

Here is a very good and detailed paper on CVD of vertically aligned silicon nanowires in MEMS using silane as a precursor by researchers at Catalonia Institute for Energy Research (IREC), Institute of Microelectronics of Barcelona, and ETH Zurich. Pretty high aspect ratio - Open Access - enjoy!

Towards a full integration of vertically aligned silicon nanowires in MEMS using silane as a precursor

G Gadea, A Morata, J D Santos, D Dávila, C Calaza, M Salleras, L Fonseca and A Tarancón
G Gadea et al 2015 Nanotechnology 26 195302

Samples with R = 168 and tdip = 30 s grown during 60 min at 32 mTorr of silane pressure (2.5 Torr total pressure) at different growth temperatures: (a) 520 °C; (b) 630 °C; (c) and (d) 725 °C ((d) shows a 20° tilted view). In (a), (b), and (c) higher-magnification insets show the nanowires at their middle section for diameter comparison. The inset in (d) shows a higher magnification of the nanowire tips from sample (c).


Silicon nanowires present outstanding properties for electronics, energy, and environmental monitoring applications. However, their integration into microelectromechanical systems (MEMS) is a major issue so far due to low compatibility with mainstream technology, which complicates patterning and controlled morphology. This work addresses the growth of 〈111〉 aligned silicon nanowire arrays fully integrated into standard MEMS processing by means of the chemical vapor deposition–vapor liquid solid method (CVD–VLS) using silane as a precursor. A reinterpretation of the galvanic displacement method is presented for selectively depositing gold nanoparticles of controlled size and shape. Moreover, a comprehensive analysis of the effects of synthesis temperature and pressure on the growth rate and alignment of nanowires is presented for the most common silicon precursor, i.e., silane. Compared with previously reported protocols, the redefined galvanic displacement together with a silane-based CVD–VLS growth methodology provides a more standard and low-temperature (<650 °C) synthesis scheme and a compatible route to reliably grow Si nanowires in MEMS for advanced applications.

Wednesday, June 10, 2015

Researchers at Rice University make ultrasensitive conductivity measurements

Here is a very interesting report that might indeed be interesting to characterize ALD growth in-situ ultra fast at optical frequencies!

(Nanowerk News) Researchers at Rice University have discovered a new way to make ultrasensitive conductivity measurements at optical frequencies on high-speed nanoscale electronic components.The research at Rice's Laboratory for Nanophotonics (LANP) is described online in a new study in the American Chemical Society's journal ACS Nano ("Charge Transfer Plasmons: Optical Frequency Conductances and Tunable Infrared Resonances"). In a series of experiments, LANP researchers linked pairs of puck-shaped metal nanodisks with metallic nanowires and showed how the flow of current at optical frequencies through the nanowires produced "charge transfer plasmons" with unique optical signatures.

Linked pairs of nanodisks as seen with a scanning electron microscope. (Image: Fangfang Wen/Rice University)

Monday, June 8, 2015

IBM Zurich present III-V on silicon wafers breakthrough technology using ALD

IBM has done it - a method of depositing ultra-fast III-V nanowires suitable for transistor channels and other structures on silicon-on-insulator (SOI) substrates -  and for sure ALD was involved in one of the early crucial processing steps to create the template for TASE - Template Assisted Selective Epitaxy. 

"A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) " 

Check out the details below and in the Open Access paper!

Template-assisted selective epitaxy of III–V nanoscale devices for co-planar heterogeneous integration with Si (Open Access)

H. Schmid, M. Borg, K. Moselund, L. Gignac, C. M. Breslin, J. Bruley, D. Cutaia and H. Riel
Appl. Phys. Lett. 106, 233101 (2015); 

Schematic (a) and SEM images (b)–(d) illustrating stacking of Si and III-V NWs. (b) SEM image shows a tilted view of three stacked template structures. (c) SEM cross-section image of the Si NW stack and (d), TEM image of the GaAs NW stack (Appl. Phys. Lett. 106, 233101 (2015);

III–V nanoscale devices were monolithically integrated on silicon-on-insulator (SOI) substrates by template-assisted selective epitaxy (TASE) using metal organic chemical vapor deposition. Single crystal III–V (InAs, InGaAs, GaAs) nanostructures, such as nanowires, nanostructures containing constrictions, and cross junctions, as well as 3D stacked nanowires were directly obtained by epitaxial filling of lithographically defined oxide templates. The benefit of TASE is exemplified by the straightforward fabrication of nanoscale Hall structures as well as multiple gate field effect transistors (MuG-FETs) grown co-planar to the SOI layer. Hall measurements on InAs nanowire cross junctions revealed an electron mobility of 5400 cm2/V s, while the alongside fabricated InAs MuG-FETs with ten 55 nm wide, 23 nm thick, and 390 nm long channels exhibit an on current of 660 μA/μm and a peak transconductance of 1.0 mS/μm at VDS = 0.5 V. These results demonstrate TASE as a promising fabrication approach for heterogeneous material integration on Si.

SEM images illustrating epitaxial filling of complex nano structures. (a) Evolution of the growth during filling of three templates, each having a lithographically pre-defined constriction. (b) Formation of an InAs cross-junction for the later fabrication of a Hall structure. The InAs film thickness is 23 nm (Appl. Phys. Lett. 106, 233101 (2015);

The fabrication steps of TASE : a (100)-oriented SOI substrates (Soitec) with a device layer thickness of 25–50 nm were patterned using e-beam lithography and reactive ion etching. A 30-nm-thick SiO2 layer covering the entire structure was conformally deposited using atomic layer deposition (ALD) and annealed at 850 °C in Ar/H2. The SiO2 cap on one end of the Si structure was opened by patterning polymethylmethacrylate (PMMA) by e-beam lithography and buffered hydrofluoric acid (BHF) etching to expose the Si device layer. Next the Si was back-etched to the desired length using either XeF2 dry etching followed by tetramethylammoniumhydroxide (TMAH) wet etching or TMAH etching only, to result in well-defined {111} planes. The orientation of the {111} planes with respect to the channel direction was controlled by the alignment of the channel patterns. All structures reported here were patterned along the 〈110〉 direction. The as-prepared substrate was dipped in diluted (2.5%) HF to remove the native oxide on the exposed Si surfaces within the channels and was immediately loaded into the MOCVD reactor. Selective epitaxy of InGaAs was carried out using trimethylindium (TMIn), tertiarybutylarsine (TBAs), and trimethygallium (TMGa) at V/III ratio = 40 with TMIn/(TMIn+TMGa) = 0.5 at 580 °C. Chemical analysis was obtained from electron energy loss spectroscopy (EELS) analysis and indicated an In0.50Ga0.50As composition. InAs epitaxy was carried out at 520 °C using TMIn and TBAs with a V/III ratio = 80 and V/III ratio = 40 for the MuGFETs, respectively. Optionally, the dielectric template was removed after growth by wet etching in diluted HF, to expose the Si–III-V nano-structure on the SiO2 layer (BOX). 

Sunday, May 31, 2015

Epitaxial growth of GaN nanowires on metallic TiN by Paul-Drude-Institut, Berlin

Paul-Drude-Institut für Festkörperelektronik in Berlin has recently published a paper (below) on how to grow GaN Nanowires on TiN. From a silicon based semiconductor device perspective this is very interesting results since TiN can be used to make ohmic contact to silicon. For instance the is used in most DRAM Capacitor cells today where the word line is connected by a TiN/Ti/TiSi/Si ohmic contact. This technology was invented by Qimonda - The buried Word Line technology that was introduced at 65 nm and has been transferred to many other companies since then (Winbond, Micron, Elpida, ...). Or as the researchers at the Paul-Drude-Institut states:  

"The freedom to employ metallic substrates for the epitaxial growth of semiconductor nanowires in high structural quality may enable novel applications that benefit from the associated high thermal and electrical conductivity as well as optical reflectivity."

Epitaxial Growth of GaN Nanowires with High Structural Perfection on a Metallic TiN Film 

M. Wölz , C. Hauswald , T. Flissikowski , T. Gotschke , S. Fernández-Garrido , O. Brandt , H. T. Grahn , L. Geelhaar *, and H. Riechert 
Nano Lett., Article ASAP DOI: 10.1021/acs.nanolett.5b00251 
Publication Date (Web): May 22, 2015

Vertical GaN nanowires are grown in a self-induced way on a sputtered Ti film by plasma-assisted molecular beam epitaxy. Both in situ electron diffraction and ex situ ellipsometry show that Ti is converted to TiN upon exposure of the surface to the N plasma. In addition, the ellipsometric data demonstrate this TiN film to be metallic. The diffraction data evidence that the GaN nanowires have a strict epitaxial relationship to this film. Photoluminescence spectroscopy of the GaN nanowires shows excitonic transitions virtually identical in spectral position, line width, and decay time to those of state-of-the-art GaN nanowires grown on Si. Therefore, the crystalline quality of the GaN nanowires grown on metallic TiN and on Si is equivalent. The freedom to employ metallic substrates for the epitaxial growth of semiconductor nanowires in high structural quality may enable novel applications that benefit from the associated high thermal and electrical conductivity as well as optical reflectivity.

Thursday, May 28, 2015

Asenov claims Nanowire transistors (NWT) favourite to succeed FinFET at 5 nm

Nanowire transistors are the most likely successor to finfets and will scale to 5nm, says Professor Asen Asenov, Professor of Electrical Engineering at Glasgow University and CEO of Gold Standard Simulations (GSS) which specialises in the predictive simulation of nano-CMOS devices including statistical variability and reliability.

”While 16/14nm FinFETs are about to enter volume production at the major foundries, the next generation transistors suitable for 7nm CMOS and below are already on the drawing board,” says Asenov, “one of the best candidates “Gate all around” transistors, better known as nanowire transistors (NWT), have superior scaling properties compared to FinFETs and can be scaled to channel lengths of approximately 5nm. ”

Mobile charge distribution in a NWT with different cross-sections suitable for 7nm CMOS technology. Due to quantum mechanical confinement effects ‘strange’ patterns determine the Source' Drain' Gate' Spacer' Channel' positions of the current flow in the nanowire cross-section (Picure from GSS).

Friday, May 1, 2015

InAs Nanowire Transistors with Multiple Independent Wrap-Gate Segments

The Nanometer Structure Consortium (nmC) at, Lund University Sweden and School of Physics, University of New South Wales, Australia demonstrate a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments
A. M. Burke, D. J. Carrad, J. G. Gluschke, K. Storm, S. Fahlvik Svensson, H. Linke, L. Samuelson, and A. P. Micolich
Nano Lett., Article ASAP, DOI: 10.1021/nl5043243

Abstract Image

AN InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments (Graphical Abstracts Nano Lett., Article ASAP, DOI: 10.1021/nl5043243)

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

Friday, March 20, 2015

Sol Voltaics makes record-breaking III-V nanowire solar cell

As reported in Compund Semiconductor: Sol Voltaics, based in Lund, Sweden, has announced that it has doubled the previously reported world-record for photovoltaic (PV) conversion efficiency using a GaAs nanowire array (NWA).

As independently verified by Fraunhofer-ISE, Sol Voltaics has demonstrated a 1-sun conversion efficiency of 15.3 percent in a GaAs NWA solar cell, representing a significant milestone towards providing the solar industry with an efficiency boosting tandem film.

This is the highest efficiency reported to date in a III-V NWA solar cell, and twice the prior record for GaAs NWA technology. Control of the high density of surface states of native GaAs is essential for PV applications, and these results, says Sol Voltaics, prove that it has has resolved this challenge in the growth of solar cell nanowires.

"The efficiency of our GaAs nanowires is a critical component of our low cost film. The use of III-V materials in the PV industry has always been a goal but the costs have been prohibitive. Using Sol Voltaic's Aerotaxy nanowire production methodology allows our III-V film to be produced at competitive cost at efficiencies that are industry changing," said Erik Smith, CEO of Sol Voltaics. "We look forward to working with industrial partners on the integration of our technology on to silicon cells so they may make the leap to 27 percent efficiency and beyond."

GaAs has been used in performance-category solar modules for years because of its high conversion efficiencies. The challenge has always been its high cost relative to other solar materials.

The low cost Aerotaxy process invented by Sol Voltaics' founder and Lund University professor Lars Samuelson, reduces the amount of GaAs and other expensive materials required to generate electricity. Nanowires are created by suspending active materials in gases intermingled in precisely controlled environment. The suspended materials bond to form larger, uniform structures: nanowires are literally grown in space.

Aerotaxy generates nanowires within milliseconds, according to the company, and can produce them on a continuous basis at comparatively low temperatures.

The finished nanowire film can be integrated into solar panels or stored indefinitely. A 2012 paper published in Nature details how Samuelson and his team manufactured GaAs nanowires with Aerotaxy.

Magnus Heurlin, Martin H. Magnusson, David Lindgren, Martin Ek, L. Reine Wallenberg, Knut Deppert & Lars Samuelson

Nature 492, 90–94

Semiconductor nanowires are key building blocks for the next generation of light-emitting diodes1, solar cells2 and batteries3. To fabricate functional nanowire-based devices on an industrial scale requires an efficient methodology that enables the mass production of nanowires with perfect crystallinity, reproducible and controlled dimensions and material composition, and low cost. So far there have been no reports of reliable methods that can satisfy all of these requirements. Here we show how aerotaxy, an aerosol-based growth method4, can be used to grow nanowires continuously with controlled nanoscale dimensions, a high degree of crystallinity and at a remarkable growth rate. In our aerotaxy approach, catalytic size-selected Au aerosol particles induce nucleation and growth of GaAs nanowires with a growth rate of about 1micrometre per second, which is 20 to 1,000 times higher than previously reported for traditional, substrate-based growth of nanowires made of group III–V materials5, 6, 7. We demonstrate that the method allows sensitive and reproducible control of the nanowire dimensions and shape—and, thus, controlled optical and electronic properties—through the variation of growth temperature, time and Au particle size. Photoluminescence measurements reveal that even as-grown nanowires have good optical properties and excellent spectral uniformity. Detailed transmission electron microscopy investigations show that our aerotaxy-grown nanowires form along one of the four equivalent left fence111right fenceB crystallographic directions in the zincblende unit cell, which is also the preferred growth direction for III–V nanowires seeded by Au particles on a single-crystal substrate. The reported continuous and potentially high-throughput method can be expected substantially to reduce the cost of producing high-quality nanowires and may enable the low-cost fabrication of nanowire-based devices on an industrial scale.