Gartner says that 7nm will be delayed and 5nm will be pushed out ot 2023

10 nm FinFET may start to ship as early as end of 2016. However, according to a recent article by Mark Lapedus (at Semiconductor Engineering) Bob Johnson, an analyst at Gartner, projects that 7nm could get pushed out to 2020. "This, in turn, could impact the potential timing of 5nm, if the industry decides to move forward with the technology. “I assume 5nm will happen, but not by 2020,” Johnson said, adding that a viable 5nm process may not appear until the next decade, possibly 2023."

The slow down in scaling is not something new and has been seen for some time now. Above is a forecast presented at 2014 Semicon West with conclusions of the SEMI’s World Fab Forecast - Technology Node Transitions Slowing Below 32 nm. Her you can clearly see that the node transitions has paced slower since 28/32 nm.  The question now is then if the pace will come to a halt.

The current 3 main options for 5nm logic FETs are :

• Gate-All-Around FETs based on III/V Nanowires
• To extend FinFET
• Monolithic 3D and other 2.5D/3D IC technologies

It´s not only getting tight in FEOL but also in BEOL where major breakthroughs in Interconnects will also be need at 5nm. Read the full article here: http://semiengineering.com/will-5nm-happen/

So good the good news for all nanowire based nano electronic research - there is still time to make an impact on future sub 10 nm technologies! That is why I recommend you to visit NanoLund in Sweden and learn more about the leading edge research taking place at The Lund Nano Lab of Lund University. Lund Nano Lab is the latest addition among Swedish research and development laboratories for semiconductor material and devices. Inaugurated in 2007, Lund Nano Lab (LNL) offers a clean room space, equipment and expertise for cutting edge nanofabrication for fundamental research and device development. One of the missions of LNL, which is the open lab facility, is to provide research infrastructure and knowledge in nanofabrication and epitaxy to both academic users and start-up companies and.

Nanoelectronics at NanoLund

We study electronic devices based on novel semiconductor nanowire structures. The target of this subarea is to investigate new and improved devices, with an emphasis on future transistors. The devices are based on exotic semiconductor materials formed by bottom-up growth methods, high-k dielectric deposition and wrap-around gate processing.

Project areas:

• Tunneling-based heterostructure devices.
• Surface and transport properties of InAs nanowire transistors.
• GaN-based electronics.
• Multiple-method characterisation.