Samsung’s GAA Transistor, MBCFET™ aims at Reduced Size and Increased Performance

While chipmakers are struggling with the FinFET based chip production below 5 nm process nodes, Samsung has planned to opt for GAA (gate all around) architecture. Samsung’s GAA redesigns the transistor, making it more power-efficient and better-performing than the existing Multi Bridge Channel FET (MBCFET™) that utilize stacked nanosheets. 

 

Samsung’s patented MBCFET™ is formed as a nanosheet, allowing for a larger current and simpler device integration. It allows to reduce the operating voltage below 0.75 V that had been extremely difficult with FinFET. This yields to 50% less power consumption or 30% more performance at 45% less chip area compared to 7 nm FinFET technology. Also, Samsung's GAA technology is compatible with current FinFET production line that means the today's fab running on mature process tools and methodology can be utilized for GAA transistors. Here is the infographic to learn more about how Samsung’s GAA is advancing the future of semiconductor technology.

Source: Samsung LINK

Written by : Abhishekkumar Thakur and Jonas Sundqvist

 

Samsung will give insights to their 3nm CMOS technology at IEDM2018

The 64th IEDM conference will be held December 1-5, 2018 in San Francisco (LINK). This year Samsung will give insights to their 3nm CMOS technology that will feature the so calle gate-all-around (GAA) transistors. The GAA is trasistors ar realized by having channels made from horizontal layers of nanosheets that are completely surrounded by gate structures. 

Samsung has recently stated (LINK) that they have started wafer production on its new 7LPP node (FinFET). According to the press release the process uses EUV lithography technology and demonstrates that Samsung's Foundry can follow its roadmap reaching down to 3 nm.

 

 

Samsung Foundry Roadmap as shown at SFF Japan 2018.

 

Samsung refers to this architecture as a Multi-Bridge-Channel architecture, and claims "that it is highly manufacturable as it makes use of ~90% of the company’s existing FinFET fabrication technology, requiring only a few revised photomasks" (LINK). 

 

Paper #28.7, "3nm GAA Technology Featuring Multi-Bridge-Channel FET for Low-Power and High-Performance Applications," G. Bae et al, Samsung

 

 

What Transistors Will Look Like At 5nm by Mark LaPedus

As finFETs run out of steam after 7nm, what comes next? The debate is just beginning.

August 18th, 2016 - By: Mark LaPedus, Semiconductor Engineering

Chipmakers are currently ramping up 16nm/14nm finFET processes, with 10nm and 7nm just around the corner. The industry also is working on 5nm. TSMC hopes to deliver a 5nm process by 2020. GlobalFoundries, Intel and Samsung are doing R&D for that node.

But 5nm technology presents a multitude of unknowns and challenges. For one thing, the exact timing and specs of 5nm remain cloudy. Then, there are several technical and economic roadblocks. And even if 5nm happens, it’s likely that only a few companies will be able to afford it.

“My current assumption is that 5nm will happen, but it won’t hit high-volume manufacturing until after 2020,” said Bob Johnson, an analyst at Gartner. “If I were to guess, I’d say 2021 to 2022.”

Continue reading at Semiconductor Engineering: http://semiengineering.com/going-to-gate-all-around-fets/ 

I am happy to see that they are using horizontal rather than vertical integration of Nanowires since we have developed an ALE process to realize longitudinal splitting of nanowires at Lund Nano Lab : http://www.blog.baldengineering.com/2016/07/lund-nano-lab-to-present-new-maskless.html

So we could make 10 out of those 5 wires... without Lihorgraphy(!)

Gartner says that 7nm will be delayed and 5nm will be pushed out ot 2023

10 nm FinFET may start to ship as early as end of 2016. However, according to a recent article by Mark Lapedus (at Semiconductor Engineering) Bob Johnson, an analyst at Gartner, projects that 7nm could get pushed out to 2020. "This, in turn, could impact the potential timing of 5nm, if the industry decides to move forward with the technology. “I assume 5nm will happen, but not by 2020,” Johnson said, adding that a viable 5nm process may not appear until the next decade, possibly 2023."

The slow down in scaling is not something new and has been seen for some time now. Above is a forecast presented at 2014 Semicon West with conclusions of the SEMI’s World Fab Forecast - Technology Node Transitions Slowing Below 32 nm. Her you can clearly see that the node transitions has paced slower since 28/32 nm.  The question now is then if the pace will come to a halt.

The current 3 main options for 5nm logic FETs are :

• Gate-All-Around FETs based on III/V Nanowires
• To extend FinFET
• Monolithic 3D and other 2.5D/3D IC technologies

Imec presents successors to FinFET for 7nm and beyond at VLSI Technology Symposium 2015

Leuven (Belgium)– June 17, 2015 – At this week’s VLSI 2015 Symposium in Kyoto (Japan), imec reported new results on nanowire FETs and quantum-well FinFETs towards post-FinFET multi-gate device solutions. 

The Technology roadmap as presented recently by Imec at the EWMOVPE workshop in Lund, Sweden.

As the major portion of the industry adopts FinFETs as the workhorse transistor for 16nm and 14nm, researchers worldwide are looking into the limits of FinFETs and potential device solutions for the 7nm node and beyond. Two approaches, namely Gate-All-Around Nanowire (GAA NW) FETs, which offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels), which achieve high carrier mobility, are promising options. 

For the first time, imec demonstrated the integration of these novel device architectures with state-of-the-art technology modules like Replacement-Metal-Gate High-k (RMG-HK) and Self (Spacer)-Aligned Double-Patterned (SADP) dense fin structures. By building upon today’s advanced FinFET technologies, the work shows how post-FinFET devices can emerge, highlighting both new opportunities as well as complexities to overcome. 

Imec and its technology research partners demonstrated SiGe-channel devices with RMG-HK integration. Besides SiGe FinFET, a unique GAA SiGe nanowire channel formation during the gate replacement process has been demonstrated. The novel CMOS-compatible process converts fin channels to nanowires by sacrificial Si removal during the transistor gate formation. The process may even enable future heterogeneous co-integration of fins and nanowires, as well as Si and SiGe channels. The work also demonstrates that such devices and their unique processing can lead to a drastic 2x or more improvement in reliability (NBTI) with respect to Si FinFETs. 

Moreover, imec demonstrated Si GAA-NW FETs based on SOI with RMG-HK. The work compares junction-based and junction-less approaches and the role of gate work function for multi-Vt implementations. New insights into the improved reliability (PBTI) with junction-less nanowire devices have been gained.

Extending the heterogeneous channel integration beyond Si and SiGe, imec demonstrated for the first time strained Ge QW FinFETs by a novel Si-fin replacement fin technique integrated with SADP process. Our results show that combining a disruptive approach like fin replacement with advanced modules like SADF-fin, RMG-HK, direct-contacts can enable superior QW FinFETs. The devices set the record for published strained Ge pMOS devices, outperforming by at least 40% in drive current at matched off-currents.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, SK hynix, Sony and TSMC.