STMicroelectronics and CEA/Leti have been leading an effort in scaling FD-SOI for long now and have recently gotten some muscles in support by fabing it at Samsung (28nm) and Globalfoundries Fab1 in Dresden (22nm). I ran some sub 22 nm development LOTs for one of our customers some years ago and form an ALD high-k point of view this was a a piece of cake. I gave them the same recipe, adjusted the thickness slightly, as the other guys and they didn't complain. That is why I since then always follow news on FD-SOI - it´s such an underdog technology compared to bulk FinFET in terms of ecosystem support and investments but I like underdogs - or maybe rather medium sized dogs with a big dog attitude. Anyhow here is a recent feature article by GloFo on the topic that is worth reading:
It was the coolest transistor development in many a year. Rather than
continually squishing transistor parts closer and closer together, we
flipped it to vertical and celebrated the arrival of the FinFET.
Image courtesy GlobalFoundries
Which was great: it gave us a way to keep increasing performance in
many of the applications where the value lies in the speed of the
circuit. But after the initial party was over and we started picking up
the pointy party hats and nursing the hangovers with massive doses of
ibuprofen, we started looking at the bill. FinFET is nice, but it’s also
expensive. And, while we’re throwing stones, it’s also not so great for
analog and RF designers based on the quantized nature of the gate. You
can’t increase channel dimensions by 1.5 times; it’s either 1 or 2.
Rutger Wijburg announcing the investment for 22 nm FD-SOI investment at Fab1 in Dresden, Germany. (Picture by Computer-Oiger)
FinFET has been billed as the future of silicon, and Intel jumped on
it, meaning everyone else had to as well. But that pounding
morning-after headache is pretty strong, and there are folks wishing
they had an alternative to FinFET.
Full story here: http://www.eejournal.com/archives/articles/20160118-fdsoi/
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