A Non-FinFET Path to 10nm Globalfoundries’ FD-SOI Alternative

STMicroelectronics and CEA/Leti have been leading an effort in scaling FD-SOI for long now and have recently gotten some muscles in support by fabing it at Samsung (28nm) and Globalfoundries Fab1 in Dresden (22nm). I ran some sub 22 nm development LOTs for one of our customers some years ago and form an ALD high-k point of view this was a a piece of cake. I gave them the same recipe, adjusted the thickness slightly, as the other guys and they didn't complain. That is why I since then always follow news on FD-SOI - it´s such an underdog technology compared to bulk FinFET in terms of ecosystem support and investments but I like underdogs - or  maybe rather medium sized dogs with a big dog attitude. Anyhow here is a recent feature article by GloFo on the topic that is worth reading:

It was the coolest transistor development in many a year. Rather than continually squishing transistor parts closer and closer together, we flipped it to vertical and celebrated the arrival of the FinFET.

Image courtesy GlobalFoundries

Which was great: it gave us a way to keep increasing performance in many of the applications where the value lies in the speed of the circuit. But after the initial party was over and we started picking up the pointy party hats and nursing the hangovers with massive doses of ibuprofen, we started looking at the bill. FinFET is nice, but it’s also expensive. And, while we’re throwing stones, it’s also not so great for analog and RF designers based on the quantized nature of the gate. You can’t increase channel dimensions by 1.5 times; it’s either 1 or 2.

Rutger Wijburg announcing the investment for 22 nm FD-SOI investment at Fab1 in Dresden, Germany. (Picture by Computer-Oiger)

FinFET has been billed as the future of silicon, and Intel jumped on it, meaning everyone else had to as well. But that pounding morning-after headache is pretty strong, and there are folks wishing they had an alternative to FinFET.

Full story here: http://www.eejournal.com/archives/articles/20160118-fdsoi/

Improved gate oxide quality for PEALD TiN vs PVD TiN for FDSOI CMOS

Gate dielectric quality is critical for advanced device fabrication, especially for low power, low leakage devices. In a recent study MIT shows a improved gate oxide quality for PEALD TiN vs PVD TiN. Using an Oxford Instruments OpAL system for PEALD of TiN from  tetrakis(dimethylamido)titanium (TDMAT) and an H2/N2 plasma mixture as precursors and plasma magnetron sputtered TiN films deposited at 300 °C using an Electrotech Sigma system the investigation concluded that:

• FDSOI transistors fabricated with either gate deposition process showed similar electrostatic performance.
• Gate dielectric quality metrics were significantly better when PE-ALD TiN was used compared to plasma sputtered TiN.
• A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current.
• A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PEALD source.

The study was conducted in The MIT Lincoln Laboratory Microelectronics Laboratory. The Lab has a fully depleted silicon-on-insulator (FDSOI) CMOS circuit prototyping capability.

MIT Lincoln Laboratory occupies 75 acres (20 acres of which are MIT property) on the eastern perimeter of Hanscom Air Force Base, which is at the nexus of Lexington, Bedford, Lincoln, and Concord. The MIT property and most of the Laboratory’s facilities are within the Lexington town boundaries.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates (OPEN ACCESS)

Christopher J. Brennan, Christopher M. Neumann and Steven A. Vitale

J. Appl. Phys. 118, 045307 (2015); http://dx.doi.org/10.1063/1.4927517

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gatedeposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN.  A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

The MIT Lincoln Laboratory Microelectronics Laboratory is a state-of-the-art semiconductor research and fabrication facility supporting a wide range of Lincoln Laboratory programs. The 70,000-square-foot facility has 8100 square feet of class-10 and 10,000 square feet of class-100 cleanroom areas. The Lab has a fully depleted silicon-on-insulator (FDSOI) CMOS circuit prototyping capability

GLOBALFOUNDRIES Webinar: Extending Moore's Law with FD-SOI Technology

"Extending Moore's Law with FD-SOI Technology" is part of the GLOBALFOUNDRIES Technical Webinar Series. Jamie Schaeffer, Ph.D. explains how FDSOI (Fully Depleted Silicon On Insulator) technology is extending the life of Moore's Law.

Only available by this link : https://www.youtube.com/watch?v=7VmQlpXKtHE#t=100

It has previously been announced this year that Globalfoundries will entry FDSOI at 22 nm and today there will be a press conference in Dresden in front of the Bundeskanslerin Angela Merkels visit to the Dresden Fab tomorrow (Fab 1).

News & Analysis

GlobalFoundries’ FD-SOI Revolution

Junko Yoshida

6/23/2015 06:16 PM EDT 
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GRENOBLE, France — The appearance of Gerd Teepe, director and design engineering at GlobalFoundries, at a CEA-Leti-sponsored FD-SOI workshop here has confirmed, once again, rumors surrounding the company’s upcoming “big announcement” about FD-SOI.
Teepe offered, in broad strokes, GlobalFoundries' FD-SOI time schedule. While it was no formal announcement, his presentation implied the company’s oft-leaked but never confirmed big plans in FD-SOI.
Teepe came to Grenoble, ostensibly, to end the suspense.
He said, “We are developing 22nm FD-SOI process technology right now.” The plan is to qualify the process by early 2016 and start volume production by the end of 2016. Asked about what the company’s 22nm FD-SOI process entails, Teepe explained, “We are using STMicroelectronics’ 14nm FD-SOI in our frontend, while using 28nm FD-SOI in the backend.”

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