Improved gate oxide quality for PEALD TiN vs PVD TiN for FDSOI CMOS

Gate dielectric quality is critical for advanced device fabrication, especially for low power, low leakage devices. In a recent study MIT shows a improved gate oxide quality for PEALD TiN vs PVD TiN. Using an Oxford Instruments OpAL system for PEALD of TiN from  tetrakis(dimethylamido)titanium (TDMAT) and an H2/N2 plasma mixture as precursors and plasma magnetron sputtered TiN films deposited at 300 °C using an Electrotech Sigma system the investigation concluded that:

• FDSOI transistors fabricated with either gate deposition process showed similar electrostatic performance.
• Gate dielectric quality metrics were significantly better when PE-ALD TiN was used compared to plasma sputtered TiN.
• A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current.
• A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PEALD source.

The study was conducted in The MIT Lincoln Laboratory Microelectronics Laboratory. The Lab has a fully depleted silicon-on-insulator (FDSOI) CMOS circuit prototyping capability.

MIT Lincoln Laboratory occupies 75 acres (20 acres of which are MIT property) on the eastern perimeter of Hanscom Air Force Base, which is at the nexus of Lexington, Bedford, Lincoln, and Concord. The MIT property and most of the Laboratory’s facilities are within the Lexington town boundaries.

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates (OPEN ACCESS)

Christopher J. Brennan, Christopher M. Neumann and Steven A. Vitale

J. Appl. Phys. 118, 045307 (2015); http://dx.doi.org/10.1063/1.4927517

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gatedeposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN.  A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

The MIT Lincoln Laboratory Microelectronics Laboratory is a state-of-the-art semiconductor research and fabrication facility supporting a wide range of Lincoln Laboratory programs. The 70,000-square-foot facility has 8100 square feet of class-10 and 10,000 square feet of class-100 cleanroom areas. The Lab has a fully depleted silicon-on-insulator (FDSOI) CMOS circuit prototyping capability