Showing posts with label beyond CMOS. Show all posts
Showing posts with label beyond CMOS. Show all posts

Thursday, January 25, 2018

High Dielectric Constant Materials for Nanoscale Devices and Beyond

Here is a nice review on the introduction of high-k materials in the semiconductor industry and a future outlook by Prof. Hiroshi Iwai at Tokyo and Prof. Akira Toriumi Institute of Technology and their partner Prof. Durga Misra at New Jersey Institute of Technology. Thank you for sharing this one Rob Clark! The paper is part of a winter special issue in Interface (by ECS) with focus on "Importance of dielectric science"  and is free for download.

The authors conclude that:
  • The step coverage advantage of atomic layer deposition (ALD and is possible for, high‑k migration to FinFET CMOS technology.
  • The use of high‑k on new semiconductor substrates such as III-V, Ge and 2D materials is currently being investigated and faces many challenges. 
  • The discovery of ferroelectric properties of HfO2 makes it viable for more potential applications.

High Dielectric Constant Materials for Nanoscale Devices and Beyond
Hiroshi Iwai, Akira Toriumi and Durga Misra

Electrochem. Soc. Interface Winter 2017 volume 26, issue 4, 77-81

Abstract: Tremendous progress of CMOS integrated circuits have been conducted by the down-scaling or the miniaturization of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Ten years, ago, the huge direct-tunneling gate leakage current through the thin gate SiO2 film of 1 nm thickness made it impossible to further scale-down the MOSFETs, and replacing the SiO2 by HfO2-based higher-dielectric constant (high-k) material was the solution. In this paper, the history of high-k gate insulator film development and two topics from recent research results regarding ferroelectricity and reliability are described.

Tuesday, August 22, 2017

Woah - Hafnium oxide as gate dielectric scales also in the 2D world

Hafnium oxide high-k dielectrics deposited by atomic layer deposition have been used in DRAM since 2004 (Samsung 90 nm) and 2007 in high performance CMOS logic (Intel 45 nm). Later the DRAM high-k dielectric was replaced by a zirconium oxide based material but for logic hafnium oxide has remained the material of choice for the high-k metal gate stack by toping off the native oxide of silicon with its higher k-value. Hafnium oxide even survived the transition to narrow 3D FinFET devices and is also the main contender for silicon based Nano Wire FETs. However, recent research in alternative 2D channel materials such as graphene, molybdenum disulfide and others has created a totally new situation where hafnium oxide finds it difficult to compete as the material of choice for the gate stack dielectric. 

Until now that is, because just recently some clever researchers at Stanford has presented an new all hafnium channel and dielectric combo using hafnium diselenide and the natural native oxide of that - ta da - hafnium oxide. Apparently the zirconium version is also brought into play but let us see about that...

You can read all about it in this online article published by Stanford, which also leads you to the original scientific references and journal publications.

New ultrathin semiconductor materials exceed some of silicon’s ‘secret’ powers, Stanford engineers find

The next generation of feature-filled and energy-efficient electronics will require computer chips just a few atoms thick. For all its positive attributes, trusty silicon can’t take us to these ultrathin extremes.

Now, electrical engineers at Stanford have identified two semiconductors – hafnium diselenide and zirconium diselenide – that share or even exceed some of silicon’s desirable traits, starting with the fact that all three materials can “rust.”

TEM cross-section of an experimental chip, the bands of black and white reveal alternating layers of hafnium diselenide – an ultrathin semiconductor material – and the hafnium dioxide insulator. (Image credit: Michal Mleczko)

Tuesday, May 17, 2016

Imec Expands its Silicon Platform for Quantum Computing Applications

Leuven (Belgium) – May 17, 2016 – At the Quantum Europe conference, taking place in Amsterdam, Belgian’s nanoelectronincs research center imec announced today that it is ramping-up its R&D activities focused on quantum computing. Imec will implement qubits and supporting nanoelectronic functionality for quantum computing, leveraging its advanced silicon (Si) platform that was established within the framework of its industrial affiliation program with additional support from the EU through e.g. ECSEL projects SENATE and TAKE-5. 

Widely seen as a possible solution to complex computing problems which are intractable on classical computers, quantum computing uses quantum physics to create and manipulate quantum states within electronic devices (qubits) to enhance the performance over that of existing, ‘classical’ approaches. Of the many device proposals for qubit implementation, the ones compatible with existing Si technology will provide the most viable solution for interfacing with the outside world.

The Imec Fab with all necessary 300mm equipment to allow advanced sub-10nm CMOS R&D (
The goal of imec’s initiative is to establish a bridge between the most advanced transistor technology and emerging quantum technology options, representing a natural extension of imec’s Si platform. This will ensure routes to demonstrate the quantum computing functionality compatible with industries’ platform technologies. Assuming a key position in the quantum technologies ecosystem, imec will support the transition of new quantum technologies, from the physics lab to technology feed into the supply chain. Imec’s platform will help translate laboratory demonstrators into commercial products. It will be open for universities, SMEs and industrial partners of imec’s quantum technologies programs.

“The coming decades will be characterized by a wave of quantum technology based applications, ranging from communication, simulation and sensing, to computation. However, to enable this, the industry will need technical support to adopt and to integrate these new technologies into products and services”, stated Jo De Boeck, CTO at imec. “ Imec’s industry relevant Si platform for the advanced technology nodes, is currently used to screen technology options for the 5nm nodes and beyond. The same platform is hence the ideal basis to start implementing quantum devices as quantum effects are becoming the starting point of developing a quantum platform.”

Thursday, March 10, 2016

Atomic Layer Lithography turns ALD into an angstrom-resolution gap-forming method

Here is a really cool paper on Atomic Layer Lithography! The method is a combination of "atomic layer lithography, which turns atomic layer deposition (ALD) into an angstrom-resolution gap-forming method" The combination of these two powerful methods can create ultrasmall coaxial nanocavities at extreme densities over an entire wafer, opening up the door to devices with sub-10 nm gaps"

High-Throughput Fabrication of Resonant Metamaterials with Ultrasmall Coaxial Apertures via Atomic Layer Lithography

Daehan Yoo, Ngoc-Cuong Nguyen, Luis Martin-Moreno, Daniel A. Mohr, Sol Carretero-Palacios, Jonah Shaver, Jaime Peraire, Thomas W. Ebbesen, and Sang-Hyun Oh

Nano Lett., 2016, 16 (3), pp 2040–2046 DOI: 10.1021/acs.nanolett.6b00024

Figure from graphical abstract used with permission (Account #: 3000915597)
We combine atomic layer lithography and glancing-angle ion polishing to create wafer-scale metamaterials composed of dense arrays of ultrasmall coaxial nanocavities in gold films. This new fabrication scheme makes it possible to shrink the diameter and increase the packing density of 2 nm-gap coaxial resonators, an extreme subwavelength structure first manufactured via atomic layer lithography, both by a factor of 100 with respect to previous studies. We demonstrate that the nonpropagating zeroth-order Fabry-Pérot mode, which possesses slow light-like properties at the cutoff resonance, traps infrared light inside 2 nm gaps (gap volume ∼ λ3/106). Notably, the annular gaps cover only 3% or less of the metal surface, while open-area normalized transmission is as high as 1700% at the epsilon-near-zero (ENZ) condition. The resulting energy accumulation alongside extraordinary optical transmission can benefit applications in nonlinear optics, optical trapping, and surface-enhanced spectroscopies. Furthermore, because the resonance wavelength is independent of the cavity length and dramatically red shifts as the gap size is reduced, large-area arrays can be constructed with λresonance ≫ period, making this fabrication method ideal for manufacturing resonant metamaterials.

Tuesday, February 16, 2016

A nanolaser for fast and efficient data processing with light from TU München

As reported by TU Munich in EurekAlert!: Physicists at the Technical University of Munich (TUM) have developed a nanolaser, a thousand times thinner than a human hair. Thanks to an ingenious process, the nanowire lasers grow right on a silicon chip, making it possible to produce high-performance photonic components cost-effectively. This will pave the way for fast and efficient data processing with light in the future.

"Today already, transistors are merely a few nanometers in size. Further reductions are horrendously expensive," says Professor Jonathan Finley, Director of the Walter Schottky Institute at TUM. "Improving performance is achievable only by replacing electrons with photons, i.e. particles of light."

This news release is available in German.


Monolithically Integrated High-beta Nanowire Lasers on Silicon
B. Mayer, L. Janker, B. Loitsch, J. Treu, T. Kostenbader, S. Lichtmannecker, T. Reichert, S. Morkötter, M. Kaniber, G. Abstreiter, C. Gies, G. Koblmüller, and J. J. Finley;
Nano Letters, 2016, 16 (1), pp 152-156 - DOI: 10.1021/acs.nanolett.5b03404

Coaxial GaAs-AlGaAs core-multishell nanowire lasers with epitaxial Gain control
T. Stettner, P. Zimmermann, B. Loitsch, M. Döblinger, A. Regler, B. Mayer, J. Winnerl, S. Matich, H. Riedl, M. Kaniber, G. Abstreiter, G. Koblmüller, and J. J. Finley;
Applied Physics Letters, 108, 011108 (2016) - DOI: 10.1063/1.4939549

Continuous wave lasing from individual GaAs-AlGaAs core-shell nanowires
B. Mayer, L. Janker, D. Rudolph, B. Loitsch, T. Kostenbader, Abstreiter, G. Koblmüller, and J. J. Finley; Applied Physics Letters 108, Vol. 8, to appear on Feb. 22nd (2016)


Saturday, February 13, 2016

ALD HfO2 HKMG FETs on CVD mono layer graphene channels on 200 mm glass wafers by Samsung

Samsung Advanced Institute of Technology and Samsung-SKKU Graphene/2D Center showcases ALD HfO2 high-k transistors on mono layer graphene channels using 200 mm glass wafers. The ALD Process is TEMAHf/H2O running at 200 C and they achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors.
Check out the free to down load Nature Scientific Report below.

SAIT (Samsung Advanced Institute of Technology)

Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors. 

Seong-Jun Jeong, Yeahyun Gu, Jinseong Heo, Jaehyun Yang, Chang-Seok Lee, Min-Hyun Lee, Yunseong Lee, Hyoungsub Kim, Seongjun Park & Sungwoo Hwang
Sci. Rep. 6, 20907; doi: 10.1038/srep20907 (2016).

(a) Optical image of the MOG-FET arrays fabricated on a 6″ Si wafer and a schematic illustration showing the structure of the MOG-FET device. (b) Optical microscope image of a fabricated MOG-FET unit device. (c) Cross sectional TEM image showing the HfO2 gate dielectric layer with a thickness of ~5 nm (including the seed layer converted to a HfO2 layer) on monolayered graphene. (d) Statistical distribution of the sheet resistance of a monolayered graphene before and after the ALD of HfO2 with and without an e-beam-evaporated Hf seed layer. Representative electrical characteristics measured from the fabricated MOG-FET devices: (e) gate dielectric leakage current, (f) gate capacitance as a function of the frequency, and (g) transfer curve (ID-VG). (Sci. Rep. 6, 20907; doi: 10.1038/srep20907 (2016)., Creative Commons Attribution 4.0 International License)

The downscaling of the capacitance equivalent oxide thickness (CET) of a gate dielectric film with a high dielectric constant, such as atomic layer deposited (ALD) HfO2, is a fundamental challenge in achieving high-performance graphene-based transistors with a low gate leakage current. Here, we assess the application of various surface modification methods on monolayer graphene sheets grown by chemical vapour deposition to obtain a uniform and pinhole-free ALD HfO2 film with a substantially small CET at a wafer scale. The effects of various surface modifications, such as N-methyl-2-pyrrolidone treatment and introduction of sputtered ZnO and e-beam-evaporated Hf seed layers on monolayer graphene, and the subsequent HfO2 film formation under identical ALD process parameters were systematically evaluated. The nucleation layer provided by the Hf seed layer (which transforms to the HfO2 layer during ALD) resulted in the uniform and conformal deposition of the HfO2 film without damaging the graphene, which is suitable for downscaling the CET. After verifying the feasibility of scaling down the HfO2 thickness to achieve a CET of ~1.5 nm from an array of top-gated metal-oxide-graphene field-effect transistors, we fabricated graphene heterojunction tunnelling transistors with a record-low subthreshold swing value of <60 mV/dec on an 8″ glass wafer.

Friday, February 5, 2016

The view by Intel on Moore`s Law and Beyond cmos

Here is an interesting article in EE Times on the future of Moore`s law in the view of Intel’s top fab executive, speaking to an audience of chip designers:

 “The economics of Moore’s Law are sound if we focus on reducing cost per transistor,” William Holt told about 3,000 attendees of the International Solid-State Circuits Conference (ISSCC) here. But “beyond CMOS we’ll see changes in everything, probably even in computer architecture,” he said.

Full article: